[0001] This invention relates to a transversal filter for use in a waveform equalization
circuit in a digital communication system and, more particularly, to a transversal
filter of a parallel processing type.
[0002] In general, the transversal filter is used in a waveform shaping filter such as the
waveform equalization circuit in the digital communication system or an interference
canceller. The transversal filter has been digitized and put to practical use due
to miniaturization of the device, low power consumption, and adjustmentless. In addition,
in order to be operable at a high speed, it has been made a proposal to make a plurality
of transversal filters process in parallel to construct the transversal filter of
the parallel processing type. Such a transversal filter of the parallel processing
type has been disclosed, for example, in Japanese Unexamined Patent Prepublication
No. 190033/90.
[0003] A conventional transversal filter is supplied with an input signal having an input
data rate. The input signal may be a baseband digital signal which is obtained by
demodulating and decision a digital modulated signal. The transversal filter filters
the input signal into an output signal in response to first through J-th tap gains,
where J represents a first positive integer which is not less than two. The output
signal also has an output data rate equal to the input data rate. The transversal
filter comprises a delay circuit which has first through J-th taps. The input signal
is supplied to the delay circuit. The delay circuit comprises first through (J-l)-th
delay units each of which is placed between two taps of the first through the J-th
taps. Each of the first and the (J-l)-th delay units provides a unit delay which is
substantially equal to a reciprocal of the input data rate. The first through the
J-th taps of the delay circuit produce first through J-th tap signals, respectively.
[0004] The first through the J-th tap signals are supplied to first and second latch circuits.
The first latch circuit latches the first through the J-th tap signals at each odd
time slot of the input signal and holds these signals during a time duration corresponding
to two time slots to produce first through J-th primary latched signals. Likewise,
the second latch circuit latches the first through the J-th tap signals at each even
time slot of the input signal and holds these signals during the time duration corresponding
to the two time slots to produce first through J-th subsidiary latched signals.
[0005] The first through the J-th primary latched signals are supplied to a first calculation
circuit. The first calculation circuit comprises first through J-th primary multiplying
circuits and a first adding circuit. The first through the J-th primary multiplying
circuits are supplied with the first through the J-th primary latched signals. The
first through the J-th tap gains are supplied to the first through the J-th primary
multiplying circuits, respectively. The first through the J-th primary multiplying
circuits multiplies the first through the J-th primary latched signals by the first
through the J-th tap gains to produce first through J-th primary product signals,
respectively. The first through the J-th primary product signals are supplied to the
first adding circuit. The first adding circuit adds up J terms of the first through
the J-th primary product signals to produce a first addition result signal indicative
of a first addition result of the J terms.
[0006] Likewise, the first through the J-th subsidiary latched signals are supplied to a
second calculation circuit. The second calculation circuit comprises first through
J-th subsidiary multiplying circuits and a second adding circuit. The first through
the J-th subsidiary multiplying circuits are supplied with the first through the J-th
subsidiary latched signals. The first through the J-th tap gains are supplied to the
first through the J-th subsidiary multiplying circuits, respectively. The first through
the J-th subsidiary multiplying circuits multiply the first through the J-th subsidiary
latched signals by the first through the J-th tap gains to produce first through J-th
subsidiary product signals, respectively. The first through the J-th subsidiary product
signals are supplied to the second adding circuit. The second adding circuit adds
up J terms of the first through the J-th subsidiary product signals to produce a second
addition result signal indicative of a second addition result of the J terms.
[0007] The first and the second addition result signals are supplied to a parallel-serial
converter. The parallel-serial converter carries out a parallel-serial conversion
on or couples the first and the second addition result signals to produce a serial
converted signal as the output signal.
[0008] As apparent from the above description, the transversal filter produces the output
signal which is equalized thereby. In the conventional transversal filter, the first
and the second latch circuits distribute input elements of the input signal into the
first through the J-th primary latched signals and the first through the J-th subsidiary
latched signals at alternative timings. In other words, each of the first and the
second latch circuits serves as a serial-parallel converter for converting the input
signal into J latched signals each of which has a data rate equal to a half times
as large as the input data signal of the input signal. Accordingly, the first and
the second calculation circuits carry out the parallel processing at a low operational
speed which is equal to a half of the output data rate of the output signal. However,
each of the first through the (J-l)-th delay units must carry out a delay operation
at an operational speed equal to the input data rate of the input signal. As a result,
the conventional transversal filter is defective in that the input data rate of the
input signal and the operational speed of the transversal filter are restricted by
the operational speed of the first through the (J-l)-th delay units.
[0009] It is therefore an object of this invention to provide a transversal filter capable
of processing an input signal of high data rate.
[0010] It is another object of this invention to provide a transversal filter of the type
described, which is operable at a high speed.
[0011] Other objects of this invention will become clear as the description proceeds.
[0012] On describing the gist of an aspect of this invention, it is possible to understand
that a transversal filter filters an input signal into an output signal in response
to first through J-th tap gains, where J represents a first positive integer which
is not less than two. The input signal has an input data rate while the output signal
has an output data rate which is equal to the input data rate.
[0013] According to the above-mentioned aspect of this invention, the above-understood transversal
filter comprises a serial-parallel converter, supplied with the input signal, for
converting the input signal into first through M-th parallel converted signals, where
M represents a second positive integer which is not less than two. Connected to the
serial-parallel converter, a delay circuit has first through L-th taps, where L represents
a third positive integer which is greater than the first positive integer J. The delay
circuit comprises a plurality of delay units each of which is connected between two
taps selected from the first through the L-th taps. Each of the delay units provides
M times a unit delay which substantially equal to a reciprocal of the input data rate.
The first through the L-th taps of the delaying circuit produce first through L-th
tap signals, respectively. Each of first through M-th calculation circuits is supplied
with the first through the J-th tap gains and J tap signals selected from the first
through the L-th tap signals. The first through the M-th calculation circuits carry
out a calculation operation on the J tap signals using the first through the J-th
tap gains to produce first through M-th calculation result signals, respectively.
Connected to the first through the M-th calculation circuits, a coupling circuit couples
the first through the M-th calculation result signals to produce the output signal.
[0014] On describing the gist of a different aspect of this invention, it is possible to
understand that a transversal filter filters an input signal into an output signal
in response to first through J-th tap gains, where J represents a first positive integer
which is not less than two. The input signal has an input data rate while the output
signal has an output data rate which is equal to a half of the input data rate.
[0015] According to the different aspect of this invention, the afore-understood transversal
filter comprises a serial-parallel converter, supplied with the input signal, for
converting the input signal into first through M-th parallel converted signals, where
M represents a second positive integer which is not less than two. Connected to the
serial-parallel converter, a delay circuit has first through L-th taps, where L represents
a third positive integer which is greater than the first positive integer J. The delay
circuit comprises a plurality of delay units each of which is connected between two
taps selected from the first through L-th taps. Each of the delay units provides M
times a unit delay which substantially equal to a reciprocal of the input data rate.
The first through L-th taps of the delaying circuit produce first through L-th tap
signals, respectively. Each of the first through M-th latch circuits is supplied with
J tap signals selected from the first through the L-th tap signals. Each of the first
through the M-th latch circuits latches the J tap signals and holding the J tap signals
during a time duration which substantially equal to twice a reciprocal of the output
data rate to produce first through J-th latch signals. First through M-th calculation
circuits are connected to the first through the M-th latch circuits, respectively.
Each of the first through the M-th calculation circuits is supplied with the first
through the J-th tap gains. The first through the M-th calculation circuits carrying
out a calculation operation on the first through the J-th latch signals using the
first through the J-th tap gains to produce first through M-th calculation result
signals, respectively. Connected to the first through the M-th calculation circuits,
a coupling circuit couples the first through the M-th calculation result signals to
produce the output signal.
Brief Description of the Drawing:
[0016]
Fig. 1 is a block diagram of a conventional transversal filter;
Fig. 2 shows a time chart for use in describing an operation of the conventional transversal
filter illustrated in Fig. 1;
Fig. 3 is a block diagram of a transversal filter according to a first embodiment
of this invention;
Fig. 4 shows a time chart for use in describing an operation of the transversal filter
illustrated in Fig. 3;
Fig. 5 is a block diagram of a transversal filter according to a second embodiment
of this invention;
Fig. 6 shows a time chart for use in describing an operation of the transversal filter
illustrated in Fig. 5;
Fig. 7 is a block diagram of a modified serial-parallel converter into which a serial-parallel
converter for use in the transversal filter illustrated in Fig. 3 is modified; and
Fig. 8 shows a time chart for use in an operation of the modified serial-parallel
converter illustrated in Fig. 7.
Description of the Preferred Embodiments:
[0017] Referring to Fig. 1, a conventional transversal filter of a parallel processing type
will be described at first in order to facilitate an understanding of the present
invention. The illustrated transversal filter is a three-tap transversal filter supplied
with an input signal IN. In the example being illustrated, the input signal IN has
an input data rate and is a digital signal having waveform shaped. The input signal
IN may be a baseband digital signal which is obtained by demodulating and decision
a digital modulated signal which is transmitted at a predetermined modulation rate.
[0018] The three-tap transversal filter filters the input signal IN into an output signal
OUT in response to first through J-th controllable tap gains, where J represents a
first positive integer which is not less than two. In the example being illustrated,
the first positive integer J is equal to three and the three-tap transversal filter
therefore responds to the first through the third tap gains which may be specified
by C₋₁, C₀, and C₁. The output signal OUT has an output data rate equal to the input
data rate. The three-tap transversal filter comprises a delay circuit 10' which has
first through third taps 11', 12', and 13'. The second tap 12' may be called a central
tap. The first and the third taps 11' and 13' are depicted on the lefthand and the
righthand sides of the central tap 12'. The first and the third taps 11' and 13' may
be referred to as first and second additional taps.
[0019] The input signal IN is supplied to the delay circuit 10'. The delay circuit 10' comprises
first and second delay units 16' and 17' which are placed between the first and the
second taps 11' and 12' and between the second and the third taps 12' and 13', respectively.
Each of the first and the second delay units 16' and 17' provides a unit delay which
is substantially equal to a reciprocal of the input data rate. The input signal IN
is delivered to the first tap 11' as a first tap signal and successively delayed by
the first and the second delay units 16' and 17' to be produced as second and third
tap signals which are sent to the second and the third taps 12' and 13', respectively.
[0020] Let the first through the third taps 11', 12', and 13' be specified by consecutive
numbers of (-1), 0, and (+1), respectively, taking the successive delays into consideration.
In this connection, the first tap signal appearing as the (-1) tap 11' may be specified
by D
n+1. Likewise, the second and the third tap signals may be specified by D
n and D
n-1, respectively. Since the first tap signal D
n+1 is identical with the input signal IN with no delay, it may be called a zeroth delayed
signal. Likewise, the second and the third tap signals D
n and D
n-1 may be referred to as first and second delay signals, respectively. At any rate,
the delay circuit 10' produces the zeroth through the second delayed signals D
n+1, D
n, and D
n-1.
[0021] The zeroth through the second delayed signals D
n+1, D
n, and D
n-1 are supplied to first and second latch circuits 21 and 22. The first latch circuit
21 latches the zeroth through the second delayed signals D
n+1, D
n, and D
n-1 at each odd time slot of the input signal IN and holds these signals during a time
duration corresponding to two time slots to produce first through third primary latched
signals D
2m+1, D
2m, and D
2m-1. Likewise, the second latch circuit 22 latches the zeroth through the second delayed
signals D
n+1, D
n, and D
n-1 at each even time slot of the input signal IN and holds these signals during the
time duration corresponding to the two time slots to produce first through third subsidiary
latched signals D
2m+2, D
2m+1, and D
2m.
[0022] The first through the third primary latched signals D
2m+1, D
2m, and D
2m-1 are supplied to a first calculation circuit 31. The first calculation circuit 31
carries out a calculation operation on the first through the third primary latched
signals D
2m+1, D
2m, and D
2m-1 using the first through the third tap gains C₋₁, C₀, and C₁ to produce a first calculation
result signal. The first calculation circuit 31 comprises first through third primary
multiplying circuits 311, 312, and 313 and a first adding circuit 314.
[0023] The first through the third primary multiplying circuits 311 to 313 are supplied
with the first through the third primary latched signals D
2m+1, D
2m, and D
2m-1. The first through the third tap gains C₋₁, C₀, and C₁ are supplied to the first
through the third primary multiplying circuits 311 to 313, respectively. The first
primary multiplying circuit 311 multiplies the first primary latched signal D
2m+1 by the first tap gain C₋₁ to produce a first primary product signal indicative of
a product of the first primary latched signal D
2m+1 and the first tap gain C₋₁. The second primary multiplying circuit 312 multiplies
the second primary latched signal D
2m by the second tap gain C₀ to produce a second primary product signal indicative of
a product of the second primary latched signal D
2m and the second tap gain C₀. The third primary multiplying circuit 313 multiplies
the third primary latched signal D
2m-1 by the third tap gain C₁ to produce a third primary product signal indicative of
a product of the third primary latched signal D
2m-1 and the third tap gain C₁. The first through the third primary product signals are
supplied to the first adding circuit 314. The first adding circuit 314 adds up three
terms of the first through the third primary product signals to produce, as the first
calculation result signal, a first addition result signal D
2m' indicative of a first addition result of the three terms.
[0024] Likewise, the first through the third subsidiary latched signals D
2m+2, D
2m+1, and D
2m are supplied to a second calculation circuit 32. The second calculation circuit 32
carries out a calculation operation on the first through the third subsidiary latched
signals D
2m+2, D
2m+1, and D
2m using the first through the third tap gains C₋₁, C₀, and C₁ to produce a second calculation
result signal. The second calculation circuit 32 comprises first through third subsidiary
multiplying circuits 321, 322, and 323 and a second adding circuit 324.
[0025] The first through the third subsidiary multiplying circuits 321 to 323 are supplied
with the first through the third subsidiary latched signals D
2m+2, D
2m+1, and D
2m. The first through the third tap gains C₋₁, C₀, and C₁ are supplied to the first
through the third subsidiary multiplying circuits 321 to 323, respectively. The first
subsidiary multiplying circuit 321 multiplies the first subsidiary latched signal
D
2m+2 by the first tap gain C₋₁ to produce a first subsidiary product signal indicative
of a product of the first subsidiary latched signal D
2m+2 and the first tap gain C₋₁. The second subsidiary multiplying circuit 322 multiplies
the second subsidiary latched signal D
2m+1 by the second tap gain C₀ to produce a second subsidiary product signal indicative
of a product of the second subsidiary latched signal D
2m+1 and the second tap gain C₀. The third subsidiary multiplying circuit 323 multiplies
the third subsidiary latched signal D
2m by the third tap gain C₁ to produce a third subsidiary product signal indicative
of a product of the third subsidiary latched signal D
2m and the third tap gain C₁. The first through the third subsidiary product signals
are supplied to the second adding circuit 324. The second adding circuit 324 adds
up three terms of the first through the third subsidiary product signals to produce,
as the second calculation result signal, a second addition result signal D
2m+1' indicative of a second addition result of the three terms.
[0026] The first and the second addition result signals D
2m' and D
2m+1' are supplied to a parallel-serial converter 35. The parallel-serial converter 35
carries out a parallel-serial conversion on or couples the first and the second addition
result signals D
2m' and D
2m+1' to produce a serial converted signal D
n' as the output signal OUT.
[0027] Referring to Fig. 2 in addition to Fig. 1, description will be directed to operation
of the conventional transversal filter illustrated in Fig. 1. First through ninth
input time slots are indicated along a first or top line in Fig. 2 by numerals 1 through
9.
[0028] The input signal IN or the zeroth delayed signal D
n+1 is indicated along a second line. Third and fourth lines show the first and the second
delayed signals D
n and D
n-1, respectively. Fifth through seventh lines show the first through the third primary
latched signals D
2m+1, D
2m, and D
2m-1, respectively. Eighth through tenth lines show the first through the third subsidiary
latched signals D
2m+2, D
2m+1, and D
2m, respectively. Eleventh and twelfth lines show the first and the second addition
result signals D
2m' and D
2m+1', respectively. A thirteenth line shows the output signal OUT or the serial converted
signal D
n'.
[0029] The input signal IN or the zeroth delayed signal D
n+1 comprises a series of input elements such as first through ninth input elements D₁,
D₂, D₃, D₄, D₅, D₆, D₇, D₈, and D₉ of the first through the ninth input time slots
1 to 9. Similarly, the first delayed signal D
n comprises a series of primary delayed elements such as first through ninth primary
delayed elements which are equal to zeroth through eighth input elements D₀ to D₈
of a zeroth through the eighth input time slots 0 to 8. The second delayed signal
D
n-1 comprises a series of secondary delayed elements such as first through ninth secondary
delayed elements which are equal to one time slot previous to the zeroth or (-l)-th
through seventh elements D₋₁ to D₇ of a (-l)-th through the seventh input time slots
-1 to 7.
[0030] The first primary latched signal D
2m+1 comprises a series of primary latched elements having input time slots each of which
is equal in number to an odd number such as the first input element D₁ of the first
input time slot 1, the third input element D₃ of the third input time slot 3, the
fifth input element D₅ of the fifth input time slot 5, the seventh input element D₇
of the seventh input time slot 7. The second primary latched signal D
2m comprises a series of primary latched elements having input time slots each of which
is equal in number to an odd number such as the first primary delayed element D₀ of
the first input time slot 1, the third primary delayed element D₂ of the third input
time slot 3, the fifth primary delayed element D₄ of the fifth input time slot 5,
the seventh primary delayed element D₆ of the seventh input time slot 7. The third
primary latched signal D
2m-1 comprises a series of primary latched elements having input time slots each of which
is equal in number to an odd number such as the first secondary delayed element D₋₁
of the first input time slot 1, the third secondary delayed element D₁ of the third
input time slot 3, the fifth secondary delayed element D₃ of the fifth input time
slot 5, the seventh secondary delayed element D₅ of the seventh input time slot 7.
[0031] The first subsidiary latched signal D
2m+2 comprises a series of subsidiary latched elements having input time slots each of
which is equal in number to an even number such as the second input element D₂ of
the second input time slot 2, the fourth input element D₄ of the fourth input time
slot 4, the sixth input element D₆ of the sixth input time slot 6, the eighth input
element D₈ of the eighth input time slot 8. The second subsidiary latched signals
D
2m+1 comprises a series of subsidiary latched elements having input time slots each of
which is equal in number to an even number such as the second primary delayed element
D₁ of the second input time slot 2, the fourth primary delayed element D₃ of the fourth
input time slot 4, the sixth primary delayed element D₅ of the sixth input time slot
6, the eighth primary delayed element D₇ of the eighth input time slot 8. The third
subsidiary latched signal D
2m comprises a series of subsidiary latched elements having input time slots each of
which is equal in number to an even number such as the second secondary delayed element
D₀ of the second input time slot 2, the fourth secondary delayed element D₂ of the
fourth input time slot 4, the sixth secondary delayed element D₄ of the sixth input
time slot 6, the eighth secondary delayed element D₆ of the eighth input time slot
8.
[0032] The first addition result signal D
2m' comprises a series of addition result elements having output time slots each of
which is equal in number to an even number such as a zeroth addition result element
D₀' of a zeroth output time slot, a second addition result element D₂' of a second
output time slot, a fourth addition result element D₄' of a fourth output time slot,
a sixth addition result element D₆' of a sixth output time slot, an eighth addition
result element D₈' of an eighth output time slot. Similarly, the second addition result
signal D
2m+1' comprises a series of addition result elements having output time slots each of
which is equal in number to an odd number such as a first addition result element
D₁' of a first output time slot, a third addition result element D₃' of a third output
time slot, a fifth addition result element D₅' of a fifth output time slot, a seventh
addition result element D₇' of a seventh output time slot.
[0033] The output signal OUT or the serial converted signal D
n' comprises a series of addition result elements such as the zeroth through the eighth
addition result elements D₀' to D₈' of the zeroth through the eighth output time slots.
The output signal OUT or the serial converted signal D
n' is given by:
[0034] The first through the third tap gains C₋₁, C₀, and C₁ may be automatically controlled
by a control circuit (not shown) when the three-tap transversal filter is used in
a waveform equalization circuit or an interference canceller. In this event, the first
through the third tap gains C₋₁, C₀, and C₁ supplied to the first calculation circuit
31 are different from those supplied to the second calculation circuit 32. This is
because the first through the third tap gains C₋₁, C₀, and C₁ vary every moment. The
first through the third tap gains C₋₁, C₀, and C₁ may be fixed at predetermined values
when the three-tap transversal filter is used in a digital filter such as a roll-off
filter.
[0035] As apparent from the above description, the transversal filter produces the output
signal OUT which is equalized thereby. In the conventional transversal filter, the
first and the second latch circuits 21 and 22 distribute the input elements of the
input signal IN into the first through the third primary latched signals D
2m+1, D
2m, and D
2m-1 and the first through the third subsidiary latched signals D
2m+2, D
2m+1, and D
2m at alternative timings. In other words, each of the first and the second latch circuits
21 and 22 serves as a serial-parallel converter for converting the input signal IN
into three latched signals each of which has a data rate equal to a half times as
large as the input data rate of the input signal IN. Accordingly, the first and the
second calculation circuits 31 and 32 carry out the parallel processing at a low operational
speed which is equal to a half of the output data rate of the output signal OUT. However,
each of the first and the second delay units 16' and 17' must carry out a delay operation
at an operational speed equal to the input data rate of the input signal IN. As a
result, the conventional transversal filter is defective in that the input data rate
of the input signal IN and the operational speed of the transversal filter are restricted
by the operational speed of the first and the second delay units 16' and 17', as mentioned
in the preamble of the instant specification.
[0036] Referring to Fig. 3, the description will proceed to a transversal filter of a parallel
processing type according to a first embodiment of this invention. The transversal
filter is similar in structure and operation to the conventional transversal filter
illustrated in Fig. 1 except that the transversal filter comprises a serial-parallel
converter 40 in place of the first and the second latch circuits 21 and 22. In addition,
the delay circuit is modified in the manner which will later be described. The delay
circuit is therefore depicted at the reference numeral 10. In the transversal filter,
the input signal IN and the output signal OUT have the input and the output data rates
which are equal to each other.
[0037] The serial-parallel converter 40 is supplied with the input signal IN or D
n+1. The serial-parallel converter 40 converts the input signal IN into first and M-th
parallel converted signals, where M represents a second positive integer which is
not less than two. In the example being illustrated, the second positive integer M
is equal to two and the serial-parallel converter 40 therefore produces the first
and the second parallel converted signals D
2m+1 and D
2m.
[0038] The first and the second parallel converted signals D
2m+1 and D
2m are supplied to the delay circuit 10. The delay circuit 10 has first through L-th
taps, where L represents a third positive integer which is larger than the first positive
integer J. In the example being illustrated, the third positive integer L is equal
to four and the delay circuit 10 therefore has the first through the fourth taps 11,
12, 13, and 14. The first parallel converted signal D
2m+1 is supplied to the first tap 11 while the second parallel converted signal D
2m is supplied to the second tap 12. The first tap 11 produces the first parallel converted
signal D
2m+1 as a first tap signal as it is. Likewise, the second tap 12 produces the second parallel
converted signal D
2m as a second tap signal as it is. The delay circuit 10 comprises first and second
delay units 16 and 17 which are placed between the first and the third taps 11 and
13 and between the second and the fourth taps 12 and 14, respectively. Each of the
first and the second delay units 16 and 17 provides twice the unit delay which is
substantially equal to the reciprocal of the input data rate.
[0039] The first parallel converted signal D
2m+1 is delivered to the first tap 11 and successively delayed by the first delay unit
16 to be produced as a third tap signal D
2m-1 which is sent to the third tap 13. Likewise, the second parallel converted signal
D
2m is delivered to the second tap 12 and successively delayed by the second delay unit
17 to be produced as a fourth tap signal D
2m-2 which is sent to the fourth tap 14. At any rate, the delay circuit 10 produces the
first through the fourth tap signals D
2m+1, D
2m, D
2m-1, and D
2m-2.
[0040] The first through the third tap signals D
2m+1, D
2m, and D
2m-1 are supplied to the first calculation circuit 31 as first through third primary tap
signals, respectively. The second through the fourth tap signals D
2m, D
2m-1, and D
2m-2 are supplied to the second calculation circuit 31 as first through third subsidiary
tap signals, respectively.
[0041] In the first calculation circuit 31, the first through the third primary multiplying
circuits 311 to 313 are supplied with the first through the third primary tap signals
D
2m+1, D
2m, and D
2m-1. The first primary multiplying circuit 311 multiplies the first primary tap signal
D
2m+1 by the first tap gain C₋₁ to produce a first primary product signal indicative of
a product of the first primary tap signal D
2m+1 and the first tap gain C₋₁. The second primary multiplying circuit 312 multiplies
the second primary tap signal D
2m by the second tap gain C₀ to produce a second primary product signal indicative of
a product of the second primary tap signal D
2m and the second tap gain C₀. The third primary multiplying circuit 313 multiplies
the third primary tap signal D
2m-1 by the third tap gain C₁ to produce a third primary product signal indicative of
a product of the third primary tap signal D
2m-1 and the third tap gain C₁. The first through the third primary product signals are
supplied to the first adding circuit 314. The first adding circuit 314 adds up three
terms of the first through the third primary product signals to produce a first addition
result signal D
2m' indicative of a first addition result of the three terms.
[0042] In the second calculation circuit 32, the first through the third subsidiary multiplying
circuits 321 to 323 are supplied with the first through the third subsidiary tap signals
D
2m, D
2m-1, and D
2m-2. The first subsidiary multiplying circuit 321 multiplies the first subsidiary tap
signal D
2m by the first tap gain C₋₁ to produce a first subsidiary product signal indicative
of a product of the first subsidiary tap signal D
2m and the first tap gain C₋₁. The second subsidiary multiplying circuit 322 multiplies
the second subsidiary tap signal D
2m-1 by the second tap gain C₀ to produce a second subsidiary product signal indicative
of a product of the second subsidiary tap signal D
2m-1 and the second tap gain C₀. The third subsidiary multiplying circuit 323 multiplies
the third subsidiary tap signal D
2m-2 by the third tap gain C₁ to produce a third subsidiary product signal indicative
of a product of the third subsidiary tap signal D
2m-2 and the third tap gain C₁. The first through the third subsidiary product signals
are supplied to the second adding circuit 324. The second adding circuit 324 adds
up three terms of the first through the third subsidiary product signals to produce
a second addition result signal D
2m-1' indicative of a second addition result of the three terms.
[0043] The first and the second addition result signals D
2m' and D
2m-1' are supplied to the parallel-serial converter 35. The parallel-serial converter
35 carries out a parallel-serial conversion on or couples the first and the second
addition result signals D
2m' and D
2m-1' to produce a serial converted signal D
n-1' as the output signal OUT.
[0044] As apparent from the above description, the first and the second addition result
signals D
2m' and D
2m-1' are given by:
[0045] The output signal OUT or the serial converted signal D
n' is therefore given by:
[0046] Referring to Fig. 4 in addition to Fig. 3, description will be directed to operation
of the transversal filter illustrated in Fig. 3. First through ninth input time slots
are indicated along a first or top line in Fig. 4 by numerals 1 through 9.
[0047] The input signal IN or D
n+1 is indicated along a second line. Third through sixth lines show the first through
the fourth tap signals D
2m+1, D
2m, D
2m-1, and D
2m-2, respectively. Seventh through ninth lines show the first through the third primary
tap signals D
2m+1, D
2m, and D
2m-1 which are supplied to the first through the third primary multiplying circuits 311
to 313 in the first calculation circuit 31, respectively. Tenth through twelfth lines
show the first through the third subsidiary tap signals D
2m, D
2m-1, and D
2m-2 which are supplied to the first through the third subsidiary multiplying circuits
321 to 323 in the second calculation circuit 32, respectively. Thirteenth and fourteenth
lines show the first and the second addition result signals D
2m' and D
2m-1', respectively. A fifteenth line shows the output signal OUT or the serial converted
signal D
n-1'.
[0048] The input signal IN or D
n+1 comprises a series of input elements such as first through ninth input elements D₁,
D₂, D₃, D₄, D₅, D₆, D₇, D₈, D₉ of the first through the ninth input time slots 1 to
9.
[0049] The first tap signal D
2m+1 comprises a series of primary tap elements having input time slots each of which
is equal in number to an odd number such as the first input element D₁ of the first
input time slot 1, the third input element D₃ of the third input time slot 3, the
fifth input element D₅ of the fifth input time slot 5, the seventh input element D₇
of the seventh input time slot 7. The second tap signal D
2m comprises a series of secondary tap elements having input time slots each of which
is equal in number to an even number such as a zeroth input element D₀ of a zeroth
input time slot 0, the second input element D₂ of the second input time slot 2, the
fourth input element D₄ of the fourth input time slot 4, the sixth input element D₆
of the sixth input time slot 6. The third tap signal D
2m-1 comprises a series of tertiary tap elements having input time slots each of which
is equal in number to an odd number such as one time slot previous to the zeroth or
a (-1)-th input element D₋₁ of a (-1)-th input time slot -1, the first input element
D₁ of the first input time slot 1, the third input element D₃ of the third input time
slot 3, the fifth input element D₅ of the fifth input time slot 5. The fourth tap
signal D
2m-1 comprises a series of quaternary tap elements having input time slots each of which
is equal to an even number such as two time slots previous to the seroth or a (-2)-th
input element D₋₂ of a (-2)-th input time slot -2, the zeroth input element D₀ of
the zeroth input time slot 0, the second input element D₂ of the second input time
slot 2, the fourth input element D₄ of the fourth input time slot 4.
[0050] The first through the third primary tap signals D
2m+1, D
2m, and D
2m-1 are equal to the first through the fourth tap signals D
2m+1, D
2m, and D
2m-1, respectively. The first through the third subsidiary tap signals D
2m, D
2m-1, and D
2m-2 are equal to the second through the fourth tap signals D
2m, D
2m-1, and D
2m-2, respectively.
[0051] The first addition result signal D
2m' comprises a series of addition result elements having output time slots each of
which is equal in number to an even number such as a zeroth addition result element
D₀' of a zeroth output time slot, a second addition result element D₂' of a second
output time slot, a fourth addition result element D₄' of a fourth output time slot,
a sixth addition result element D₆' of a sixth output time slot. Similarly, the second
addition result signal D
2m-1' comprises a series of addition result elements having output time slots each of
which is equal in number to an odd number such as a (-1)-th addition result element
D₋₁' of a (-1)-th output time slot, a first addition result element D₁' of a first
output time slot, a third addition result element D₃' of a third output time slot,
a fifth addition result element D₅' of a fifth output time slot.
[0052] The output signal OUT or the serial converted signal D
n-1' comprises a series of the addition result elements such as the (-1)-th through the
sixth addition result elements D₋₁' to D₆' of the (-1)-th through the sixth output
time slots.
[0053] Referring to Fig. 5, the description will proceed to a transversal filter of a parallel
processing type according to a second embodiment of this invention. The transversal
filter is similar in structure and operation to the conventional transversal filter
illustrated in Fig. 1 except that the transversal filter comprises the serial-parallel
converter 40 and the delay circuit is modified in the manner which will later be described.
The delay circuit is therefore depicted at the reference numeral 10a. In the transversal
filter, the input signal IN has the input data rate which is twice the output data
rate of the output signal OUT. The illustrated transversal filter is a transversal
filter having a tap interval which is a half of a symbol interval and the illustrated
transversal filter is applicable to the digital filter such as the interference canceller
or the roll-off filter. In the example being illustrated, the input signal IN is a
digital signal having waveform shaped. Such a digital signal is a baseband digital
signal which is obtained by demodulating and decision a digital modulated signal.
Its decision timing has an interval which is a half of the symbol interval. In other
words, the input data rate is twice a bit rate of the input signal IN.
[0054] The serial-parallel converter 40 is supplied with the input signal IN or D
0.5(k+1). The serial-parallel converter 40 converts the input signal IN into first and second
parallel converted signals D
n+0.5 and D
n.
[0055] The first and the second parallel signals D
n+0.5 and D
n are supplied to the delay circuit 10a. The delay circuit 10 has first through L-th
taps, where L represents the third positive integer which is larger than the first
positive integer J. In the example being illustrated, the third positive integer is
equal to five and the delay circuit 10a therefore has the first through the fifth
taps 11, 12, 13, 14, and 15. The first parallel converted signal D
n+0.5 is supplied to the first tap 11 while the second parallel converted signal D
n is supplied to the second tap 12. The first tap 11 produces the first parallel converted
signal D
n+0.5 as a first tap signal as it is. Likewise, the second tap 12 produces the second parallel
converted signal D
n as a second tap signal as it is. The delay circuit 10a comprises first through third
delay units 16a, 17a, and 18a which are placed between the first and the third taps
11 and 13, between the second and the fourth taps 12 and 14, and between the third
and the fifth taps 13 and 15, respectively. Each of the first through the third delay
units 16a, 17a, and 18a provides twice the unit delay which is substantially equal
to the reciprocal of the input data rate.
[0056] The first parallel converted signal D
n+0.5 is delivered to the first tap 11 and successively delayed by the first delay unit
16a to be produced as a third tap signal D
n-0.5 which is sent to the third tap 13. Likewise, the second parallel converted signal
D
n is delivered to the second tap 12 and successively delayed by the second delay unit
17a to be produced as a fourth tap signal D
n-1.0 which is sent to the fourth tap 14. The third tap signal D
n-0.5 is delayed by the third delay unit 18a to be produced as a fifth tap signal D
n-1.5 which is sent to the fifth tap 15. At any rate, the delay circuit 10a produces the
first through the fifth tap signals D
n+0.5, D
n, D
n-0.5, D
n-1.0, and D
n-1.5.
[0057] The first through the third tap signals D
n+0.5, D
n, and D
n-0.5 are supplied to the first latch circuit 21. The first latch circuit 21 latches the
first through the third tap signals D
n+0.5, D
n, and D
n-0.5 and holds these signals during a time duration corresponding to four input time slots
of the input signal IN to produce first through third primary latched signals D
2m+0.5, D
2m, and D
2m-0.5. Likewise, the third through the fifth tap signals D
n-0.5, D
n-1.0, and D
n-1.5 are supplied to the second latch circuit 22. The second latch circuit 22 latches
the third through the fifth tap signals D
n-0.5, D
n-1.0, and D
n-1.5 and holds these signals during the time duration corresponding to the four time slots
to produce first through third subsidiary latched signals D
2m-0.5, D
2m-1.0, and D
2m-1.5.
[0058] The first through the third primary latched signals D
2m+0.5, D
2m, and D
2m-0.5 are supplied to the first calculation circuit 31 as first through third primary tap
signals, respectively. The first through the third subsidiary latched signals D
2m-0.5, D
2m-1.0, and D
2m-1.5 are supplied to the second calculation circuit 31 as first through third subsidiary
tap signals, respectively.
[0059] In the first calculation circuit 31, the first through the third primary multiplying
circuits 311 to 313 are supplied with the first through the third primary tap signals
D
2m+0.5, D
2m, and D
2m-0.5. The first primary multiplying circuit 311 multiplies the first primary tap signal
D
2m+0.5 by the first tap gain C₋₁ to produce a first primary product signal indicative of
a product of the first primary tap signal D
2m+0.5 and the first tap gain C₋₁. The second primary multiplying circuit 312 multiplies
the second primary tap signal D
2m by the second tap gain C₀ to produce a second primary product signal indicative of
a product of the second primary tap signal D
2m and the second tap gain C₀. The third primary multiplying circuit 313 multiplies
the third primary tap signal D
2m-0.5 by the third tap gain C₁ to produce a third primary product signal indicative of
a product of the third primary tap signal D
2m-0.5 and the third tap gain C₁. The first through the third primary product signals are
supplied to the first adding circuit 314. The first adding circuit 314 adds up three
terms of the first through the third primary product signals to produce a first addition
result signal D
2m' indicative of a first addition result of the three terms.
[0060] In the second calculation circuit 32, the first through the third subsidiary multiplying
circuits 321 to 323 are supplied with the first through the third subsidiary tap signals
D
2m-0.5, D
2m-1.0, and D
2m-1.5. The first subsidiary multiplying circuit 321 multiplies the first subsidiary tap
signal D
2m-0.5 by the first tap gain C₋₁ to produce a first subsidiary product signal indicative
of a product of the first subsidiary tap signal D
2m-0.5 and the first tap gain C₋₁. The second subsidiary multiplying circuit 322 multiplies
the second subsidiary tap signal D
2m-1.0 by the second tap gain C₀ to produce a second subsidiary product signal indicative
of a product of the second subsidiary tap signal D
2m-1.0 and the second tap gain C₀. The third subsidiary multiplying circuit 323 multiplies
the third subsidiary tap signal D
2m-1.5 by the third tap gain C₁ to produce a third subsidiary product signal indicative
of a product of the third subsidiary tap signal D
2m-1.5 and the third tap gain C₁. The first through the third subsidiary product signals
are supplied to the second adding circuit 324. The second adding circuit 324 adds
up three terms of the first through the third subsidiary product signals to produce
a second addition result signal D
2m-1' indicative of a second addition result of the three terms.
[0061] The first and the second addition result signals D
2m' and D
2m-1' are supplied to the parallel-serial converter 35. The parallel-serial converter
35 carries out a parallel-serial conversion on or couples the first and the second
addition result signals D
2m' and D
2m-1' to produce a serial converted signal D
n-1' as the output signal OUT.
[0062] As apparent from the above description, the first and the second addition result
signals D
2m' and D
2m-1' are given by:
[0063] The output signal OUT or the serial converted signal D
n' is therefore given by:
[0064] Referring to Fig. 6 in addition to Fig. 5, description will be directed to operation
of the transversal filter illustrated in Fig. 5. First through eighteenth input time
slots are indicated along a first or top line in Fig. 6 by numerals 1 through 18.
[0065] The input signal IN or D
0.5(k+1) is indicated along a second line. Third through seventh lines show the first through
the fifth tap signals D
n+0.5, D
n, D
n-0.5, D
n-1.0, and D
n-1.5, respectively. Eighth through tenth lines show the first through the third primary
tap signals D
2m+0.5, D
2m, and D
2m-0.5 which are supplied to the first through the third primary multiplying circuits 311
to 313 in the first calculation circuit 31, respectively. Eleventh through thirteenth
lines show the first through the third subsidiary tap signals D
2m-0.5, D
2m-1.0, and D
2m-1.5 which are supplied to the first through the third subsidiary multiplying circuits
321 to 323 in the second calculation circuit 32, respectively. Fourteenth and fifteenth
lines show the first and the second addition result signals D
2m' and D
2m-1', respectively. A sixteenth line shows the output signal OUT or the serial converted
signal D
n-1'.
[0066] The input signal IN or D
0.5(k+1) comprises a series of input elements such as first through eighteenth input elements
D
0.5, D
1.0, D
1.5, D
2.0, D
2.5, D
3.0, D
3.5, D
4.0, D
4.5, D
5.0, D
5.5, D
6.0, D
6.5, D
7.0, D
7.5, D
8.0, D
8.5, and D
9.0 of the first through the eighteenth input time slots 1 to 18.
[0067] The first tap signal D
n+0.5 comprises a series of primary tap elements having input time slots each of which
is equal in number to an odd number such as the first input element D
0.5 of the first input time slot 1, the third input element D
1.5 of the third input time slot 3, the fifth input element D
2.5 of the fifth input time slot 5, the seventh input element D
3.5 of the seventh input time slot 7, the ninth input element D
4.5 of the ninth input time slot 9, the eleventh input element D
5.5 of the eleventh input time slot 11, the thirteenth input element D
6.5 of the thirteenth input time slot 13, the fifteenth input element D
7.5 of the fifteenth input time slot 15, the seventeenth input element D
8.5 of the seventeenth input time slot 17.
[0068] The second tap signal D
n comprises a series of secondary tap elements having input time slots each of which
is equal in number to an even number such as a zeroth input element D
0.0 of a zeroth input time slot 0, the second input element D
1.0 of the second input time slot 2, the fourth input element D
2.0 of the fourth input time slot 4, the sixth input element D
3.0 of the sixth input time slot 6, the eighth input element D
4.0 of the eighth input time slot 8, the tenth input element D
5.0 of the tenth input time slot 10, the twelfth input element D
6.0 of the twelfth input time slot 12, the fourteenth input element D
7.0 of the fourteenth input time slot 14, the sixteenth input element D
8.0 of the sixteenth input time slot 16.
[0069] The third tap signal D
n-0.5 comprises a series of tertiary tap elements having input time slots each of which
is equal in number to an odd number such as a (-1)-th input element D
-0.5 of a (-1)-th input time slot -1, the first input element D
0.5 of the first input time slot 1, the third input element D
1.5 of the third input time slot 3, the fifth input element D
2.5 of the fifth input time slot 5, the seventh input element D
3.5 of the seventh input time slot 7, the ninth input element D
4.5 of the ninth input time slot 9, the eleventh input element D
5.5 of the eleventh input time slot 11, the thirteenth input element D
6.5 of the thirteenth input time slot 13, the fifteenth input element D
7.5 of the fifteenth input time slot 15.
[0070] The fourth tap signal D
n-1.0 comprises a series of quaternary tap elements having input time slots each of which
is equal to an even number such as a (-2)-th input element D
-1.0 of a (-2)-th input time slot -2, the zeroth input element D
0.0 of a zeroth input time slot 0, the second input element D
1.0 of the second input time slot 2, the fourth input element D
2.0 of the fourth input time slot 4, the sixth input element D
3.0 of the sixth input time slot 6, the eighth input element D
4.0 of the eighth input time slot 8, the tenth input element D
5.0 of the tenth input time slot 10, the twelfth input element D
6.0 of the twelfth input time slot 12, the fourteenth input element D
7.0 of the fourteenth input time slot 14.
[0071] The fifth tap signal D
n-1.5 comprises a series of quinary tap elements having input time slots each of which
is equal to an odd number such as a (-3)-th input element D
-1.5 of a (-3)-th input time slot -3, the (-1)-th input element D
-0.5 of a (-1)-th input time slot -1, the first input element D
0.5 of the first input time slot 1, the third input element D
1.5 of the third input time slot 3, the fifth input element D
2.5 of the fifth input time slot 5, the seventh input element D
3.5 of the seventh input time slot 7, the ninth input element D
4.5 of the ninth input time slot 9, the eleventh input element D
5.5 of the eleventh input time slot 11, the thirteenth input element D
6.5 of the thirteenth input time slot 13.
[0072] The first primary tap signal D
2m+0.5 comprises a series of primary latched elements having (4n+1)-th input time slots
such as the first input element D
0.5 of the first input time slot 1, the fifth input element D
2.5 of the fifth input time slot 5, the ninth input element D
4.5 of the ninth input time slot 9, the thirteenth input element D
6.5 of the thirteenth input time slot 13. The second primary tap signal D
2m comprises a series of primary latched elements having (4n)-th input time slots such
as the zeroth input element D
0.0 of a zeroth input time slot 0, the fourth input element D
2.0 of the fourth input time slot 4, the eighth input element D
4.0 of the eighth input time slot 8, the twelfth input element D
6.0 of the twelfth input time slot 12. The third primary tap signal D
2m-0.5 comprises a series of primary latched elements having (4n-1)-th input time slots
such as the (-1)-th input element D
-0.5 of the (-1)-th input time slot -1, the third input element D
1.5 of the third input time slot 3, the seventh input element D
3.5 of the seventh input time slot 7, the eleventh input element D
5.5 of the eighth input time slot 11.
[0073] The first subsidiary tap signal D
2m-0.5 comprises a series of subsidiary latched elements having (4n-1)-th input time slots
such as the (-1)-th input element D
-0.5 of the (-1)-th input time slot -1, the third input element D
1.5 of the third input time slot 3, the seventh input element D
3.5 of the seventh input time slot 7, the eleventh input element D
5.5 of the eleventh input time slot 11. The second subsidiary tap signal D
2m-1.0 comprises a series of subsidiary latched elements having (4n-2)-th input time slots
such as the (-2)-th input element D
-1.0 of the (-2)-th input time slot -2, the second input element D
1.0 of the second input time slot 2, the sixth input element D
3.0 of the sixth input time slot 6, the tenth input element D
5.0 of the tenth input time slot 10. The third subsidiary tap signal D
2m-1.5 comprises a series of subsidiary latched elements having (4n-3)-th input time slots
such as the (-3)-th input element D
-1.5 of the (-3)-th input time slot -3, the first input element D
0.5 of the first input time slot 1, the fifth input element D
2.5 of the fifth input time slot 5, the ninth input element D
4.5 of the ninth input time slot 9.
[0074] The first addition result signal D
2m' comprises a series of addition result elements having output time slots each of
which is equal in number to an even number such as a zeroth addition result element
D
0.0' of a zeroth output time slot, a second addition result element D
2.0' of a second output time slot, a fourth addition result element D
4.0' of the fourth output time slot, a sixth addition result element D
6.0' of the sixth output time slot. Similarly, the second addition result signal D
2m+1' comprises a series of addition result elements having output time slots each of
which is equal in number to an odd number such as a (-1)-th addition result element
D
-1.0' of a (-1)-th output time slot, a first addition result element D
1.0' of a first output time slot, a third addition result element D
3.0' of a third output time slot, a fifth addition result element D
5.0' of a fifth output time slot.
[0075] The output signal OUT or the serial converted signal D
n-1' comprises a series of the addition result elements such as the (-1)-th through the
sixth addition result elements D
-1.0' to D
6.0' of the (-1)-th through the sixth output time slots.
[0076] In the above-mentioned embodiments, the serial-parallel converter 40 carries out
serial-parallel conversion on the digital input signal IN into which an analog input
signal is converted by an analog-to-digital converter (not shown).
[0077] Referring to Fig. 7, the description will be directed to another serial-parallel
converter 40a. The serial-parallel converter 40a is supplied with the analog input
signal depicted at INa instead of the digital input signal IN. In addition, the serial-parallel
converter 40a is supplied with an input clock signal CLK having a clock frequency
which is equal to a half of the input data rate of the analog input signal INa.
[0078] The serial-parallel converter 40a comprises first and second analog-to-digital (A/D)
converter 41a and 42a and an inverting circuit 43a. The first A/D converter 41a is
supplied with the analog input signal INa and the input clock signal CLK. The first
A/D converter 41a converts the analog input signal INa into a first digital converted
signal D
2m in synchronism with the input clock signal CLK. In particular, the first A/D converter
41a converts, in response to leading edge of the input clock signal CLK, input analog
values of the analog input signal INa into the first digital converted signal D
2m. The first digital converted signal D
2m is produced as the second parallel converted signal.
[0079] The inverting circuit 43a is supplied with the input clock signal CLK. The inverting
circuit 43a inverts the input clock signal CLK to produce an inverted clock signal
. The inverted clock signal
is supplied to the second A/D converter 42a which is supplied with the analog input
signal INa. The second A/D converter 42a converts the analog input signal INa into
a second digital converted signal D
2m+1 in synchronism with the inverted clock signal
. In particular, the second A/D converter 42a converts, in response to leading edge
of the inverted clock signal
, input analog values of the analog input signal INa into the second digital converted
signal D
2m+1. The second digital converted signal D
2m+1 is produced as the first parallel converted signal.
[0080] At any rate, the analog input signal INa is converted into the first and the second
digital converted signals D
2m and D
2m+1 by the first and the second A/D converters 41a and 42a at two different timings.
[0081] Turning to Fig. 8 in addition to Fig. 7, description will be directed to operation
of the serial-parallel converter 40a. The analog input signal INa is indicated along
a first or top line in Fig. 8. Second and third lines show the input clock signal
CLK and the inverted clock signal
, respectively. Fourth and fifth lines show the first and the second digital converted
signals D
2m and D
2m+1, respectively.
[0082] The analog input signal INa comprises a series of zeroth through seventh input analog
values Da₀, Da₁, Da₂, Da₃, Da₄, Da₅, Da₆, and Da₇. The input clock signal CLK has
the leading edges where the input analog values each of which is equal in number to
an even number such as the zeroth input analog value Da₀, the second input analog
value Da₂, the fourth input analog value Da₄, the sixth input analog value Da₆ are
present. The inverted clock signal
has the leading edges where the input analog values each of which is equal in number
to an odd number such as the first input analog value Da₁, the third input analog
value Da₃, the fifth input analog value Da₅, the seventh input analog value Da₇ are
present.
[0083] It will be assumed that the zeroth through the seventh input analog values Da₀ to
Da₇ correspond to zeroth through seventh digital values D₀, D₁, D₂, D₃, D₄, D₅, D₆,
and D₇, respectively. The first digital converted signal D
2m comprises a series of primary digital converted elements having the digital values
each of which is equal in number to an even number such as the zeroth digital value
D₀, the second digital value D₂, the fourth digital value D₄, the sixth digital value
D₆. The second digital converted signal D
2m+1 comprises a series of secondary digital converted elements having the digital values
each of which is equal in number to an odd number such as the first digital value
D₁, the third digital value D₃, the fifth digital value D₅, and the seventh digital
value D₇.
[0084] While this invention has thus far been described in conjunction with a few embodiments
thereof, it will now be readily possible for those skilled in the art to put this
invention into practice in various other manners.