BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] This invention relates to electronic circuitry, and more particularly to a method
and apparatus for reducing power usage by registers in low-power circuits.
2. Description of Related Art
[0002] Low power electronic circuits are commonly used in battery-operated products such
as cellular telephones, calculators, computers,
etc. Much effort has been devoted by the electronics industry to provide greater functionality
for such circuits while reducing power requirements.
[0003] Various types of low power circuits use a plurality of registers (also known as register
files) to store multiple bits of data. For example, a microprocessor or microcontroller
circuit often has multiple registers for storing data values and instructions. FIGURE
1 is a block diagram of a typical prior art microprocessor showing a set or bank of
8 registers 1 are coupled to input selectors 2 and output selectors 3 as shown. Other
elements, such as multiplexers 4, 5, barrel shifter 6, and arithmetic logic unit 7,
are coupled in a loop to the inputs selectors 2 and output selectors 3 for the registers
1. Typically, one to three registers are involved in any one processing cycle. A microinstruction
controlling a particular processing cycle specifies which registers are involved.
[0004] Registers are generally designed to be fast and static (
i.e., do not require refreshing), and thus generally comprise a plurality of static storage
elements, each element comprising a plurality of transistor elements. Static storage
elements can consume a fairly large amount of power. It would be desirable to reduce
power consumption by registers used in low power circuits.
[0005] The present invention provides a method and apparatus for accomplishing this goal.
SUMMARY OF THE INVENTION
[0006] The invention is based on the observations that (1) a characteristic of static storage
elements is that they draw some power when clocked (
i.e., when a synchronizing signal is applied to each element to transfer input to output,
if the element is enabled), but draw substantially more power when the data within
the elements is changing instead of static, and (2) not all registers are used in
each processing cycle. Accordingly, the present invention analyzes each microinstruction
to determine which registers in a processing cycle are not involved in the processing
cycle, and prevents those registers from being clocked during such processing cycle.
Hence, inactive registers during a processing cycle do not consume power at the level
of active registers, thus lowering overall power usage by any system employing such
gated-clock registers.
[0007] The details of the preferred embodiment of the present invention are set forth in
the accompanying drawings and the description below. Once the details of the invention
are known, numerous additional innovations and changes will become obvious to one
skilled in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGURE 1 is a block diagram of a typical prior art microprocessor showing a set of
8 registers coupled to input selectors and output selectors.
[0009] FIGURE 2 is a block diagram showing the preferred embodiment of the invention.
[0010] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION OF THE INVENTION
[0011] Throughout this description, the preferred embodiment and examples shown should be
considered as exemplars, rather than as limitations on the present invention.
Overview
[0012] A characteristic of static storage elements is that they draw some power when clocked
(
i.e., when a synchronizing signal is applied to each element to transfer input to output,
if the element is enabled), but draw substantially more power when the data within
the elements is changing instead of static. In conventional circuitry using registers
(
e.g., microprocessors or microcontrollers), all registers are clocked even when no change
is to be made to the contents of each register. Further, not all registers are used
in each processing cycle. Accordingly, the present invention analyzes each microinstruction
to determine which registers in a processing cycle are not involved in the processing
cycle, and prevents those registers from being clocked during such processing cycle.
(As used herein, "microinstruction" means any collection of bits controlling processing
cycles).
[0013] FIGURE 2 is a block diagram showing the preferred embodiment of the invention. A
set of registers 20, similar to the register bank 1 shown in FIGURE 1, have their
clock inputs 21 coupled through corresponding AND gates 26 to a clock signal from
a clock source 24. Also coupled to each AND gate 26 is decode logic 28, which in turn
is coupled to an instruction source 30 (which may be, for example, a ROM). While FIGURE
2 shows the functional aspects of the invention most clearly, in practice it may be
preferred to directly couple the clock source 24 to the decode logic 28, and incorporate
the AND gates 26 directly into the decode logic 28.
[0014] The decode logic 28 determines which of the registers 20 are involved in each processing
cycle by examining the appropriate fields or bit positions of the microinstruction
controlling that particular processing cycle. That is, each microinstruction has at
least one indication of which of the plurality of registers are active during each
processing cycle. If a register is not involved in a processing cycle, then the decode
logic 28 blocks the clock signal from the clock source 24 from being applied to the
clock input 21 of that register 20 through the corresponding AND gate 26. (In the
preferred embodiment, the output control signal of the decode logic 28 is synchronized
to the falling edge of the clock to avoid clock "glitches" or noise). Conversely,
if a register is involved in a processing cycle, then the decode logic 28 allows the
clock signal from the clock source 24 to pass to the clock input 21 of that register
20. Hence, unused (inactive) registers during a processing cycle do not consume power
at the level of used (active) registers, thus lowering overall power usage by any
system employing such gated-clock registers.
Example
[0017] Power savings using the invention depends on the implementing semiconductor technology,
the style of the storage element circuitry comprising each register, and the width
of each register. In one embodiment in which the invention was used for a 16-bit register,
power savings from clocking only active registers was about 20% to 25%. For a smaller
register width, the percentage saved would be lower, while for a wider register, the
percentage saved is potentially considerably higher.
[0018] A number of embodiments of the present invention have been described. Nevertheless,
it will be understood that various modifications may be made without departing from
the spirit and scope of the invention. Accordingly, it is to be understood that the
invention is not to be limited by the specific illustrated embodiment, but only by
the scope of the appended claims.
1. A circuit for controlling power usage in an electronic system (1) having a processing
cycle synchronized by a clock signal from a clock source and (2) utilizing a plurality
of registers clocked by the clock signal and under control of microinstructions, each
microinstruction having at least one indication of which of the plurality of registers
are active during each processing cycle, the circuit comprising:
(a) a plurality of control gates, each having an output coupled to a clock input of
a corresponding registers and an input coupled to the clock signal from the clock
source;
(b) decode logic, having an input coupled to a source of microinstructions and a plurality
of output, each coupled to a corresponding control gate, for determining, from the
at least one indication of which of the plurality of registers are active during each
processing cycle, which of the plurality of registers will be inactive during each
processing cycle, and for blocking the clock signal through the control gate of each
such inactive register, thereby controlling power usage of the system.
2. A method for controlling power usage in an electronic system (1) having a processing
cycle synchronized by a clock signal from a clock source and (2) utilizing a plurality
of registers clocked by the clock signal and under control of microinstructions, each
microinstruction having at least one indication of which of the plurality of registers
are active during each processing cycle, the method comprising the steps of:
(a) determining, from the at least one indication of which of the plurality of registers
are active during each processing cycle, which of the plurality of registers will
be inactive during each processing cycle; and
(b) blocking the clock signal to each such inactive register, thereby controlling
power usage of the system.