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(11) | EP 0 977 386 A1 |
| (12) | EUROPEAN PATENT APPLICATION |
| published in accordance with Art. 158(3) EPC |
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| (54) | DIGITAL SIGNAL RECEIVER |
| (57) FM multiplex signals received by an antenna 12 and FM-demodulated by an FM tuner
portion 14 are supplied to an FM multiplex decoding portion 15 extracting a base band
signal therefrom. A CPU 40 in a personal computer 120 reconfigures program data based
on the extracted base band signal. CPU 40 starts reconfiguring of the program data
sent over a new selected network after it receives a predetermined number of packet
data subsequently to instruction of network switching. |
Technical Field
[0001] The present invention relates to a digital signal receiving device which can receive programs over a plurality of networks in a multiplex broadcast system, and in particular an FM multiplex signal receiving device which receives the program data transmitted by FM multiplex broadcast system.
Background Art
[0002] In recent years, FM multiplex broadcast has been developed toward practical utilization as one kind of broadcast providing new service. In this FM multiplex broadcast, digital signals are multiplexed in a blank spectrum region of base band signals in FM stereo broadcast.
[0003] The FM multiplex broadcast is new media for broadcasting traffic information, character and graphic information or the like by multiplexing digital signals in a frequency band higher than that of audio signals of current FM stereo broadcast. The FM multiplex broadcast has such features that the frequency can be effectively utilized, broadcast facilities can be simple, data can be received on mobile units, and therefore traffic information or the like can be easily transmitted to mobile units such as automobiles.
[0004] Accordingly, practical use of the FM multiplex broadcast has already started in some fields as means for sending traffic jam information and others in real time to automobiles or the like carrying receivers, or as means providing inexpensive transmission paths over which users having handy-size receivers can access necessary information at any time and any place.
[0005] Before describing structures of the FM multiplex broadcast receiving device in the prior art, data structures in the FM multiplex broadcast will now be described briefly.
[Method of FM Multiplex Broadcast]
[0006] In the FM multiplex broadcast, multipath jamming and phasing jamming become factors deteriorating a state of signal reception. In particular, signal reception on the mobile unit is generally performed over paths of extremely bad properties. Even in this case, it is desired that the system allows complete signal reception by only one receiving operation. In practice, however, transmitted data cannot be completely received by one receiving operation in some cases. In such cases, incomplete data must be complemented by receiving data which is retransmitted. A service area of the FM multiplex broadcast is desired to be equal to a service area of the FM stereo broadcast. However, the service area practically contains locations where an average bit error rate exceeds 10-2. In the structure of the transmitted data, therefore, an error correction system and a frame structure are determined in view of such extremely bad transmission path properties.
[0007] In particular, the phasing jam causes extreme voltage drop, resulting in a critical error which cannot be corrected in some cases. In view of this, the unit data length of data to be transmitted is determined to match with the average burst length of the error caused by phasing. Thereby, the data can be complemented by replacing the above unit data with the retransmitted unit data when uncorrectable error occurs.
[0008] Since product codes formed of orthogonally arranged two block codes are used in an error correcting system because it can achieve a high error correction effect. Therefore, the data has a two-dimensional frame structure which includes error correction codes in both the longitudinal and lateral directions.
[0009] The transmission data has a data structure having a hierarchical structure in which data of the above one frame forms a basic unit.
[0010] As a specific example described above, description will now be given on the FM multiplex broadcast system, which is disclosed in a reference (Proc. of Vehicle Navigation & Information Systems Conference (1994), A4-2, pp. 111 - 116).
[0012] In a layer 1, transmission path properties are specified. In addition to L+R signals and L-R signals which are usual FM stereo broadcast signals, multiplex signals are superimposed on the side of a higher frequency than the L-R signals.
[0013] As this superimposing system, LMSK (Level controlled Minimum Shift Keying) system, in which the level of multiplex signal is controlled in accordance with the degree of demodulation, is employed in view of the fact that jamming against audio signals by the multiplex signals becomes remarkable if the degree of audio demodulation is small.
[0014] The layer 2 specifies the frame structure of data including the error correction method. Each frame is formed of 272 blocks in the column direction, and a BIC (Block Identification Code) of 16 bits are added to the front end. Frame synchronization and block synchronization are performed based on the BIC. Among 272 blocks in the column direction, 190 blocks form a packet transmitting data, and 82 blocks form a parity packet transmitting parities in the column direction. Each packet is formed of an information portion of 176 bits in the row direction, a CRC (Cyclic Redundancy Code) of 14 bits forming an error detection code and a parity portion of 82 bits forming an error correction code.
[0015] Thus, the transmission data is first subjected to the error correction in this layer handling the one frame as a basic unit.
[0016] A layer 3 specifies the structure of the data packet. The data packet is formed of 176 bits in each row of the frame other than BIC, CRC and the parities.
[0017] Further, this data packet is formed of a prefix and a data block. The prefix contains information for identifying contents of the data, and specifies, e.g., the program contents, to which the data packet in question belongs, as will be described later.
[0018] A layer 4 specifies a structure of a data group. The data block is formed of one or more data blocks. Based on the information in the prefix of the data packet, the data blocks are arranged in the order of the data packet numbers starting from "0" to that of the data block carrying "ON information end flag in its prefix. This data group likewise includes CRC, i.e., the error correction code, and error detection is likewise effected on the transmission data in this layer.
[0020] A layer 5 specifies one grouped form or unit of information data transmitted by the FM multiplex broadcast, and thus specifies the structure of the program data. Fig. 13 shows a structure of the program data. The program of characters and graphic information is formed of a plurality of data groups. The data group in the front end serves as program management data, and is formed of coded information relating, e.g., to a program number and a total number of pages, and thus relating to the whole of the program. The program management data is followed by a plurality of page data, each of which is coded for each page.
[0021] The program data and page data is formed of a data header and a data unit group. The data unit group is formed of a plurality of data units such as a character data part and a photographic image data part, which are divided in accordance with coded units or parts.
[0022] In the above data structure described above, the program data forms a group of data, in which the program data represents one grouped form of consistent information on the receiver side. In the case of, e.g., traffic information, the program information presents a situation of traffic jam or the like in each junction on a specific route (e.g., a speedway). In the case of weather forecast, it represents weather forecast information or the like in a specific region.
[Structure of Conventional FM Multiplex Broadcast Receiving Device]
[0023] Fig. 14 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 10 in the prior art.
[0024] FM multiplex broadcast signals received via an antenna 12 and a tuner 14 are detected by a detector circuit 16, and are sent through a band-path filter 18 to an LMSK demodulation circuit 20. LMSK demodulation circuit 20 performs data demodulation on LMSK-modulated FM multiplex broadcast signals to take out FM multiplex signals. The demodulated data signals are processed in a synchronous reproducing circuit 22, which performs frame synchronization and block synchronization based on BIC, as already described in connection with layer 2 shown in Fig. 12. The data signals thus synchronized are processed by an error correction circuit 24 performing error correction based on the parity code and CRC.
[0025] Accordingly, error correction circuit 24 issues packet data of the FM multiplex broadcast, which is correctly received, is subjected to error correction and has the structure shown in the layer 3 in Fig. 12.
[0026] A central processing unit 40, which will be referred to as a "CPU" hereinafter, processes the supplied packet data by performing extraction of data blocks, reconfiguration of data groups, error correction in the data group stage and reconfiguration into program data, and thereafter issues the program data to a display device 42. Display device 42 displays the supplied program data as graphics or characters.
[0027] Display device 42 employs a liquid crystal screen or the like having a display region for one page, i.e., 248 x 60 dots (corresponding to 15.5 characters x 2.5 lines of Japanese letters).
[0028] In FM multiplex broadcast receiving device 10 described above, programs transmitted over different networks, i.e., programs sent from different providers can be selectively received by such a structure that CPU 40 controls channel selection by a tuner.
[0029] For this, channel selection information data for specifying the network selected by CPU 40 is applied to tuner 14 and LMSK demodulation circuit 20. Thereby, tuner 14 selects the intended network, and the LMSK demodulation circuit 20 detects the reception of packet data over the selected network. Upon this detection, LMSK demodulation circuit 20 returns predetermined data to CPU 40. In this manner, it is possible to achieve a synchronous operation for notifying the start of data reception over the selected network. In other words, synchronous operation by so-called handshaking can be performed between CPU 40, and tuner 14 and LMSK demodulation circuit 20.
[0030] The FM multiplex broadcast receiving device may have a structure other than the integrated structure shown in Fig. 14, and more specifically may have a structure, in which circuits performing FM demodulation, LMSK demodulation and extraction of packet data (including synchronous reproduction and error correction of packet data) are integrated in a so-called PC card (PCMCIA card: Personal Computer Memory Card International Association card) and are connected to a host personal computer (which will be referred to as a "host PC" hereinafter) via an appropriate interface.
[0031] According to this structure, character/graphic information transmitted by the FM multiplex broadcast can be displayed without restrictions on the display screen size in contrast to the FM multiplex broadcast receiving device of an integrated type.
[0032] Fig. 15 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 80 having the above structure, in which a PC card is connected to a host PC via an interface.
[0033] For the sake of simplicity, Fig. 15 depicts tuner 14 and detector circuit 16 in Fig. 14 as one block of an FM demodulation circuit 17, and LMSK demodulation circuit 20 and error correction circuit 24 are depicted as one block of LMSK demodulation integrated circuit 25. Accordingly, FM multiplex broadcast signals which are received by antenna 12 and are demodulated by FM demodulation circuit 17 are applied to LMSK demodulation integrated circuit 25 through band-path filter 18. LMSK demodulation integrated circuit 25 performs data demodulation on the FM multiplex broadcast signals which were LMSK-modulated, and the frame synchronization and block synchronization are effected on the extracted FM multiplex signals based on BIC as already described in connection with the layer 2 in Fig. 12. Thereafter, the error correction is performed based on the parity code and CRC.
[0034] Accordingly, LMSK demodulation integrated circuit 25 issues the packet data (having the structure shown in layer 3 in Fig. 12) of the FM multiplex broadcast, which are normally received and are already subjected to the error correction.
[0035] An interface portion (which will be referred to as an "I/F portion" hereinafter) 30 receives the packet data from LMSK demodulation integrated circuit 25, and issues the same to an interface portion 38 on the host PC side.
[0036] A central processing unit (CPU) of the host PC processes the received packet data by performing extraction of data blocks, reconfiguration of data groups, error correction in the data group stage and reconfiguration to the program data, and thereafter issues the program data to a display device (not shown). In Fig. 15, the CPU and a memory transmitting data to and from the CPU are depicted as one block 45.
[0037] As described above, the display device may be provided by the display device of the host PC such as a liquid crystal flat panel display, whereby the display region in the above structure can have a resolution of 640 x 400 dots or more.
[0038] However, FM multiplex broadcast receiving device 80 which includes the PC card and the host PC coupled through the interface suffers from the following problems. Circuits incorporated into the PC card must have a structure as simple as possible in view of mounting and cost. For this, connection to the host PC must be achieved by a structure, which does not have a reception buffer or the like, and can directly transfer received data to the host PC. In this structure, instruction of the network switching from the host PC to the PC card as well as data transfer from the PC card to the host PC must be performed in an asynchronous manner.
[0039] According to the asynchronous interface, however, positions of delimiters in the program data cannot be determined when switching and receiving the program data over a plurality of networks.
[0040] Even if switching of the network is instructed from the host PC side to the PC card, packet data corresponding to the new switched or selected network is not issued from the PC card immediately after the instruction. In the system which simply employs the asynchronous interface, therefore, the display device erroneously displays the program, which was selected before the switching, for a certain time after the switching of the network.
[0041] Further, various kinds of information supplied by FM multiplex broadcast over different networks (from broadcast stations) aim at different kinds of services, respectively. For completely receiving all the kinds of services, the structure additionally suffers from the following problem. The above different kinds of services are, for example, so-called visible radio for transmitting news information as character information, traffic information (which will be referred to as VICS (Vehicle Information Communication System) information) and others.
[0042] For fully receiving all the different kinds of services as described above, a plurality of receiver systems may be mounted, as is done in a double tuner structure shown in Fig. 16. In this case, if a plurality of systems each formed of a simple receiving system are employed, a plurality of systems are likewise required for data transfer to the host PC. In other words, a plurality of addresses must be allocated in the interface portion on the host PC side, and a plurality of interrupts are asynchronously performed on the host PC. This complicates data reception software on the host PC side, and increases loads on hardware.
[0043] Meanwhile, on-vehicle systems are not allowed to cause interruption of audio output during reception over a specific network. However, the foregoing structure including the PC card and the host PC connected together via the interface may be used in such a field that prime importance is placed on acquisition of information over a plurality of networks rather than real-time output of information. In this case, such a structure may be employed that is provided with only one receiving system, and can successively scan a plurality of networks. However, even this structure suffers from a problem that a delimiter of information cannot be detected on the host PC side when the networks are switched.
[0044] The above structure may employ such a specific structure that scans a plurality of networks in accordance with timing specified by a user. In this case, however, appropriate timing for scanning must be selected on the system side in order to prevent deterioration of the data acquisition efficiency.
Disclosure of Invention
[0045] An object of the invention is to provide a digital signal receiving device, which can be used in an operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, and particularly can prevent output of information sent over a last selected network after switching of the network.
[0046] Another object of the invention is to provide a digital signal receiving device, which can be used in an operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, and particularly can employ a receiver portion and a data reconfiguring portion having simplified structures and allowing reduction in manufacturing cost.
[0047] Still another object of the invention is to provide a digital signal receiving device, which can be used in an operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, and particularly can efficiently acquire the data over the plurality of networks.
[0048] In summary, the invention provides a digital signal receiving device in a communication system for transmitting a plurality of program data each divided into a plurality of packets taking the form of a packet stream and multiplexed into main signal data, each of the packets including an attribute data specifying one of a plurality of networks belonging to the corresponding program data, comprising: a multiplex signal separating circuit for receiving the packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
[0049] The multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as the plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the packet data after adding identification data to each packet data in accordance with the attribute data.
[0050] According to another aspect, the invention provides a digital signal receiving device in a communication system for transmitting a plurality of program data each divided into a plurality of packets taking the form of a packet stream and multiplexed into main signal data, each of the packets including an attribute data specifying one of a plurality of networks belonging to the corresponding program data, comprising: a multiplex signal separating circuit for receiving the packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
[0051] The multiplex signal separating circuit includes a first demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a first multiplex signal decoding circuit for receiving the output of the first demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of first packet data formed of the corresponding digital signals; a second demodulating circuit for receiving and demodulating the carrier wave carrying the multiplex signal corresponding to the selected network in accordance with the control signal; a second multiplex signal decoding circuit for receiving the output of the second demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of second packet data formed of the corresponding digital signal; and an interface control circuit for receiving the outputs of the first and second multiplex signal decoding circuits, and issuing the packet data in a time-sharing manner after adding identification data to each of the first and second packet data depending on whether the packet data is an output of the first or second multiplex decoding circuit.
[0052] According to still another aspect, the invention provides a digital signal receiving device in a communication system for transmitting a plurality of program data each divided into a plurality of packets taking the form of a packet stream and multiplexed into main signal data, each of the packets including an attribute data specifying one of a plurality of networks belonging to the corresponding program data, comprising: a multiplex signal separating circuit, an information reconfiguring circuit and a display device.
[0053] The multiplex signal separating circuit receives the packet stream, and extracts corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
[0054] The multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after buffering the same.
[0055] The information reconfiguring circuit applies the control signal to the multiplex signal separating circuit, receiving the output of the interface control circuit, reconfiguring display data corresponding to the program data and outputting the same. Thee information reconfiguring circuit includes a timing detecting circuit for determining a time of start of acquiring the packet data for reconfiguring the display data after issuing the control signal for switching the networks.
[0057] According to yet another aspect, the invention provides a digital signal receiving device in a communication system for transmitting a plurality of program data each divided into a plurality of packets taking the form of a packet stream and multiplexed into main signal data, each of the packets including an attribute data specifying one of a plurality of networks belonging to the corresponding program data, and at least one of the networks providing program data of a cyclic type containing information contents to be broadcasted within a first predetermined time and to be renewed at intervals of a second predetermined time, comprising: a multiplex signal separating circuit, an information reconfiguring circuit and a display device.
[0058] The multiplex signal separating circuit receives the packet stream, and extracts corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
[0059] The multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after adding identification data to each packet data in accordance with the attribute data.
[0060] The information reconfiguring circuit applies the control signal to the multiplex signal separating circuit, receiving the output of the interface control circuit and reconfiguring display data corresponding to the program data in accordance with the identification data.
[0061] The information reconfiguring circuit includes a network selection control circuit for performing control to repeat first processing of reconfiguring the cyclic program data for at least the first predetermined time and second processing of selecting another network and reconfiguring the program data of the selected network at intervals of the second predetermined time.
[0063] According to further another aspect, the invention provides a digital signal receiving device in a communication system for transmitting a plurality of program data each divided into a plurality of packets taking the form of a packet stream and multiplexed into main signal data, each of the packets including an attribute data specifying one of a plurality of networks belonging to the corresponding program data, and at least one of the networks providing program data of a cyclic type containing information contents to be broadcasted within a first predetermined time and to be renewed at intervals of a second predetermined time, comprising: a multiplex signal separating circuit, an information reconfiguring circuit and a display device.
[0064] The multiplex signal separating circuit receives the packet stream, and extracts corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
[0065] The multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after buffering the same.
[0066] The information reconfiguring circuit applies the control signal to the multiplex signal separating circuit, receiving the output of the interface control circuit and reconfiguring display data corresponding to the program data.
[0067] The information reconfiguring circuit includes a network selection control circuit for performing control to repeat first processing of reconfiguring cyclic program data for at least a first predetermined time and second processing of selecting another network and reconfiguring the program data of the selected network at intervals of a second predetermined time; and a timing detecting circuit for determining a time of start of acquiring the packet data for reconfiguring the display data after issuing the control signal for switching the networks.
[0069] Accordingly, the invention has such a major advantage that, in the operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, the digital signal receiving device can prevent output of information sent over a last selected network after switching of the network.
[0070] Another advantage of the invention is that, for the operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, the digital signal receiving device can employ a receiver portion and a data reconfiguring portion which have simplified structures and therefore require a low manufacturing cost.
[0071] Yet another advantage of the invention is that, in the operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, the digital signal receiving device can efficiently acquire the data over the plurality of networks.
[0072] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
[0073]
Fig. 1. is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 100 of a first embodiment;
Fig. 2 is a schematic block diagram showing by way of example an outer appearance of the FM multiplex broadcast receiving device 100 of the first embodiment;
Fig. 3 is a diagram showing a structure of a data group in FM multiplex broadcast signals;
Fig. 4 is a flowchart showing an operation of a CPU 40 of the first embodiment;
Fig. 5 is a diagram showing a structure of ID data of a second embodiment;
Fig. 6 is a timing chart showing a sending frequency of VICS information;
Fig. 7 is a flowchart showing an operation of a CPU 40 of a third embodiment;
Fig. 8 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 200 of a fourth embodiment;
Fig. 9 is a fragmentary block diagram specifically showing the FM multiplex broadcast receiving device 200 shown in Fig. 8;
Fig. 10 is a diagram showing a format of data issued from an LMSK demodulation circuit;
Fig. 11 is a flowchart showing an operation of a CPU 52 of the fourth embodiment;
Fig. 12 shows specifications of the FM multiplex broadcast;
Fig. 13 is a diagram showing a structure of program data;
Fig. 14 is a schematic block diagram showing a structure of a first FM multiplex broadcast receiving device 10 in the prior art;
Fig. 15 is a schematic block diagram showing a structure of a second FM multiplex broadcast receiving device 80 in the prior art; and
Fig. 16 is a schematic block diagram showing a modification of the FM multiplex broadcast receiving device 10 in Fig. 14.
Best Mode for Carrying Out the Invention
[First Embodiment]
[0074] Fig. 1 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 100 of a first embodiment of the invention.
[0075] FM multiplex broadcast receiving device 100 includes an antenna 12 receiving FM radio wave, an FM tuner portion 14 which receives and frequency-demodulates the output of antenna 12, an FM multiplex decoding portion 15 which receives the output of FM tuner portion 14 and outputs corresponding digital signals by extracting FM multiplex signals and correcting errors, and a personal computer 120 which receives the digital signals, forms display unit data (page data) and displays corresponding characteristics and others.
[0076] FM multiplex broadcast receiving device 100 differs from conventional FM multiplex broadcast receiving device 10 shown in Fig. 14 in the following structures. In FM multiplex broadcast receiving device 100, FM multiplex decoding portion 15 extracts the FM multiplex signals from the signals which are FM-demodulated by FM tuner portion 14, and issues the digital signals as packet data to personal computer 120, which reconfigures the packet data into the program data and displays the same.
[0077] Thus, the FM multiplex broadcast signals received by antenna 12 are synchronously detected in an FM demodulating circuit 2 in FM tuner portion 14 with a local oscillating wave issued from a phase-locked loop circuit 4 (which will be referred to as a "PLL circuit" hereinafter), and are issued to FM multiplex decoding portion 15 through a buffer 6.
[0078] FM multiplex decoding portion 15 receives the FM-demodulated signals through a buffer circuit 8, and a band-path filter 18 takes out signal components in a predetermined frequency region from the received signals. Thereafter, demodulation LSI 20 performs LMSK demodulation to extract the FM multiplex signals.
[0079] A CPU 26 receives the output of demodulation LSI 20, and issues packet data after performing appropriate processing such as block synchronization of the received data and error correction. If packet data containing an uncorrectable error is present, CPU 26 selects and issues only the data required for display after deleting the data containing the uncorrectable error.
[0080] A RAM 28 functions as a buffer which receives the output of CPU 26 and issues the data to an interface 30.
[0081] An address decoder 32 operates to issue the data from interface 30 when it detects that CPU 26 accesses personal computer 120.
[0082] A controller 34 usually receives data sent from interface 30, and sends the data to personal computer 120. During boot-up of the device or the like, however, controller 34 performs initial setting between the interfaces based on data stored in a ROM 36.
[0083] Personal computer 120 which is a host PC receives the packet data sent from FM multiplex decoding portion 15 through an interface 38. A CPU 40 receives the output data, i.e., packet data from interface 38, and extracts data blocks from the data packet in accordance with a hierarchical structure shown in Fig. 10. Then, CPU 40 reconfigures the data groups from the extracted data blocks, and performs error correction on the data groups. Further, CPU 40 extracts data heads and data unit groups, which correspond to page data, from the data group data in the data group, and reconfigures the program data.
[0084] CPU 40 sends a channel select instruction to CPU 26 in FM decoding portion 15 through interfaces 38 and 30 in accordance with data applied from an input portion 46 or data stored in a memory 44 as will be described later. CPU 26 controls FM tuner portion 14 to select the intended network based on this channel select instruction.
[0085] Based on the program data thus reconfigured, CPU 40 issues corresponding display data to a display portion 42, which outputs corresponding character or graphic information based on the received display data.
[0086] For example, in a personal computer of a hand-held type, display portion 42 is formed of a liquid crystal flat panel display or the like, and has a display region of a resolution of 640 x 400 dots or more.
[0087] Fig. 2 schematically shows a notebook-size personal computer 120 and a PC card, which form FM multiplex broadcast receiving device 100 shown in Fig. 1.
[0088] In this structure, FM decoding portion 15 takes the form of the PC card, and is removably attached to personal computer 120. FM tuner portion 14 is connected to FM multiplex decoding portion 15 via a connection cord. According to the above structure, the FM tuner portion 14 can be located remote from personal computer 120 for preventing mixing of noises, which are produced from personal computer 120, into the received signal.
[0089] Naturally, FM tuner portion 14 and FM multiplex decoding portion 15 may be integrated for improving portability in contrast to the structure shown in Fig. 2, wherein FM tuner portion 14 and FM multiplex decoding portion 15 are connected via the connection code.
[0090] Description will now be given on an operation of FM multiplex broadcast receiving device 100 in Fig. 1 and particularly an operation of CPU 40.
[0091] Before describing the operation of CPU 40 in personal computer 120 in FM multiplex broadcast receiving device 100, a data structure of the FM multiplex broadcast signals forming the precondition of the operation is first described more in detail.
[0092] Fig. 3 schematically shows an example of the structure of the data group shown in Fig. 12. The data group includes at its leading end a heading start code (SOH) indicating start of the data group, and also includes in the subsequent positions a data group link code, which is a flag indicating existence and absence of coupling between data groups, and a data group size data indicating the number of bytes of the data group data. The data group data, which is a main portion of the data to be transmitted, is present in the position following the above, and is followed by an NULL region for length control, which is performed to set the data group length to an integer multiple of the data block length, an end code indicating the end of the data group, and a CRC code for error correction of the data group.
[0093] The data group data also contains data indicating whether VICS data is dynamic data or static data, as will be described later.
[0095] After start of operation (step S102), CPU 40 performs the channel selection in accordance with an instruction externally applied to input portion 46, and more specifically determines whether switching of the network is instructed or not (step S104).
[0096] When switching is instructed, CPU 40 resets a variable n, which is used for counting the number of packet data applied from FM multiplex decoding portion 15, to 0 (step S106). Subsequently, CPU 40 determines whether interrupt occurs for data transmission from the FM multiplex decoding portion or not (step S108).
[0097] Meanwhile, if switching of the network is not instructed, CPU 40 advances the process to step S108 (step S104).
[0098] If it is determined that the interrupt for data transfer does not occur in step S108, the process returns to step S104.
[0099] If it is determined the interrupt for data transfer occurs (step S108), comparison in magnitude between variable n and a predetermined number N is performed (step S110).
[0100] If n > N, i.e., if reading of the packet data of a predetermined number of more is already completed (step S110), CPU 40 determines that the data supplied after this is packet data sent over the new switched or selected network. Based on this determination, CPU 40 reads in the data, and returns the process to step S104 (S112).
[0101] If n > N is not satisfied, i.e., if reading of the packet data of the predetermined number N is not yet completed (step S110), CPU 40 abandons the data already taken (step S114), and returns the processing to step S104 after incrementing the value of variable n by one (step S116).
[0102] In the above manner, it is possible to prevent CPU 40 from reconfiguring the data sent from the last selected network, i.e., the network which was selected before the switching, and issuing the same to display device 42 even in the case where the packet data is asynchronously taken in from FM multiplex decoding portion 15.
[0103] In the above description, CPU 40 abandons the packet data of the predetermined number N after instruction of the network switching. However, such a structure may be employed that CPU 40 does not take in data until a predetermined time elapses after instruction of the network switching.
[0104] An operation of the latter structure is expressed inside the parentheses in Fig. 4, and will now be described below.
[0105] After start of the operation (step S102), CPU 40 performs channel select operation in accordance with the instruction externally applied to the input 46 and, in other words, determines whether switching of the network for signal reception is instructed or not.
[0106] If the switching is instructed, CPU 40 resets a count of a timer 41 (step S106). Subsequently, CPU 40 determines whether the interrupt for data transfer from the FM multiplex decoding portion occurs or not (step S108).
[0107] If the switching of the network is not instructed, CPU 40 advances the processing to step S108 (step S104).
[0108] If it is determined that the interrupt for data transfer does not occur in step 108, the processing returns to step S104.
[0109] If it is determined that the interrupt for data transfer occurs (step S108), comparison is then made between the time counted by the timer and the predetermined time t (step S110).
[0110] If the time t has already elapsed (step S110), CPU 40 determines that the data taken in thereafter is packet data sent over a new selected network, and thereby CPU 40 reads in the data and returns the processing to step S104 (step S112).
[0111] If the time t has not elapsed (step S110), CPU 40 returns the processing to step S104 (step S116).
[0112] In the above manner, it is likewise possible to prevent CPU 40 from reconfiguring the data sent from the last selected network, and issuing the same to display device 42 in the case where the packet data is asynchronously taken in from FM multiplex decoding portion 15.
[Second Embodiment]
[0113] In the first embodiment, it is not particularly determined whether the data taken by CPU 40 is the data sent over the last selected network or the data sent over the new selected network, and reconfiguration of the program data from the packet data is not performed until the packet data of the predetermined number are taken in, or before the predetermined tine elapses. Accordingly, even when the device has received data over the new selected network, the received data is unconditionally abandoned in the practical operation. Conversely, the operation cannot be performed stably unless the predetermined number N and the predetermined time t are determined in view of such wasteful data to be abandoned.
[0114] However, the foregoing waste of data can be prevented if it is possible to determine whether the data received by CPU 40 is data sent after instruction of the network switching or not.
[0115] A digital signal receiving device of a second embodiment has a structure which is basically similar to that of the digital signal receiving device 100 of the first embodiment, but differs therefrom in operation of CPU 26 of FM multiplex decoding portion 15 in the structure of digital signal receiving device 100 shown in Fig. 1 as described below.
[0116] When CPU 26 receives the data (i.e., data in layer 3 or 4) from demodulation LSI 20 to be transferred to host PC, CPU 26 adds identification data, from which the channel of the received data can be identified, to the received data. CPU 26 mixes units of data, which are sent from the respective channels and carry the identification data added thereto, in the predetermined order, and transfers the same to the host PC.
[0117] Fig. 5 conceptually shows a structure of the data format to which the above identification data (which will be referred to as an "ID" hereinafter) is added.
[0118] In a first example, a value of a frequency of the network transmitting the received data may be added as the ID to the data. In a second example, a parameter corresponding to the reception frequency in a one-to-one relationship may be added as the ID, in which case a value of 1 is can be uses as the ID when the received signal frequency is 80.2 MHz, and a value of 2 can be used as the ID when the received signal frequency is 85.1 MHz.
[0119] In a third example, such a structure may be employed that only a flag is set on, and in other words, the value of ID is set to "1" only in the first data sent over a new selected network. In this case, data which follow the data bearing the ON flag, and thus carry the flags of "0" are determined as the data after the channel selection.
[0120] By receiving the data carrying the ID, CPU 40 can determine a point in time from which data sent over the new selected network starts after instruction of the network switching.
[0121] The structure described above does not require a plurality of signal receiving systems even if the structure receives data over the plurality of switchable networks for transferring the data to the host PC.
[0122] Further, the above structure can reduce a load against software processing on the host PC side.
[Third Embodiment]
[0123] The second embodiment has been discussed in connection with the structure for providing a delimiter between the data sent over the new selected network and the data sent over the last selected network in the operation of switching the network for signal reception.
[0124] As already described, it is likewise important to detect the delimiter in the data for completely receiving difference services such as news information and VICS information.
[0125] Thus, in the structure including the PC card and the host PC connected via the interface, prime importance is placed on acquisition of information over a plurality of networks rather than real-time output of information in some cases. In these cases, such a structure may be employed that employs only one signal receiving system, and can successively scan the plurality of networks. Even in this structure, however, a delimiter in information provided by switching the networks cannot be detected on the host PC side.
[0126] As will be described below, the above structure can improve the scanning efficiency by performing the scanning in accordance with properties such as VICS information.
[0127] A structure of a digital signal receiving device of the third embodiment is basically similar to that of the digital signal receiving device 100 of the first embodiment in that the delimiter is provided in the data, but differs therefrom in operation of CPU 40 in the structure of the host PC shown in Fig. 1.
[0128] The digital signal receiving device of the third embodiment may have a structure, which is basically similar to that of digital signal receiving device 100 of the second embodiment in that the above data delimiter is detected, but differs therefrom in the operation of CPU 40 in the structure of the host PC.
[0129] Fig. 6 is a timing chart showing timing for sending VICS information. The VICS information is renewed every five minutes, but sending of dynamic information (i.e., information changing ceaselessly) such as traffic jam information, which indicates degrees of jamming on respective roads, respectively, is completed within first one minute. The remaining time is used for retransmitting static information such as map information, which does not change over time.
[0130] The purpose of always retransmitting the static information as described above is to allow reproduction of the whole traffic information on the display device whenever the receiving side starts the signal reception.
[0131] In other words, once the static information is completely received, it is not necessary to receive the same again unless change in program itself, which requires change even in static information, is performed.
[0132] Accordingly, such a structure can be employed that automatically scans the network of dynamic information at a frequency of 5 minutes (or an integer multiple of 5 minutes) after reception of the dynamic information is once confirmed, and returns the operation to reception from the former or initial channel upon every completion of reception of the dynamic information.
[0134] After start of the operation (step S202), CPU 40 selects an A channel transmitting VICS information (step S204).
[0135] Subsequently, CPU 40 stands by based on the data in the data group data until start of reception of the dynamic data from the A channel (step S204). When start of reception of the dynamic data is detected (step S206), CPU 40 resets timer 41 (step S208), and starts the counting operation.
[0136] Until reception of the next dynamic data, CPU 40 keeps the standby state (step S210). When CPU 40 detects reception of the dynamic data again (step S210), it acquires the send timing of the dynamic data, i.e., the frequency of the VICS information (step S212). In parallel with the above processing, static data is acquired, utilizing a period from step S206 to step S212.
[0137] Thereafter, CPU 40 stands by until it externally receives the channel select instruction (step S214).
[0138] When the channel select instruction is externally supplied, CPU 40 sends an instruction to select, e.g., the A channel (step S216).
[0139] Subsequently, CPU 40 stands by until it detects start of reception of the dynamic data (step S218).
[0140] When CPU 40 detects the start of reception of the dynamic data (step S218), CPU 40 resets timer 41 and starts the counting operation (step S220).
[0141] When CPU 40 detects complete reception of the dynamic data of the A channel, it instructs selection of a B channel (step S224).
[0142] CPU 40 receives data from the B channel (step S226), and determines whether the count of the timer reaches the send frequency of VICS information or not (step S228). If the count has not yet reached the send frequency, it continues reception of the data from the B channel (step S226). If the count reaches the send frequency, processing returns to step S216.
[0143] Owing to the above structure, it is possible to scan efficiently the reception of the program, in which dynamic data and static data are alternately sent, and the reception of the program sent over another network. Further, even in the case of asynchronously transmitting data, CPU 40 can selectively acquire the information on the new selected network after instructing switching of the network.
[0144] In the above structure, the send frequency of the VICS information is acquired by monitoring the same for one period after start of the operation of CPU 40. Alternatively, if the send frequency is fixed in advance, another structure may be employed. For example, data of the send frequency is stored in advance in memory 44 of the host PC.
[0145] Such a structure may be employed that CPU 26 in the FM multiplex decoding portion in Fig. 1 additionally performs the operation of CPU 40.
[Fourth Embodiment]
[0146] The third embodiment has been described in connection with the structure, in which only one signal receiving system can be used for scanning the multiple networks because prime importance is placed on acquisition of information and therefore interruption of sound or the like does not cause a problem.
[0147] However, in a system such as an on-vehicle system which is not allowed to cause interruption of sound and others, at least two signal receiving systems are required for completely receiving data over a plurality of networks.
[0148] The fourth embodiment will now be described below in connection with a structure of a digital signal receiving device 200 which can be effectively used for the above case.
[0149] Fig. 8 is a schematic block diagram, which shows the structure of the digital signal receiving device 200 of the fourth embodiment, and is comparable to Fig. 15 showing the structure of the digital signal receiving device 80 in the prior art.
[0150] The structure of digital signal receiving device 200 differs from the structure of the digital signal receiving device 80 in the following two points.
[0151] First, digital signal receiving device 200 includes two FM demodulating circuits 17a and 17b, two filters 18a and 18b, and two LMSK demodulating circuits 25a and 25b.
[0152] Secondly, an I/F portion 50, which receives the outputs of LMSK demodulating circuits 25a and 25b, adds corresponding ID to each data similarly to the second embodiment, and outputs the data to the host PC in a mixed fashion, i.e., in a time-sharing manner.
[0153] Structures other than the above are similar to those of the digital signal receiving device 80 in the prior art. The same parts and portions bear the same reference numbers, and will not be discussed below.
[0154] Although not discussed, a host PC 120 in Fig. 8 includes block 45, CPU 40, timer 41, display portion 42, memory 44 and input portion 46 similarly to the structure in Fig. 1.
[0155] Fig. 9 is a block diagram showing more specifically structures of I/F portion 50 and LMSK demodulating circuits 25a and 25b. I/F portion 50 includes a CPU 52, which receives the outputs of LMSK demodulating circuits 25a and 25b, and adds corresponding ID thereto, respectively, and an I/F circuit 56 which receives the outputs of CPU 52, and sends the data to an interface on the host PC side. CPU 52 includes a random access memory 54 (which will be referred to as a "RAM" hereinafter) operating as a buffer, as will be described later.
[0156] CPU 52 responds to activation of one of interrupt signals 1 and 2, which are issued from LMSK demodulating circuit 25a and 25b for indicating completion of the data reception, respectively, and thereby issues internal clock CLK1 or CLK2 to the side which issued the active interrupt signal.
[0157] The LMSK demodulating circuit which receives internal clock CLK1 or CLK2 issues data DATA1 or DATA2 to CPU 52 in synchronization with the received internal dock CLK1 or CLK2. CPU 52 adds the ID already described with reference to Fig. 5 to the received data, and successively outputs the data to I/F circuit 56.
[0158] Accordingly, the data, which are received over the two networks and carry the ID added thereto, are issued from I/F circuit 56 in a mixed fashion and in a time-sharing manner.
[0159] Fig. 10 conceptually shows an example of a format of data issued from LMSK demodulating circuits 25a and 25b.
[0160] Data CNT1 which is a parameter indicating the state of signal reception as well as data CNT2 indicating a block number are present before the data in layer 3 of 22 bytes.
[0162] After start of the operation (step S302) in Fig. 11, CPU 52 determines whether interrupt from LMSK demodulating circuit 25a receiving signals from the A channel is present or not (step S304). If interrupt is present, reading of data (of 24 bytes) from LMSK demodulating circuit 25a is performed (step S306).
[0163] Subsequently, CPU 52 adds ID to the read data (step S308), and stores the same in RAM 54 (step S310).
[0164] If interrupt from LMSK demodulating circuit 25a is not present, CPU 52 advances the processing to step S312.
[0165] Then, CPU 52 determines whether interrupt from LMSK demodulating circuit 25b is present or not (step S312). If the interrupt is present, data (of 24 bytes) is read from LMSK demodulating circuit 25b (step S314).
[0166] Subsequently, CPU 52 adds ID to the read data (step S316), and stores the same in RAM 54 (step S318).
[0167] If interrupt from LMSK demodulating circuit 25b is not present, CPU 52 advances the processing to step S320.
[0168] CPU 52 determines whether the data is stored in RAM 54 or not (step S320). If the data is stored, the data is transferred to the host PC (step S322).
[0170] According to the above structures, data can be efficiently acquired from the multiple networks by the simple structure, compared with the structure provided with two complete signal receiving systems as shown in Fig. 16, without interrupting the output of information which is being received over the network. Further, even in the case of asynchronously transmitting the data, CPU 40 can selectively acquire the information over the new selected network after sending an instruction of the network switching.
[0171] Although the present invention has been described and illustrated in detail, it is dearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
1. A digital signal receiving device in a communication system for transmitting a plurality
of program data each divided into a plurality of packets taking the form of a packet
stream and multiplexed into main signal data, each of said packets including an attribute
data specifying one of a plurality of networks belonging to the corresponding program
data, comprising:
multiplex signal separating means (100) for receiving said packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same, wherein
said multiplex signal separating means includes:
demodulating means (14) for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal;
multiplex signal demodulating means (20) for receiving the output of said demodulating means, and extracting said multiplex signal; and
multiplex signal decoding means (26) for receiving the output of said multiplex signal demodulating means, extracting the plurality of packet data formed of the corresponding digital signal and issuing said packet data after adding identification data to each of said packet data in accordance with said attribute data.
2. The digital signal receiving device according to claim 1, wherein
said multiplex signal separating means is included in a PC card, and
said PC card further includes interface means (30, 34) capable of externally transmitting the data and the control signal.
3. The digital signal receiving device according to claim 1, further comprising:
information reconfiguring means (120) for applying the control signal to said multiplex signal separating means, receiving the output of said multiplex signal decoding means, reconfiguring display data corresponding to said program data in accordance with said identification data and outputting the same; and
display means (42) for outputting said display data.
4. The digital signal receiving device according to claim 3, wherein
said information reconfiguring means and said display means are included in a personal computer; and
said multiplex signal separating means is included in a PC card, and is connected to said personal computer via an interface portion (30, 34) detachable from said personal computer.
5. A digital signal receiving device in a communication system for transmitting a plurality
of program data each divided into a plurality of packets taking the form of a packet
stream and multiplexed into main signal data, each of said packets including an attribute
data specifying one of a plurality of networks belonging to the corresponding program
data, comprising:
multiplex signal separating means for receiving said packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same, wherein
said multiplex signal separating means includes:
first demodulating means (17a) for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal;
first multiplex signal demodulating means (25a) for receiving the output of said first demodulating means, and extracting said multiplex signal;
second demodulating means (17b) for receiving and demodulating the carrier wave carrying the multiplex signal corresponding to the selected network in accordance with the control signal;
second multiplex signal demodulating means (25b) for receiving the output of said second demodulating means, and extracting said multiplex signal; and
multiplex signal decoding means (50) for receiving the outputs of said first and second multiplex signal demodulating means, extracting a plurality of first packet data and a plurality of second packet data formed of the corresponding digital signals, and issuing said first and second packet data in a time-sharing manner after adding identification data to each of said first and second packet data depending on whether the packet data is an output of said first or second multiplex decoding means.
6. The digital signal receiving device according to claim 5, wherein
said multiplex signal separating means is included in a PC card, and
said PC card further includes interface means capable of externally transmitting the data.
7. The digital signal receiving device according to claim 5, further comprising:
information reconfiguring means (120) for applying the control signal to said multiplex signal separating means, receiving the output of said interface control means, reconfiguring display data corresponding to said program data in accordance with said identification data and outputting the same; and
display means for outputting said display data.
8. The digital signal receiving device according to claim 7, wherein
said information reconfiguring means and said display means are included in a personal computer; and
said multiplex signal separating means is included in a PC card, and is connected to said personal computer via an interface portion detachable from said personal computer.
9. A digital signal receiving device in a communication system for transmitting a plurality
of program data each divided into a plurality of packets taking the form of a packet
stream and multiplexed into main signal data, each of said packets including an attribute
data specifying one of a plurality of networks belonging to the corresponding program
data, comprising:
multiplex signal separating means for receiving said packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same,
said multiplex signal separating means including:
demodulating means for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal,
multiplex signal demodulating means for receiving the output of said demodulating means, and extracting said multiplex signal, and
multiplex signal decoding means for receiving the output of said multiplex signal demodulating means, extracting the plurality of packet data formed of the corresponding digital signals and issuing said packet data after buffering the same;
information reconfiguring means for applying the control signal to said multiplex signal separating means, receiving the output of said multiplex signal decoding means, reconfiguring display data corresponding to said program data and outputting the same,
said information reconfiguring means including timing detecting means (41) for determining a time of start of acquisition of the packet data for reconfiguring said display data after issuing the control signal for switching said networks; and
display means for outputting said display data.
10. The digital signal receiving device according to claim 9, wherein
said information reconfiguring means determines the time of starting said acquisition by measuring a predetermined time after issuing the control signal of switching said network.
11. The digital signal receiving device according to claim 9, wherein
said information reconfiguring means determines the time of starting said acquisition by detecting the fact that the number of the received packet data reaches a predetermined value after issuing the control signal of switching said network.
12. A digital signal receiving device in a communication system for transmitting a plurality
of program data each divided into a plurality of packets taking the form of a packet
stream and multiplexed into main signal data, each of said packets including an attribute
data specifying one of a plurality of networks belonging to the corresponding program
data, and at least one of said networks providing program data of a cyclic type containing
information contents to be broadcasted within a first predetermined time and to be
renewed at intervals of a second predetermined time, comprising:
multiplex signal separating means for receiving said packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same,
said multiplex signal separating means including:
demodulating means for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal,
multiplex signal demodulating means for receiving the output of said demodulating means, and extracting said multiplex signal, and
multiplex signal decoding means for receiving the output of said multiplex signal demodulating means, extracting the plurality of packet data formed of the corresponding digital signals and issuing said packet data after adding identification data to each of said packet data in accordance with said attribute data;
information reconfiguring means (120) for applying the control signal to said multiplex signal separating means, receiving the output of said multiplex signal decoding means, reconfiguring display data corresponding to said program data in accordance with said identification data and outputting the same,
said information reconfiguring means including network selection control means (40) for performing control to repeat first processing of reconfiguring said cyclic program data for at least said first predetermined time and second processing of selecting another network and reconfiguring the program data of said selected network at intervals of said second predetermined time; and
display means (42) for outputting said display data.
13. A digital signal receiving device in a communication system for transmitting a plurality
of program data each divided into a plurality of packets taking the form of a packet
stream and multiplexed into main signal data, each of said packets including an attribute
data specifying one of a plurality of networks belonging to the corresponding program
data, and at least one of said networks providing program data of a cyclic type containing
information contents to be broadcasted within a first predetermined time and to be
renewed at intervals of a second predetermined time, comprising:
multiplex signal separating means for receiving said packet stream, and extracting corresponding digital signals in accordance with an externally supplied control signal for outputting the same,
said multiplex signal separating means including:
demodulating means for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal,
multiplex signal demodulating means for receiving the output of said demodulating means, and extracting said multiplex signal, and
multiplex signal decoding means for receiving the output of said multiplex signal demodulating means, extracting the plurality of packet data formed of the corresponding digital signals and issuing said packet data after buffering the same;
information reconfiguring means (120) for applying the control signal to said multiplex signal separating means, receiving the output of said multiplex signal decoding means, reconfiguring display data corresponding to said program data and outputting the same,
said information reconfiguring means including:
network selection control means (40) for performing control to repeat first processing of reconfiguring said cyclic program data for at least said first predetermined time and second processing of selecting another network and reconfiguring the program data of said selected network at intervals of said second predetermined time, and
timing detecting means (41) for determining a time of start of acquiring the packet data for reconfiguring said display data after issuing the control signal for switching said networks; and
display means for outputting said display data.