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(11) | EP 1 324 493 A2 |
(12) | EUROPEAN PATENT APPLICATION |
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(54) | Inductive load driving method and H-bridge circuit control device |
(57) An inductive load driving method and an H-bridge circuit control device in which
an erroneous operation is not caused by noises generated at a current detecting resistor
(RS). The current detecting resistor is inserted in an H-bridge circuit constructed to
cause the flow of a current to an inductive load (L) in both of forward and reverse
directions by four semiconductor switching elements (Q1-Q4) and flywheel diodes (D1-D4) respectively connected in reverse parallel to the semiconductor switching elements.
When a current flowing through the inductive load is controlled by a detection voltage
(VS) generated by the current detecting resistor, the value of the detection voltage
(VS) is ignored immediately after the connection of the inductive load to a power source.
There is no fear that an erroneous operation is caused by a rush current and/or a
through current. When a power source regeneration is made to decrease a switching
current, the inductive load is connected to the power source at a predetermined period
and a current flowing at that time is detected as the detection voltage (Vs). There is no fear that the current becomes too small or the transfer to a steady
is made while the current is large. |
BACKGROUND OF THE INVENTION
Field of the Invention
Description of the Related Art
SUMMARY OF THE INVENTION
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 shows one example of an H-bridge circuit control device according to the present invention;
Fig. 2 is a timing chart for explaining a steady operation of the H-bridge circuit control device;
Fig. 3 is a timing chart for explaining an operation when a variable reference voltage is changed over;
Fig. 4 is a timing chart for explaining an operation when a power source regeneration is being made;
Fig. 5 is a timing chart for explaining the situation of a decrease in current.when the power source regeneration is made;
Fig. 6 is a block diagram for explaining the path of a current supplied from a power source to an inductive load;
Fig. 7 is a diagram showing the current path of a commutation current flown in the case where an energy stored in the inductive load is released as a heat;
Fig. 8 is a diagram showing a current path in which a through current flows;
Fig. 9 is a diagram showing a current path in the case where an energy stored in the inductive load is regeneratively returned to the power source;
Fig. 10 is a diagram showing the path of a through current when the power source regeneration is made;
Fig. 11 is a circuit diagram for explaining the construction of a flip-flop used in the H-bridge circuit control device according to the present invention;
Fig. 12 shows a truth table of FF54 to FF57;
Fig. 13A is a graph for explaining a current flown in the case where a stepping motor is microstep-operated and Fig. 13B is a graph for explaining a current control method for H-bridge circuit control device according to the prior art.
DESCRIPTION OF THE PREFERRED EMBODIMENT
(1) Outline of Whole
Referring to Fig. 6, reference numeral 3 denotes a stepping motor control apparatus
which has an H-bridge circuit control device 2 according to an embodiment of the present
invention and an H-bridge circuit 4.
The H-bridge circuit 4 includes the H-bridge connection of PNP transistors Q1 and Q2 having flywheel diodes D1 and D2 respectively connected in reverse parallel thereto, NPN transistors Q3 and Q4 having flywheel diodes D4 and D3 connected in reverse parallel thereto, and an inductive load (or driving coil) L.
The base terminals of the transistors Q1 to Q4 are connected to the H-bridge circuit control device 2. The H-bridge circuit control
device 2 is constructed to cause the turn-on of any one of a set of PNP transistor
Q1 and NPN transistor Q3 and a set of PNP transistor Q2 and NPN transistor Q4 so that a current is caused to be flown from a power source to the inductive load
L in either a forward direction or a reverse direction, and it is constructed to cause
the turn-off of the transistor having been turned on in that state so that an energy
stored in the inductive load L causes a current to be flown through the flywheel diodes
D1 to D4.
The transistors Q1 to Q4, the flywheel diodes D1 to D4 and the H-bridge circuit control device 2 are formed in the same chip, thereby providing
a one-chip power IC structure.
A current detecting resistor RS constructed by discrete parts is inserted between the interconnected emitter terminals
of the NPN transistors Q3 and Q4 and the interconnected cathode terminals of the flywheel diodes D3 and D4. The cathode terminals of the flywheel diodes D3 and D4 are connected to a ground potential. Either a supply current 61 supplied from the power source 9 to the inductive load L by the turn-on of the set
of PNP transistor Q1 and NPN transistor Q3 or a supply current 62 supplied from the power source 9 by the turn-on of the set of PNP transistor Q2 and NPN transistor Q4 flows from the current detecting resistor RS to the ground potential so that a detection voltage VS having a value corresponding to the amplitude of the supply current 61 or 62 is outputted from one end of the current detecting resistor RS and is then inputted to the H-bridge circuit control device 2.
(2) Outline of Internal Block Diagram
The internal block diagram of the H-bridge circuit control device 2 is shown in Fig.
1.
The H-bridge circuit control device 2 has a control circuit 5. The control circuit
5 includes two 3-input NAND circuits 32 and 31, two 2-input AND circuits 33 and 34,
and inverters 301 and 302.
The output terminals of the 3-input NAND circuits 31 and 32 are connected to the base
terminals of the PNP transistors Q1 and Q2, respectively. The output terminals of the 2-input AND circuits 33 and 34 are connected
to the base terminals of the NPN transistors Q3 and Q4, respectively.
A transistor selecting line 20 introduced from the exterior is connected to one of
the input terminals of each of the 3-input NAND circuit 31 and the 2-input AND circuit
33. The transistor selecting line 20 is also connected to one of the input-terminals
of each of the 3-input NAND circuit 32 and the 2-input AND circuit 34 through the
inverter 301 or 302.
When a signal inputted from the selecting line 20 is "HIGH", the set of PNP transistor
Q1 and NPN transistor Q3 are allowed to turn on but the set of PNP transistor Q2 and NPN transistor Q4 are not allowed to turn on. When the signal is "LOW", the set of PNP transistor Q2 and NPN transistor Q4 are allowed to turn on but the set of PNP transistor Q1 and NPN transistor Q2 are not allowed to turn on. Accordingly, only one of the two sets is allowed to turn
on so that the power source 9 is not short-circuited. In the following, it is assumed
that the transistor selecting line 20 is "HIGH" and only the set of PNP transistor
Q1 and NPN transistor Q3 are allowed to turn on.
Inverters 303 and 304 are provided in the control circuit 5. An output terminal of the inverter 303 is connected to an input terminal of each of the 3-input NAND circuits 31 and 32
and the 2-input AND circuits 33 and 34. An output terminal of the inverter 304 is connected to the remaining input terminal of each of the 3-input NAND circuits
31 and 32. Accordingly, when the outputs of the inverters 303 and 304 are both "HIGH", the PNP transistor Q1 and the NPN transistor Q3 are both turned on so that a supply current 61 is supplied from the power source 9 to the inductive load L. When the output of the
inverter 303 is "LOW", the PNP transistor Q1 and the NPN transistor Q3 are both turned off irrespective of the output of the inverter 304. When the output of the inverter 303 is "HIGH" and the output of the inverter 304 is "LOW", the PNP transistor Q1 is turned off and the NPN transistor Q3 is turned on.
(3) Outline of Operation
Now provided that the outputs of the inverters 303 and 304 are both "HIGH" and hence the supply current is flowing through the inductive load
L, a detection voltage indicated by symbol VS in Fig. 2 is being generated across the detecting resistor RS.
When the output of the inverter 303 is turned into "LOW" from such a state, the PNP transistor Q1 is turned off so that a back electromotive force generated across the opposite ends
of the inductive load causes the flow of a commutation current 63 in a current path formed by the NPN transistor Q3, the current detecting resistor RS and the flywheel diode D3, as shown in Fig. 7. Thereby, an energy stored in the inductive load L is consumed
as a heat.
When the output of the inverter 303 is turned into "HIGH" again from the state in which the commutation current 63 is flowing, the PNP transistor Q1 is turned on so that the supply current 61 is supplied again from the power source to the inductive load L along the current
path shown in Fig. 6.
At this time, the flywheel diode D3 has a sudden change from a forward bias state to a reverse bias state. Therefore,
the diode characteristic of the flywheel diode D3 is lost only during a reverse recovery time Trr of the PN junction diode. As a result,
a part of a current 64 flown through the PNP transistor Q1 flows through the flywheel diode D3 in a reverse direction and then to the ground as a through current 66, as shown in Fig. 8.
At the same time, the potential of the side of the inductive load L connected to the
collector of the PNP transistor Q1 is suddenly changed from a potential lower than the ground potential by the forward
drop voltage of the flywheel diode D3 up to a power source voltage of the power source 9. Therefore, the remaining part
of the current 64 flowing through the PNP transistor Q1 turns into a rush current 65 which charges a stray capacitor C in the stepping motor existing in parallel to the
inductive load L. This rush current flows to the detecting resistor RS.
Due to the rush current 65, a noise VN shown by symbol VN in Fig. 2 will be generated at the current detecting resistor RS so that it is superimposed on the detection voltage VS.
A procedure for eliminating the noises VN will be explained on the basis of the operation of the H-bridge circuit control device
2. The H-bridge circuit control device 2 includes a comparator 24, a variable reference
voltage circuit 22, a voltage change-over detecting circuit 23 and an oscillator 26
in addition to the above-mentioned control circuit 5. The outputs of the comparator
24, the variable reference voltage circuit 22, the voltage change-over detecting circuit
23 and the oscillator 26 are connected so that they are inputted to the control circuit
5.
The oscillator 26 is constructed such that a sawtooth wave VT as shown in a timing chart of Fig. 2 is outputted by a resistor and a condenser externally
mounted. First explaining a relationship between the PNP and NPN transistors Q1 and Q3 and the sawtooth wave VT, the PNP transistor Q1 and the NPN transistor Q3 are turned off when the voltage of the sawtooth wave VT changes from the increase to the decrease. Accordingly, the current 61 begins to be supplied from the power source 9 to the inductive load L at a predetermined
period.
On the other hand, in the case where the turned-on state of the NPN transistor Q3 is kept so that the switching current flowing through the inductive load L is kept
in a predetermined amplitude, the PNP transistor Q1 is turned off when the detection voltage VS exceeds a variable reference voltage VR which the variable reference voltage circuit 22 outputs. Thereby, the commutation
current 63 shown in Fig. 7 is flown so that the energy stored in the inductive load L is consumed.
(4) Steady Operation
Explaining the operation of the H-bridge circuit control device in more detail, the
control circuit 5 is provided with a reference voltage circuit 50, a negative edge
detecting circuit 51, a positive edge detecting circuit 58, four FF's (flip-flops)
54 to 57, two 3-input NOR's 52 and 53 and inverters 305 and 306 in addition to the above-mentioned 3-input NAND circuit circuit 31 and so forth.
The sawtooth wave VT outputted by the oscillator 26 is inputted to the negative edge detecting circuit
51. The negative edge detecting circuit 51 outputs a signal, as shown by symbol V1 in Fig. 2, which becomes "HIGH" at the rising portion of the sawtooth wave VT and "LOW" at the falling portion thereof. This signal V1 is inputted to the inverter 305. The inverter 305 outputs an inverted version V2 of the signal V1 to the reset terminals R of the FF's 54 and 55.
Each of the four flip-flops (or FF's 54 to 57) has two comparators 91 and 92 each
including two NPN transistors and a constant current load, as shown in Fig. 11. The
comparators 91 and 92 are constructed such that one input and one output are cross-connected.
The remaining inputs are a set terminal S and a reset terminal R. Also, the output
of the comparator 92 on the reset terminal R side is taken out as an output terminal
Q to the exterior. In the FF's 54 to 57, the state of the output terminal Q is necessarily
"LOW" in a state in which the reset terminal is "HIGH" (reset terminal preference).
A relationship between the set and reset terminals S and R of each of the FF's 54
to 57 and the output terminal Q thereof is shown as a truth table by the following
Table 1. It is not necessarily required that the FF's 54 to 57 should be constructed
by bipolar transistors. They may be constructed by CMOS transistors so long as the
operation is attained according to the truth table as shown in Fig. 12..
During a time when the voltage of the sawtooth wave VT is increasing, the reset terminals R of the FF's 54 and 55 are kept in "HIGH" states
and hence the output terminals Q thereof are kept in "LOW" states. Since the output
terminal Q of the FF 54 is connected to the 3-input NAND circuit 31 and the 2-input
AND circuit 33 through the inverter 303, "HIGH" is inputted to the 3-input NAND circuit 31 and the 2-input AND circuit 33
during the time when the voltage of the sawtooth wave VT is increasing.
Now provided that the output terminal Q of the FF 56 is kept in a "HIGH" state, the
"HIGH" signal outputted by the FF 56 is inputted to the 3-input NOR's 52 and 53 so
that signals outputted by the 3-input NOR's 52 and 53 are kept "LOW" irrespective
of the states of the remaining inputs.
Since the kept "LOW" is inputted to the set terminal S of the FF 54, the output terminal
Q thereof is kept in a "LOW" state. Accordingly, the inverter 303 continues to output "HIGH" to the 3-input NAND circuit 31 and the 2-input AND circuit
33.
The selecting line 20 assumes a "HIGH" state. The 3-input NAND circuit 31 and the
2-input AND circuit 33 cause the turn-on of the PNP transistor Q1 and the turn-on of the NPN transistor Q3, respectively, when all the input terminals of the NAND circuit 31 and all the input
terminals of the AND circuit 33 are "HIGH". Therefore, the NPN transistor Q3 remains turned on. The PNP transistor Q1 is turned on when the output of the inverter 304 is "HIGH" or the output terminal Q of the FF 54 is "LOW" and is turned off when the
output terminal Q of the FF 54 is "HIGH".
The inverter 304 is inputted with a signal which the FF 55 outputs and is shown by
symbol V3 in Fig. 2. The reset terminal R of the FF 55 is inputted with the signal V2 which the inverter 303 outputs. Accordingly, when the signal V1 outputted by the negative edge detecting circuit 51 turns into "LOW" and hence the
signal V2 turns into "HIGH", the reset terminal R of the FF 55 is raised. Thereby, the V3 outputted by the FF 55 turns into "LOW" so that the transistor Q1 is turned on.
On the other hand, the set terminal S of the FF 55 is inputted with the output VC of the comparator 24. Further, a non-inverted input terminal of the comparator 24
is inputted with the detection voltage VS. Also, an inverted input terminal of the comparator 24 is inputted with the variable
reference voltage VR which the variable reference voltage circuit 22 outputs.
The output VC of the comparator 24 is "LOW" when the supply current 61 flowing through the current detecting resistor RS is still small so that the detection voltage VS is below the variable reference voltage VR. When the supply current 61 increases so that the detection voltage VS exceeds the variable reference voltage VR, the output VC of the comparator 24 turns into "HIGH". Accordingly, when the detection voltage VS exceeds the variable reference voltage VR, the set terminal S of the FF 55 is raised so that the output voltage V3 turns into "HIGH". At this time, the PNP transistor Q1 is turned off.
When the voltage of the sawtooth wave VT begins to decrease after the turn-off of the PNP transistor Q1, the signal V2 outputted by the inverter 305 turns into "HIGH" so that the reset terminal R of the FF 55 is raised. Thereby, the
signal V3 outputted by the FF 55 turns into "LOW" so that the PNP transistor Q1 is turned on again.
At this time, since a rush current shown by symbol 65 in Fig. 8 flows through the current detecting resistor RS, the detection voltage VS having a pulse-like noise VN superimposed thereon will be inputted to the non-inverted input terminal of the comparator
24. In the case where the noise VN is larger than the variable reference voltage VR, a pulse shown by symbol VP in Fig. 2 will be outputted from the comparator 24.
The flywheel diode having a PN junction formed in a one-chip power IC has the length
of Trr equal to about 0.1 to 0.2 µsec. During Trr, the PNP transistor Q1 makes an active operation. Therefore, during the lapse of Trr, the potential of one
end of the stray capacitor C is changed from a potential lower than the ground potential
by the forward drop voltage of the flywheel diode D3 up to the power source voltage of the power source 9. Thereby, the rush current 65
flows until Trr expires. Accordingly, the width of the noise VN is the same as the length of Trr and the width of the pulse VP does not exceed the width of the noise VN.
A time from the beginning of decrease of the voltage of the sawtooth wave VT followed by the turn-on of the PNP transistor Q1 until the voltage of the sawtooth wave VT begins to increase again, that is, a period of time when the signal V2 is "HIGH", is set to have the width of about 2 µsec. Therefore, during at least a
time when the pulse VP is outputted from the comparator 24, the reset terminal R of the FF 55 is kept in
its "HIGH" state. Accordingly, even if the pulse VP raises the set terminal S of the FF 55, the output voltage V3 remains "LOW" and there is no fear that the rush current 65 causes the turn-off of the PNP transistor Q1.
During the period of time when the signal V2 is "HIGH", the detection voltage VS outputted by the current detecting resistor RS is thus ignored. Therefore, this period will be called a first blanking period B1. When the first blanking period B1 expires, the signal V2 inputted to the reset terminal R of the FF 55 turns into "LOW" so that the FF 55
turns into an operable state, thereby enabling the turn-off of the PNP transistor
Q1. After the turn into the operable state, the current 61 supplied from the power source 9 to the inductive load L increases. When the detection
voltage VS exceeds the variable reference voltage VR, the output VC of the comparator 24 turns into "HIGH". Thereby, the set terminal S of the FF 55
is raised so that the PNP transistor Q1 is turned off.
During the operation explained above, the NPN transistor Q3 remains turned on. Accordingly, when the PNP transistor Q1 is placed in the turned-off state, an energy stored in the inductive load L causes
the flow of a commutation current 63 in a current path, as shown in Fig. 7, which is formed by the NPN transistor Q3 and the flywheel diode D3. Thus, the energy is slowly attenuated while being consumed as a heat by the NPN
transistor Q3 and the flywheel diode D3.
The foregoing corresponds to the case where the variable reference voltage VR is fixed. The signal V3 outputted by the FF 55 turns into "LOW" at a fixed period to cause the turn-on of
the PNP transistor Q1 and the comparator 24 causes the turn-off of the PNP transistor Q1 at a fixed period. Therefore, the supply current 61 supplied from the power source 9 and the commutation current 63 for releasing the stored energy alternately flow through the inductive load L so
that a switching current formed thereby is kept in a fixed amplitude.
(5) Switching Current Attenuating Operation
Next, explanation will be made of the case where the variable reference voltage VR is decreased to decrease the switching current flowing through the inductive load
L.
A circuit for generating signals for changing over a reference voltage is provided
at the exterior of the H-bridge circuit control device 2, and reference voltage change-over
signals I0 and I1 outputted by the change-over signal generating circuit are inputted to the variable
reference voltage circuit 22.
Each of the reference voltage change-over signals I0 and I1 is a signal which takes two values of "HIGH" and "LOW". The variable reference voltage
circuit 22 is constructed such that it can output a variable reference voltage VR having four kinds of magnitudes corresponding to the combination of the values of
the reference voltage change-over signals I0 and I1.
The reference voltage change-over signals I0 and I1 are also inputted to the voltage change-over detecting circuit 23. When one of the
reference voltage change-over signals I0 and I1 is changed from "LOW" to "HIGH" so that the variable reference voltage VR from the variable reference voltage circuit 22 is decreased, the voltage change-over
detecting circuit 23 detects a positive edge indicating the change from "LOW" to "HIGH"
to outputs a pulse shown by symbol V5 in Fig. 3. This pulse V5 is inputted .to the reset terminal R of the FF 56 so that a signal V6 outputted from the output terminal Q of the FF 56 is changed from "HIGH" to "LOW".
This signal V6 is inputted to the 3-input NOR's 52 and 53, thereby starting an operation for decreasing
the switching current.
The 3-input NOR 53 is inputted with the signal V6 outputted by the FF 56 as well as the output V8 of a comparator 59 and the signal V1 outputted by the negative edge detecting circuit 51. The comparator 59 is constructed
such that it has an inverted input terminal inputted with a reference voltage V'R outputted by the reference voltage circuit 50 and a non-inverted input terminal inputted
with the sawtooth wave VT outputted by the oscillator 26 to compare the reference voltage V'R and the sawtooth wave VT and it provides the output V8 of "HIGH" during a time when the sawtooth wave VT exceeds the reference voltage V'R. Since the signal V6 is "low", a signal V11 outputted by the 3-input NOR 53 turns into "HIGH" when both the output V8 and the signal V1 outputted by the negative edge detecting circuit 51 turn into "LOW", as shown in
Fig. 4.
On the other hand, the 3-input NOR 52 is inputted with the voltage V6 outputted by the FF 56 as well as the output V8 of the comparator 59 and a signal outputted by the inverter 306 which inverts the output VC of the comparator 24.
At the beginning of decrease of the variable reference voltage VR, a current flowing through the inductive load L has little decrease and hence the
detection voltage is large. Therefore, the output VC of the comparator 24 is "HIGH" so that the 3-input NOR 52 is inputted with a "LOW"
signal from the inverter 306.
Also, the signal V6 is "LOW". Accordingly, an output signal of the 3-input NOR 52 takes "LOW" when the
output V8 of the comparator 59 is "HIGH" and takes "HIGH" when the output V8 of the comparator 59 is "LOW". Namely, the 3-input NOR circuit 52 operates as an
inverter for the comparator 59 in such a manner that an inverted version of the output
V8 or a signal shown by symbol V9 in Fig. 3 is outputted to the set terminal S of the FF 54 and the reset terminal
R of the FF 57.
The reset terminal R of the FF 54 is inputted with the signal V2 in a version of the output V1 of the negative edge detecting circuit 51 inverted by the inverter 305. The FF 54 is constructed such that the output terminal Q is always "LOW" in a state
in which the reset terminal R is "HIGH". Therefore, as shown by symbol V10 in Fig. 3, a signal outputted by the FF 54 takes "LOW" only during a time when the
voltage of the sawtooth wave VT is decreasing.
The signal V9 outputted by the 3-input NOR 52 and the signal V11 outputted by the 3-input NOR 53 are synchronous with each other. Therefore, when
the set terminal S of the FF 57 is "HIGH", the reset terminal R thereof is also "HIGH"
and hence the output terminal Q of the FF 57 is kept "LOW".
The signal V10 outputted from the FF 54 is applied to the 3-input NAND circuit 31 and the 2-input
AND circuit 33 after the inversion thereof by the inverter 303.
Though the signal V3 outputted from the FF 55 is inputted to the 3-input NAND circuit 31 after the inversion
thereof by the inverter 304, the set terminal S of the FF 55 is kept in its "HIGH" state until the current flowing
through the inductive load L finishes decreasing. At this time, the reset terminal
R of the FF 55 is inputted with the signal V2 which takes "HIGH" only during the time when the voltage of the sawtooth wave VT is decreasing. Since a preference to the input of the reset terminal R is made, the
signal V3 outputted by the FF 55 takes "LOW" during the time when the voltage of the sawtooth
wave VT is decreasing. This signal V3 is inputted to the 3-input NAND circuit circuit 31 after the inversion thereof by
the inverter 304.
Accordingly, only during a time when the signal V3 and the signal V10 are both "LOW", all of the input terminals of the 3-input NAND circuit 31 are "HIGH"
so that the PNP transistor Q1 is turned on. This time corresponds to the period of time when the voltage of the
sawtooth wave VT is decreasing. At this time, the signals inputted to the 2-input AND circuit 33 are
all "high". Therefore, the NPN transistor Q3 is also turned on so that a supply current 61 is supplied from the power source 9 to the inductive load L. Thereby, a current flows
through the current detecting resistor RS to generate a detection voltage VS.
This detection voltage VS and the variable reference voltage VR are compared by the comparator 24, and the output VC as the result of comparison is inputted to the 3-input NOR 52 through the inverter
306. When the voltage of the sawtooth wave VT begins to decrease, that is, in the period of Trr from an instant of time when the
PNP transistor Q1 and the NPN transistor Q3 are turned on, through currents 68 and 69 as shown in Fig. 10 will flow through the flywheel diodes D1 and D3. Since the current 68 of the through currents 68 and 69 flows through the current detecting resistor RS, noises will be superimposed on the detection voltage VS. Especially, if such noises are generated when the current flowing through the inductive
load L becomes sufficiently small so that the detection voltage VS is below the variable reference voltage VR, the noises make the circuit operation unstable.
In the H-bridge circuit control 2, even in the case where such noises are superimposed
on the detection voltage VS when the power source regeneration is made, "HIGH" is inputted to the 3-input NOR
52 until the sawtooth wave VT becomes below the variable reference voltage VR. A period of time until the voltage of the sawtooth wave VT becomes below the variable reference voltage VR after the voltage of the sawtooth wave VT begins to decrease, will be called a second blanking period B2. During the second blanking period B2, "HIGH" is inputted to one input terminal of the 3-input NOR 52 and hence the output
terminal Q of FF54 or FF57 is kept in its "LOW" state even if the superimposed noises
are inputted to the other input terminals of the 3-input NOR 52. Accordingly, even
if the noises are generated, there is no fear that the FF 54 and 57 make erroneous
operations.
As mentioned earlier, the output of the inverter 303 takes "HIGH" only during the period of time when the voltage of the sawtooth wave
VT is decreasing. Therefore, in a period of time when the voltage of the sawtooth wave
VT increases, that is, in a period of time when the signal V10 is "HIGH", the output of the inverter 303 is "LOW" and hence the PNP transistor Q1 and the NPN transistor Q3 are both turned on. At the time of change from the turn-on to the turn-off, a back
electromotive force is generated by an energy stored in the inductive load L so that
a regenerative current 67 flows in a path including the inductive load L, the flywheel
diode D2, the power source 9 and the flywheel diode D3, as shown in Fig. 9. Since this regenerative current 67 charges an output condenser included in the power source 9, the energy released from
the inductive load L moves toward the power source.
A time when the energy stored in the inductive load L is released by the regenerative
current 67, is shorter than that in the case where the energy stored in the inductive load L
causes the flow of the commutation current 63 so that it is consumed as a heat by the NPN transistor Q3, the flywheel diode D3 and the current detecting resistor RS. Thus, the current is quickly attenuated.
The regenerative current 67 does not pass through the current detecting resistor RS. Therefore, when the regenerative current 67 is flowing, the non-inverted terminal of the comparator 24 is connected to the ground
potential through the current detecting resistor RS so that the output VC of the comparator 24 takes "LOW". Since the output VC is outputted to the 3-input NOR 52 through the inverter 306, the output V9 of the 3-input NOR 52 takes "LOW" when the regenerative current 67 is flowing. Accordingly,
there is no fear that the set terminal S of the FF 54 is raised or the FF 57 is reset.
(6) Return to Steady Operation
(Other Embodiments)