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(11) | EP 0 955 679 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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| (54) |
Method of improving plug conductivity Methode zur Verbesserung der Stöpsel-Leitfähigkeit Méthode pour améliorer la conductivité d'un plot |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
BACKGROUND
1. Technical Field
[0001] This disclosure relates to stack capacitors for semiconductor devices and more particularly, to a high conductivity plug for stack capacitors.
2. Description of the Related Art
[0002] Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored by as a high or low bit depending on the state of the capacitor. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data thereto.
[0003] Stacked capacitors are among the types of capacitors used in semiconductor memories. Stacked capacitors are typically located on top of the transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device. As with many electrical devices, high conductivity is beneficial for performance characteristics of stacked capacitors.
[0004] In semiconductor memories, such as dynamic random access memories (DRAM), high dielectric constant capacitor formation processes include deposition of highly dielectric materials. In one type of high dielectric constant capacitors, a layer of high dielectric constant materials, such as barium strontium titanium oxide (BSTO), is deposited in an oxidized atmosphere.
[0006] Referring to FIGS. 1A and 1B, a structure 2 with stacked capacitors is shown. Stacked capacitors 3 include two electrodes a top electrode or storage node 4, usually platinum (Pt) and an electrode 12 separated by a dielectric layer 18. An access transistor 5 includes a gate 6 which when activated electrically couples a bitline 7 through a bitline contact 8 to a plug 14. Plug 14 connects to electrode 12 through a diffusion barrier 16 which stores charge in electrode 12.
[0007] A partial view of a conventional stacked capacitor 10 is shown in FIG 1B. Stacked capacitor 10 includes electrode 12, preferably formed of platinum (Pt). Electrode 12 is separated from plug 14 by diffusion barrier 16. Plug 14 is preferably polycrystalline silicon (polysilicon or poly). During processing, dielectric layer 18 is deposited on electrode 12. Dielectric layer 18 is typically a material with a high dielectric constant, for example BSTO. During the deposition of dielectric layer 18, oxide layers 20 and 21 form which are detrimental to the performance of the stacked capacitor. Diffusion barrier 16 is employed to prevent the formation of oxide layer 21.
[0008] Oxide layers 20 and 21 form if:
(a) silicon diffuses through diffusion barrier 16 and reacts with oxygen to form oxide 20 between diffusion barrier 16 and electrode 12;
(b) diffusion barrier 16 materials simply react with oxygen; and
(c) oxygen diffuses through diffusion barrier 16 and reacts with plug 14 to form oxide layer 21 between diffusion barrier 16 and plug 14.
[0009] Oxide layers 20 and 21 reduce the capacitance of stacked capacitor 10. Therefore, a need exists for improving capacitance of stacked capacitors by eliminating oxide layers adjacent to a barrier layer formed as a result of processing and diffusion. A further need exists for a method of increasing conductivity of a plug used in stacked capacitors.
SUMMARY OF THE INVENTION
[0010] The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween as defined in claim 1. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug.
[0011] In particularly useful methods of improving conductivity, the step of bombarding may include the step of bombarding by ion implantation. The step of bombarding may also include the step of bombarding the oxide with germanium ions. The step of bombarding preferably includes the step of adjusting an angle of incident ions to provide for improved mixing. The step of bombarding may further include the step of adjusting an energy and dose of incident ions to provide for improved mixing. The electrode preferably includes platinum, and the plug preferably includes polysilicon.
[0012] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:
FIG. 1A is a cross-sectional view of stacked capacitors on a semiconductor device in accordance with the prior art;
FIG. 1B is a cross-sectional view of a stacked capacitor in accordance with the prior art showing oxide layers formed;
FIG. 2 is a cross-sectional view of a stacked capacitor in accordance with the present invention showing ion implantation of oxide layers;
FIG. 3 is a cross-sectional view of a stacked capacitor showing an oxide layer between a diffusion barrier and an electrode mixed in accordance with the present invention;
FIG. 4 is a cross-sectional view of a stacked capacitor showing an oxide layer between a diffusion barrier and a plug mixed in accordance with the present invention;
FIG. 5 is a cross-sectional view of a stacked capacitor showing a diffusion barrier formed on an electrode and
FIG. 6 is a cross-sectional view of a stacked capacitor showing a diffusion barrier formed within an electrode .
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0014] The present disclosure relates to stack capacitors for semiconductor devices and more particularly, to a high conductivity plug for transferring charge to the capacitor electrode. The present invention includes ion implant processes to change an oxide layer into a conductive layer or to form an oxygen diffusion barrier inside an electrode to prevent oxide layers from forming. Changing the oxide layers to conductive layers may be performed using ion implantation (I/I). The oxygen diffusion barrier may be formed using plasma doping (PLAD) or plasma immersion ion implantation (PIII).
[0015] Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, FIG. 2 shows a stacked capacitor 100 in accordance with one aspect of the present invention. A plug 106 is formed inside a dielectric layer 108. Dielectric layer 108 may include silicon dioxide material. A diffusion barrier 110 is formed at a top portion of plug 106. Diffusion barrier 110 preferably includes TaN, CoSi, TiN, WSi, TaSiN or equivalent materials. An electrode 104 is formed on diffusion barrier 110. Electrode 104 is preferably formed from platinum although other conductive materials such as Iridium (Ir), Ruthenium (Ru) or Ruthenium oxide (RuO2) may be used. A high dielectric constant layer 102 is deposited on electrode 104. High dielectric constant layer 102 is preferably formed from BSTO. BSTO is preferably deposited at high temperatures. However, since high temperatures increase diffusion, BSTO deposition temperatures must be limited to reduce the diffusion of materials, such as oxygen. In the present invention however deposition temperatures for layer 102 may advantageously be increased without degrading performance as explained herein.
[0016] During the deposition of layer 102, an oxide layer 112 and/or an oxide layer 114 are formed as described above.
[0017] In accordance with the present invention ion implantation is performed to make oxide layers 112 and/or 114 conductive. In a preferred embodiment, germanium (Ge) is implanted into oxide layers 112 and/or 114. Other elements suitable for implantation include Si, C, and/or N. By controlling an angle, α, energy and dose, oxide layer 112 and/or 114 are well mixed with materials adjacent to the respective oxide layers, thereby increasing the conductivity between plug 106 and electrode 104. Even though Ge is an electrically neutral element, Ge bridges the adjacent conductive layers (electrode/diffusion barrier or diffusion barrier/plug) to substantially increase conductivity between plug 106 and electrode 104.
[0018] Ion implantation includes bombarding oxide layer 112 and/or 114 with ions having energies between about 30 and about 200 keV, preferably between about 50 and about 150 keV at doses of between about 1×1010 and about 1×1016 atoms/cm2, preferably between about 1×1014 and about 1×1015 atoms/cm2. In a preferred embodiment ions are introduced at an angle, α, between about 30° and about 60°.
[0019] Referring to FIG. 3, a stacked capacitor 101 is shown after ion implantation of Ge into oxide layer 112. A mixed region 116 is formed wherein atoms of adjacent materials such as from electrode 104 and diffusion barrier 110 are mixed together with oxide layer 112 to form a conductive composite thereby increasing the conductivity between electrode 104 and plug 106.
[0020] Referring to FIG. 4, a stacked capacitor 103 is shown after ion implantation of Ge into oxide layer 114. A mixed region 118 is formed wherein atoms of adjacent materials such as from diffusion barrier 110 and plug 106 are mixed together with oxide layer 114 to form a conductive composite thereby increasing the conductivity between electrode 104 and plug 106.
[0021] In alternate embodiments of the stacked capacitor not covered by the present invention, a diffusion barrier may be formed on or in the electrode to prevent oxygen and/or silicon from diffusing therethrough. Referring to FIG. 5, a partial stacked capacitor 200 is shown. Stacked capacitor 200 includes a diffusion barrier 202 which is provided and formed on electrode 104. Diffusion barrier 202 inhibits the diffusion of oxygen and silicon therethrough. Barrier 202 is formed prior to high dielectric constant layer 102 deposition (see FIG. 2) where oxygen may be introduced. Barrier 202 may be deposited on the surface of electrode 104 by a chemical vapor deposition process or by PIII or PLAD. In a preferred example, barrier 202 is formed on a surface of electrode 104 to permit improved conductivity between electrode 104 and plug 106 by preventing the diffusion of oxygen to a region between electrode 104 and plug 106. Barrier 202 may be sized to obviate the need for diffusion barrier 110 since diffusing oxygen through dielectric layer 102, deposition is inhibited by barrier 202. In the alternative, barrier 110 may be maintained, however more materials choices are available for the diffusion barrier 110 since oxygen concentration is reduced. For example, a material that is easier to process but has less oxygen diffusion inhibiting properties, may be substituted. For example, TiN may be used.
[0022] Referring to FIG. 6, a barrier 204 is formed below the surface of electrode 104. For example, a diffusion inhibiting material, such as nitrogen, may be introduced below the surface of electrode 104 by a PLAD or PIII process. The nitrogen is formed in a thin layer, from about 50 A (10 Å = 1 nm) to about 150 Å in thickness, preferably from about 70 Å to about 100 Å. In this way, the nitrogen layer functions as a diffusion barrier without degrading conductivity between electrode 104 and plug 106. Barrier 204 may be positioned and sized to obviate the need for diffusion barrier 110 (FIG. 2) since diffusing oxygen from conductive layer 102 deposition is inhibited by barrier 204. In the alternative, barrier 110 may be maintained, however more materials choices are available for the diffusion barrier 110 since oxygen concentration is reduced. In this way, a more easily processed material may be substituted. For example, TiN may be used.
[0023] PIII and PLAD include bombarding electrode 104 with ions having energies between 500 eV and about 10 keV, preferably between about 1 keV and about 5 keV, at doses of between about 1×1015 atoms/cm2 and about 1×1017 atoms/cm2, preferably between about 5×1015 atoms/cm2 and about 5×1016 atoms/cm2. Since PIII is an isotropic process and includes three dimensional doping, α is not relevant. PIII is performed at pressures of about 5 mTorr to about 300 mTorr, preferably 20 mTorr to about 100 mTorr.
[0024] Having described preferred embodiments for a stack capacitor with improved plug conductivity (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
1. A method of improving conductivity between an electrode (104) and a plug (106) in
a stacked capacitor wherein said electrode (104) is one of two electrodes of said
capacitor and is connected via said plug (106) to a storage node within an integrated
circuit and wherein an oxide (112 and/or 114) has formed between said electrode (104)
and said plug (106) comprising the steps of:
bombarding the oxide with ions; and
mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug.
2. The method as recited in claim 1, wherein the step of bombarding includes the step
of bombarding by ion implantation.
3. The method as recited in claim 1, wherein the step of bombarding includes the step
of bombarding the oxide with germanium ions.
4. The method as recited in claim 1, wherein the step of bombarding includes the step
of adjusting an angle of incident ions to provide for improved mixing.
5. The method as recited in claim 1, wherein the step of bombarding includes the step
of adjusting an energy and dose of incident ions to provide for improved mixing.
6. The method as recited in claim 1, wherein the electrode (104) includes platinum.
7. The method as recited in claim 1, wherein the plug (106) includes polysilicon.
1. Verfahren zum Verbessern der Leitfähigkeit zwischen einer Elektrode (104) und einem
Plug (106) bei einem gestapelten Kondensator, wobei die Elektrode (104) eine von zwei
Elektroden des Kondensators ist und über das Plug (106) mit einem Speicherungsknoten
in einer integrierten Schaltung verbunden ist und ein Oxid (112 und/oder 114) zwischen
der Elektrode (104) und dem Plug (106) entstanden ist, mit den folgenden Schritten:
Bombardieren des Oxids mit Ionen und
Mischen des Oxids mit Materialien der Elektrode und des Plugs zur Erhöhung einer Leitfähigkeit zwischen Elektrode und Plug.
2. Verfahren nach Anspruch 1, wobei der Schritt des Bombardierens den Schritt des Bombardierens
durch Ionenimplantierung beinhaltet.
3. Verfahren nach Anspruch 1, wobei der Schritt des Bombardierens den Schritt des Bombardierens
des Oxids mit Germaniumionen beinhaltet.
4. Verfahren nach Anspruch 1, wobei der Schritt des Bombardierens den Schritt des Justierens
eines Winkels einfallender Ionen beinhaltet, um ein verbessertes Mischen zu ermöglichen.
5. Verfahren nach Anspruch 1, wobei der Schritt des Bombardierens den Schritt des Justierens
einer Energie und Dosis einfallender Ionen beinhaltet, um ein verbessertes Mischen
zu ermöglichen.
6. Verfahren nach Anspruch 1, wobei die Elektrode (104) Platin enthält.
7. Verfahren nach Anspruch 1, wobei das Plug (106) Polysilizium enthält.
1. Procédé pour améliorer la conductivité entre une électrode (104) et un plot (106)
dans un condensateur empilé, dans lequel l'électrode (104) est l'une des deux électrodes
du condensateur et se trouve connectée par le plot (106) à un noeud de stockage à
l'intérieur d'un circuit intégré, et dans lequel un oxyde (112 et/ou 114) s'est formé
entre l'électrode (104) et le plot (106),
comprenant les étapes consistant à :
comprenant les étapes consistant à :
- bombarder l'oxyde par des ions ; et
- mélanger l'oxyde aux matériaux de l'électrode et du plot pour augmenter la conductivité entre l'électrode et le plot.
2. Procédé selon la revendication 1,
dans lequel
l'étape de bombardement comprend l'étape de bombardement par implantation d'ions.
dans lequel
l'étape de bombardement comprend l'étape de bombardement par implantation d'ions.
3. Procédé selon la revendication 1,
dans lequel
l'étape de bombardement comprend l'étape de bombardement de l'oxyde par des ions de germanium.
dans lequel
l'étape de bombardement comprend l'étape de bombardement de l'oxyde par des ions de germanium.
4. Procédé selon la revendication 1,
dans lequel
l'étape de bombardement comprend l'étape de réglage de l'angle des ions incidents pour obtenir un mélange amélioré.
dans lequel
l'étape de bombardement comprend l'étape de réglage de l'angle des ions incidents pour obtenir un mélange amélioré.
5. Procédé selon la revendication 1,
dans lequel
l'étape de bombardement comprend l'étape de réglage de l'énergie et de la dose des ions incidents pour obtenir un mélange amélioré.
dans lequel
l'étape de bombardement comprend l'étape de réglage de l'énergie et de la dose des ions incidents pour obtenir un mélange amélioré.
6. Procédé selon la revendication 1,
dans lequel
l'électrode (104) contient du platine.
dans lequel
l'électrode (104) contient du platine.
7. Procédé selon la revendication 1,
dans lequel
le plot (106) contient du polysilicium.
dans lequel
le plot (106) contient du polysilicium.