(19)
(11) EP 1 429 227 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
25.01.2006 Bulletin 2006/04

(43) Date of publication A2:
16.06.2004 Bulletin 2004/25

(21) Application number: 03257713.2

(22) Date of filing: 09.12.2003
(51) International Patent Classification (IPC): 
G06F 1/00(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
Designated Extension States:
AL LT LV MK

(30) Priority: 13.12.2002 JP 2002362672
17.09.2003 JP 2003323923

(71) Applicant: Renesas Technology Corp.
Tokyo (JP)

(72) Inventor:
  • Okuda, Yuichi C/o Renesas Techn. Corp.
    Chiyoda-ku Tokyo 100-6334 (JP)

(74) Representative: Calderbank, Thomas Roger et al
Mewburn Ellis LLP York House 23 Kingsway
London WC2B 6HP
London WC2B 6HP (GB)

   


(54) Method for preventing tampering of a semiconductor integrated circuit


(57) A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously. Reverse engineering by irradiation with light can be effectively prevented.







Search report