Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache

(19)

(11)

EP 1 555 611 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	25.01.2006 Bulletin 2006/04

(43)	Date of publication A2:
	20.07.2005 Bulletin 2005/29

(21)	Application number: 04253933.8

(22)	Date of filing: 30.06.2004

(51)

International Patent Classification (IPC):

G06F 9/38^(1980.01)

G06F 12/08^(1985.01)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR
	Designated Extension States:
	AL HR LT LV MK

(30)

Priority:

16.01.2004 US 759559

(71)	Applicant: IP-First LLC
	Fremont, CA 94539 (US)

(72)	Inventor:
	Hooker, Rodney E. Austin Texas 78732 (US)

(74)	Representative: O'Connell, David Christopher
	Haseltine Lake & Co. Redcliff Quay 120 Redcliff Street Bristol BS1 6HU Bristol BS1 6HU (GB)

(54)	Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache

(57) A stack cache memory in a microprocessor and apparatus for performing fast speculative pop instructions is disclosed. The stack cache stores cache lines of data implicated by push instructions in a last-in-first-out fashion. An offset is maintained which specifies the location of the newest non-popped push data within the cache line stored in the top entry of the stack cache. The offset is updated when an instruction is encountered that updates the stack pointer register. When a pop instruction requests data, the stack cache speculatively provides data specified by the offset from the top entry to the pop instruction, before determining whether the pop instruction source address matches the address of the data provided. If the source address and the address of the data provided are subsequently determined to mismatch, then an exception is generated to provide the correct data.

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