FIELD OF THE DISCLOSURE
[0001] The present disclosure generally relates to the field of electronic fuses. In particular,
the present disclosure is directed to a method and design structure for providing
optimal field programming of electronic fuses.
BACKGROUND
[0002] Electronic fuses may commonly be found in many integrated circuit designs. One exemplary
electronic fuse is a poly silicon fuse link that is coupled to a voltage line (usually
referred to as FSource) at one end, and to an n-channel field-effect transistor (NFET),
which is usually referred to as a programming FET, at its opposite end. During a fuse
programming operation, a voltage is supplied by the FSource and the programming FET
is turned on for a certain duration of time, which allows controlled electromigration
to occur. The controlled electromigration causes a salicide/boron pile-up on an anode
side of the poly fuse link. As a result, the resistance across the poly fuse link
may rise from hundreds of ohms to many Kilo-ohms, in effect opening or "programming"
the electronic fuse.
[0003] As is known in the art, the rise in fuse resistance during a fuse programming operation
must meet a particular integrated circuit chip characteristic requirement. Using a
"one size fits all" approach to a fuse programming operation may have two undesirable
results: (1) a ruptured fuse or (2) a weakly programmed fuse. As such, if chip characteristics
vary, the fuse programming process may need to be altered in order to provide the
desired fuse yield. That is, the environmental variables of a fuse programming process,
e.g., programming Vdd, FSource voltage, or the fuse programming duration, may need
to be varied on a chip-by-chip basis according to a different characteristic requirement
of each chip. Integrated circuit chip manufacturers have satisfactorily determined
on a chip-by-chip basis whether and how one or more environmental variables need to
be altered. As a result, the proper fuse programming conditions may be applied by
automated test equipment during the normal manufacturing test flow and, thus, the
electronic fuse programming operation is successfully performed.
[0004] While the conditions and parameters that are related to the electronic fuse programming
process, which includes the environmental variables of a fuse programming process,
are known to integrated circuit chip manufacturers, they are not known to customers
that are receiving the chip, as it is not the manufacturer's practice to supply this
information to customers. However, customers may wish to program electronic fuses
in the field for a wide variety of reasons and, thus, customers may benefit from knowledge
of the electronic fuse programming process. For example, upon receiving a chip of
the customer's specifications from the manufacturer, a customer may wish to program
electronic fuses in order to implement functional or performance settings therein.
Unfortunately, without the proper electronic fuse programming information that takes
into account the environmental variables of the customer's chip specifically, programming
electronic fuses in the field (i.e., outside the manufacturing test environment) will
likely result in low fuse yield.
[0005] Integrated circuit chip manufacturers have utilized an electronic chip identification
(ECID) macro of a chip which may be used for storing non-test related data (e.g.,
chip identification data, such as lot number, wafer ID, chip coordinates). Chip customers
may access this chip identification information. However, integrated circuit chip
manufacturers have not provided customers in any fashion the knowledge to extend manufacturing
processes (e.g., effectively program electronic fuses) to the field.
[0006] A need exists for a method of providing optimal field programming of electronic fuses,
in order to enable chip customers to perform an electronic fuse programming process
in the field that produces a desired fuse yield.
SUMMARY OF THE DISCLOSURE
[0007] The invention is defined in claims 1 and 9.
[0008] In one embodiment, a method of programming an electronic fuse of a chip in the field
by a customer of the manufacturer of the chip is provided. The method includes determining
one or more optimal fuse programming conditions for one or more electronic fuses of
a chip; storing an indicator of the one or more optimal fuse programming conditions
in one or more memory bits on the chip; providing the chip to a customer in the field;
and instructing the customer to access the one or more optimal fuse programming conditions
from the one or more memory bits to enable the customer to program at least one of
the one or more electronic fuses.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] For the purpose of illustrating the invention, the drawings show aspects of one or
more embodiments of the invention. However, it should be understood that the present
invention is not limited to the precise arrangements and instrumentalities shown in
the drawings, wherein:
FIG. 1 illustrates a functional block diagram of one example of an integrated circuit
chip, upon which is stored a fuse programming condition identifier for enabling a
method of programming an electronic fuse in the field;
FIG. 2 illustrates a flow diagram of one example of a method of programming an electronic
fuse by use of the fuse programming condition identifier that is stored on the integrated
circuit chip;
FIG. 3 illustrates a flow diagram of one example of a method of determining one or
more optimal fuse programming condition identifiers for enabling a method of programming
an electronic fuse in the field;
FIG. 4 illustrates a flow diagram of one example of a method of programming an electronic
fuse in the field by an integrated circuit chip customer; and
FIG. 5 is a block diagram of a design flow process using the design structure according
to an embodiment.
DETAILED DESCRIPTION
[0010] In one embodiment, the present disclosure includes a method of providing optimal
fuse programming conditions by which an integrated circuit (IC) chip customer may
program electronic fuses in the field, i.e., outside of the manufacturing test environment.
In particular, an optimal fuse programming identifier, which is correlated to a set
of optimal fuse programming conditions, is provided to the customer in readable fashion
on the customer's IC chip. After accessing the optimal fuse programming identifier
on the customer's IC chip, the customer may apply a fuse programming process in the
field according to the correlated optimal fuse programming conditions. In one example,
this may allow the customer to achieve a desired electronic fuse yield.
[0011] FIG. 1 illustrates a functional block diagram of an exemplary IC chip 100, upon which
is stored a fuse programming condition identifier for enabling a method of programming
an electronic fuse in the field. IC chip 100 may be any integrated circuit chip, such
as an application specific integrated circuit (ASIC) device, that includes at least
one arrangement of electronic fuses (eFUSEs). For example, FIG. 1 shows that IC chip
100 includes a first eFUSE bank 110 and a second eFUSE bank 112, which may each be
a single eFUSE or a string of eFUSEs (e.g., forming a certain logic macro within IC
chip 100). The eFUSEs of banks 110 and/or 112 may be initially in an unprogrammed
(i.e., closed) state. In one example, first eFUSE bank 110 and/or eFUSE bank 112 may
be eFUSEs that form certain redundancy structures, such as structures commonly found
in memory arrays (i.e., redundant wordlines or redundant columns). In this example,
the eFUSEs may be programmed to disconnect a normal wordline and replace it with a
redundant wordline when, for example, the normal wordline is detected as defective.
In another example, first eFUSE bank 110 and/or second eFUSE bank 112 may be eFUSEs
that form an ECID macro, which contains eFUSEs that are programmed to a value that
reflects, for example, chip identification data.
[0012] Additionally, FIG. 1 shows a detail of an exemplary eFUSE 114 of first eFUSE bank
110. More specifically, eFUSE 114 may be a poly silicon fuse link that is coupled
to a voltage line (FSource) at one end, and to an NFET, which is referred to as a
programming FET 116, at its opposite end. The gate of programming FET 116 is controlled
by the chip voltage (Vdd) of IC chip 100. During an eFUSE programming operation, a
voltage is supplied by the FSource and programming FET 116 is turned on for a certain
duration of time by applying Vdd, which allows controlled electromigration to occur.
The controlled electromigration may cause a salicide/boron pile-up on an anode side
of the eFUSE 114. As a result, the resistance across eFUSE 114 may rise (e.g., from
hundreds of ohms to many Kilo-ohms), in effect opening (i.e., programming) eFUSE 114.
[0013] Referring again to FIG. 1, IC chip 100 further includes a storage device 118, within
which is stored a digital value that is related to one or more fuse programming condition
identifiers 120. Storage device 118 may be any mechanism by which one or more bits
of digital data may be stored, such as, but not limited to, a memory device or one
or more eFUSEs. In one example, storage device 118 may be a non-volatile static random
access memory (SRAM) device or a non-volatile programmable read-only memory (PROM)
device. In another example, storage device 118 may be one or more surplus eFUSEs within
a bank of existing eFUSEs within IC chip 100, such as, but not limited to, surplus
eFUSEs 114 within first eFUSE bank 110 or second eFUSE bank 112. In yet another example,
storage device 118 may be, or may be part of, one or more eFUSEs of an ECID. One or
more fuse programming condition identifiers may be represented by one or more logical
values stored in a storage device, such as storage device 118. For example, a programmed
or unprogrammed state of an eFUSE 114 may represent a logic one (1) or zero (0), e.g.,
unprogrammed eFUSE=1, programmed eFUSE=0, or visa versa.
[0014] Those skilled in the art will recognize that an integrated circuit device, which
is represented by IC chip 100, may include arrangements of one or more logic functions,
which for simplicity are not shown in FIG. 1.
[0015] The conditions of an eFUSE programming process may be controlled precisely on a chip-by-chip
basis during the manufacturing test operation in order to achieve a high eFUSE yield,
by avoiding ruptured eFUSEs or weakly programmed eFUSEs. The optimal eFUSE programming
conditions are variable on a chip-by-chip basis due to manufacturing process variations,
e.g., from one IC chip 100 to a next IC chip 100, to a next IC chip 100, and so on.
One exemplary method of determining the optimal eFUSE programming conditions is described
in
US Patent No 7,170,299 "Electronic fuse blow mimic and methods for adjusting electronic fuse blow," which
is incorporated herein by reference in its entirety. The '299 patent describes a system,
method, and program product for adjusting an environmental variable of a fuse programming
of an electronic fuse. In particular, a mimic NFET may be coupled to a fuse programming
source voltage line, a fuse programming gate voltage line, and a chip ground in the
same manner as the electronic fuse, except that the mimic NFET is not attached to
an electronic fuse. The on-current (I-ON) and off-current (I-OFF) of the mimic NFET
are measured to determine a fuse programming current (1-PROGRAM) of the electronic
fuse. The environmental variable is adjusted based on the determined programming current.
Another example of a method is summarized with reference to a method 300 of FIG. 3
below.
[0016] Example environmental variables include, but are not limited to, FSource, Vdd, background
leakage current, I-PROGRAM, chip vs. tester ground offset, programming duration, temperature,
and accuracy of test equipment. Fuse programming condition identifier 120 may be a
digital code of one or more bits that may be correlated to a certain eFUSE programming
condition, which may be a unique optimal eFUSE programming condition for a given IC
chip 100. For example, fuse programming condition identifier 120 may be uniquely encoded
with a first value on a first IC chip 100 for correlating to a first optimal eFUSE
programming condition therefor, uniquely encoded with a next unique value on a next
IC chip 100 for correlating to a next optimal eFUSE programming condition therefor,
and uniquely encoded with a next unique value on a next IC chip 100 for correlating
to a next optimal eFUSE programming condition therefor. The code contained in fuse
programming condition identifier 120 may correlate to one or any combination of multiple
environmental variables, which include, for example, FSource, Vdd, background leakage
current, I-PROGRAM, chip vs. tester ground offset, programming duration, temperature,
and accuracy of test equipment.
[0017] The number of bits that form fuse programming condition identifier 120 is dependent
on the number of or combinations of environmental variables needed to convey the optimal
eFUSE programming conditions for a given IC chip. In one example, fuse programming
condition identifier 120 may be a 1-bit code that correlates to a first and second
optimal Vdd value, e.g., fuse programming condition identifier 120=0 for Vdd=1.20
volts and fuse programming condition identifier 120=1 for Vdd=1.35 volts. In another
example, fuse programming condition identifier 120 may be a 2-bit code that correlates
to up to four optimal Vdd values, e.g., fuse programming condition identifier 120=00
for Vdd=1.20 volts, fuse programming condition identifier 120=01 for Vdd=1.35 volts,
and fuse programming condition identifier 120=10 for Vdd=1.50 volts. In yet another
example, fuse programming condition identifier 120 may be an n-bit binary code that
correlates to the actual digital value (having a certain resolution) of a certain
eFUSE programming condition, e.g., an 8-bit, 10-bit, 12-bit, or 16-bit binary word
that represents the actual value of, for example, FSource, Vdd, or 1-PROGRAM. In all
cases, the information of fuse programming condition identifier 120 may be stored
by the chip manufacturer during the normal manufacturing test flow. In the case wherein
the bits forming fuse programming condition identifier 120 are memory bits, these
bits are set to a desired state via known memory write operations. Alternatively,
in the case wherein the bits forming fuse programming condition identifier 120 are
eFUSEs 114, one or more eFUSEs 114 are set to either a programmed or unprogrammed
state according to a desired code.
[0018] As exemplified by IC chip 100 of FIG. 1, the chip manufacturer may provide a fuse
programming condition identifier, such as fuse programming condition identifier 120,
within a chip and, thereby, provides a readable mechanism that is accessible by a
customer and by which a customer may then correlate an optimal eFUSE programming condition
for his/her chip. Correlation may occur in a variety of ways. In one example, a correlation
may include comparison of a fuse programming condition identifier with a digitally
stored value (e.g., in a lookup data table). In another example, a correlation may
include comparison of a fuse programming condition identifier with a printed manual.
In yet another example, a correlation may include reading the fuse programming condition
identifier to reveal an actual programming condition. As a result, the fuse programming
condition identifier may enable a customer to apply an optimal eFUSE programming condition,
which is unique to a particular chip, in order to efficiently program eFUSEs in the
field, i.e., outside of the manufacturing test environment, such as during the customer's
card level test operation. More details are provided with reference to FIGS. 2, 3,
and 4.
[0019] FIG. 2 illustrates a flow diagram of one embodiment of a method 200 of programming
an electronic fuse by use of a fuse programming condition identifier, such as fuse
programming condition identifier 120, which is stored on an integrated circuit chip,
such as IC chip 100. Method 200 includes, but is not limited to, the following steps.
[0020] At step 210, a fuse programming condition identifier that is stored in one or more
memory bits on a chip are accessed. In one example and referring again to FIG. 1,
after delivering a chip, such as IC chip 100, from the chip manufacturer to the chip
purchaser, fuse programming condition identifier 120 of storage device 118 is accessed
by the chip purchaser. In the case wherein the bits forming fuse programming condition
identifier 120 are memory bits, these bits are accessed via known memory read operations.
Alternatively, in the case wherein the bits forming fuse programming condition identifier
120 are eFUSEs 114, the programmed or unprogrammed state of the one or more eFUSEs
114 is detected via standard circuitry that is associated with, for example, first
eFUSE bank 110 or second eFUSE bank 112.
[0021] At step 212, one or more optimal eFUSE programming conditions are correlated with
the information of fuse programming condition identifier, such as correlated with
the information of fuse programming condition identifier 120 of storage device 118
of IC chip 100. In one example, this correlation may be performed by the chip manufacturer
providing the chip purchaser any standard method of correlating each possible value
that may be encoded in fuse programming condition identifier 120 with an optimal eFUSE
programming condition e.g., a software lookup table, an electronic or printed guidebook,
or a telephone customer service center. In one example, a 1-bit fuse programming condition
identifier 120 that is set to "0" may correlate to, for example, set Vdd=1.20 volts
and that is set to "1" may correlate to, for example, set Vdd=1.35 volts. In another
example, a 2-bit fuse programming condition identifier 120 that is set to "00" may
correlate to, for example, set Vdd=1.20 volts; that is set to "01" may correlate to,
for example, set Vdd=1.35 volts; and that is set to "10" may correlate to, for example,
set Vdd=1.50 volts.
[0022] At step 214, one or more fuses on the IC chip are programmed utilizing the one or
more correlated eFUSE programming conditions. In particular, the IC chip purchaser
applies the correlated optimal eFUSE programming conditions that were extracted from
his/her IC chip during, for example, manufacturing wafer and/or module test operations,
in order to program one or more IC chip purchaser-selected eFUSEs 114.
[0023] FIG. 3 illustrates a flow diagram of one embodiment of a method 300 of determining
one or more optimal fuse programming condition identifiers for enabling a method of
programming an electronic fuse, such as programming an electronic fuse by use of method
300. In one example, one or more optimal fuse programming condition identifiers may
be determined by use of method 300 on a chip-by-chip basis during a manufacturing
test operation. Method 300 includes, but is not limited to, the following steps.
[0024] At step 310, a plurality of IC test chips are tested for the optimal chip programming
conditions. In particular, a chip manufacturer executes an eFUSE programming process
on a plurality (e.g., hundreds to millions) of IC test chips, in order to understand
the preferred way to program the eFUSEs for a selection of environmental variations.
[0025] At step 312, a plurality of test values of a correlating parameter are determined
from the plurality of IC test chips. A correlating parameter may be any measurable
value that may indicate a corresponding value for a fuse programming environmental
condition. For example, a fuse programming current may be measured at a particular
fuse programming condition value, e.g., a particular Vdd value. Each of the plurality
of test values may be for one of a plurality of fuse programming condition sets. The
test values are based upon the eFUSE-programming information that is gathered in step
310 for every known process variation. For example, physical measurements of an IC
test chip may be mapped to certain eFUSE-programming parameters.
[0026] At step 314, each IC test chip is tested for an actual value of the correlating parameter.
In one example and referring to paragraphs 0018 through 0020 of the co-pending ' 120
patent application, the background leakage current (I-BKG) of the IC chip under test
is measured, the on-current (I-ON) of a mimic programming FET at nominal Vdd and FSource
values is measured, I-BKG is subtracted from I-ON in order to determine the fuse programming
current (I-PROGRAM).
[0027] At step 316, an optimal one of the plurality of fuse programming condition sets is
determined for the IC chip under test by comparing an actual value to a plurality
of test values. In one example and referring to paragraph 0021 of the co-pending '
120 patent application, a three-way decision may be performed. Specifically, an upper
level threshold, for example, 14mA, and a lower level threshold, for example, 10mA,
are set for the determined I-PROGRAM. If the determined I-PROGRAM is higher than the
upper level threshold, here 14mA, the programming Vdd may be decreased, for example,
from the preset 1.35V to 1.20V. If the determined I-PROGRAM is lower than the lower
level threshold, here 10mA, the programming Vdd may be increased, for example, from
the preset 1.35V to 1.50V. Also, if the determined I-PROGRAM is within the range between
the upper level threshold, here 14mA, and the lower level threshold, here 10mA, the
programming Vdd may be considered proper and be maintained the same as the preset
value, here 1.35V. In doing so, an optimal value of the programming Vdd is determined
that correlates to the actual I-PROGRAM of the IC chip under test.
[0028] At step 318, an indicator of the optimal one of the plurality of fuse programming
condition sets is stored as the fuse programming condition identifier. For example,
if the optimal programming Vdd is 1.20V, a 2-bit fuse programming condition identifier
120 for the IC chip under test may be set to "00;" if the optimal programming Vdd
is 1.35V, the 2-bit fuse programming condition identifier 120 may be set to "01;"
and if the optimal programming Vdd is 1.50V, the 2-bit fuse programming condition
identifier 120 may be set to "10."
[0029] FIG. 4 illustrates a flow diagram of a method 400 of programming an electronic fuse
in the field by, for example, an integrated circuit chip customer. Method 400 includes,
but is not limited to, the following steps.
[0030] At step 410, one or more optimal fuse programming conditions are determined. These
conditions will apply to all eFUSEs on a given chip such as IC chip 100 by, for example,
performing steps 310 through 316 of method 300 of FIG. 3.
[0031] At step 412, during the manufacturing test operation, an indicator of the one or
more optimal fuse programming conditions is stored in one or more memory bits on the
IC chip under test. For example, an indicator of the one or more optimal fuse programming
conditions is stored in fuse programming condition identifier 120 of storage device
118 of IC chip 100, as described, for example, in FIG. 1 and in step 318 of method
300 of FIG. 3.
[0032] At step 414, the chip manufacturer provides an IC chip, such as IC chip 100, to a
customer in the field.
[0033] At step 416, the IC chip customer is instructed on how to access the one or more
optimal fuse programming conditions from the one or more memory bits in order to enable
the customer to program at least one of the one or more eFUSEs. For example, the IC
chip manufacturer may provide instructions to the IC chip customer on how to access,
for example, fuse programming condition identifier 120 of storage device 118 of IC
chip 100. Additionally, the IC chip manufacturer may provide the chip purchaser a
standard method of correlating each possible value that may be encoded in fuse programming
condition identifier 120 with a respective optimal eFUSE programming condition. Standard
correlation methods include, but are not limited to, a software lookup table, an electronic
or printed guidebook, or calling by telephone a customer service center.
[0034] FIG. 5 shows a block diagram of an example design flow 500. Design flow 500 may vary
depending on the type of IC being designed. For example, a design flow 500 for building
an application specific IC (ASIC) may differ from a design flow 500 for designing
a standard component. Design structure 520 is preferably an input to a design process
510 and may come from an IP provider, a core developer, or other design company or
may be generated by the operator of the design flow, or from other sources. Design
structure 520 comprises IC chip 100 in the form of schematics or HDL, a hardware-description
language (e.g., Verilog, VHDL, C, etc.). Design structure 520 may be contained on
one or more machine readable medium. For example, design structure 520 may be a text
file or a graphical representation of IC chip 100. Design process 510 preferably synthesizes
(or translates) IC chip 100 into a netlist 580, where netlist 580 is, for example,
a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that
describes the connections to other elements and circuits in an integrated circuit
design and recorded on at least one of machine readable medium. This may be an iterative
process in which netlist 580 is resynthesized one or more times depending on design
specifications and parameters for the circuit.
[0035] Design process 510 may include using a variety of inputs; for example, inputs from
library elements 530 which may house a set of commonly used elements, circuits, and
devices, including models, layouts, and symbolic representations, for a given manufacturing
technology (e.g., different technology nodes, 32nm, 45 nm, 90 nm, etc.), design specifications
540, characterization data 550, verification data 560, design rules 570, and test
data files 585 (which may include test patterns and other testing information). Design
process 510 may further include, for example, standard circuit design processes such
as timing analysis, verification, design rule checking, place and route operations,
etc. One of ordinary skill in the art of integrated circuit design can appreciate
the extent of possible electronic design automation tools and applications used in
design process 510 without deviating from the scope and spirit of the invention. The
design structure of the invention is not limited to any specific design flow.
[0036] Ultimately, design process 510 preferably translates IC chip 100, along with the
rest of the integrated circuit design (if applicable), into a final design structure
590 (e.g., information stored in a GDS storage medium). Final design structure 590
may comprise information such as, for example, test data files, design content files,
manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test
data, data for routing through the manufacturing line, and any other data required
by a semiconductor manufacturer to produce IC chip 100. Final design structure 590
may then proceed to a stage 595 where, for example, final design structure 590: proceeds
to tape-out, is released to manufacturing, is sent to another design house or is sent
back to the customer.
[0037] Exemplary embodiments have been disclosed above and illustrated in the accompanying
drawings. It will be understood by those skilled in the art that various changes,
omissions and additions may be made to that which is specifically disclosed herein
without departing from the present invention.
1. A method (300) of programming an electronic fuse of a chip (100) in the field by a
customer of the manufacturer of the chip, the method
characterised by comprising:
determining (316, 410) one or more optimal fuse programming conditions for one or
more electronic fuses of a chip;
storing (318, 412) an indicator of said one or more optimal fuse programming conditions
in one or more memory bits on said chip;
providing (414) said chip to a customer in the field; and
instructing (416) said customer to access said one or more optimal fuse programming
conditions from said one or more memory bits to enable said customer to program at
least one of said one or more electronic fuses.
2. A method according to claim 1, wherein said one or more memory bits are included in
an electronic chip identification macro.
3. A method according to claim 1 or 2, wherein said one or more memory bits includes
an electronic fuse.
4. A method according to any preceding claim, wherein said one or more optimal fuse programming
conditions is determined on a chip-by-chip basis during manufacture testing of said
chip.
5. A method according to claim 4, wherein said determining of said one or more optimal
fuse programming conditions includes:
testing a plurality of test chips for one or more optimal chip programming conditions;
determining a plurality of test values of a correlating parameter from said plurality
of test chips, each of said plurality of test values being for one of a plurality
of fuse programming condition sets;
testing said chip for an actual value of said correlating parameter;
determining an optimal one of said plurality of fuse programming condition sets for
said chip by comparing said actual value to said plurality of test values;
storing an indicator of said optimal one of said plurality of fuse programming condition
sets as said fuse programming condition identifier.
6. A method according to claim 5, wherein said correlating parameter is a fuse programming
current for said chip.
7. A method according to claim 6, wherein said fuse programming current is determined
by:
measuring a background current on a fuse programming source line of an electronic
fuse of said chip;
measuring an 'on' current on said fuse programming source line at a predetermined
value of a chip programming parameter without exposing said electronic fuse to said
'on' current; and
determining a difference between said 'on' current and said background current.
8. A method according to any preceding claim, wherein said one or more optimal fuse programming
conditions includes a condition selected from the group consisting of a fuse programming
source voltage, a fuse programming gate voltage, a fuse programming time, and any
combinations thereof.
9. A design structure for programming an electronic fuse of a chip, the design structure
characterised by comprising:
a means for determining (316, 410) one or more optimal fuse programming conditions
for one or more electronic fuses of a chip;
a means for storing (318, 412) an indicator of said one or more optimal fuse programming
conditions in one or more memory bits on said chip;
a means for providing (414) said chip to a customer in the field; and
a means for instructing (416) said customer to access said one or more optimal fuse
programming conditions from said one or more memory bits to enable said customer to
program at least one of said one or more electronic fuses.
10. A design structure according to claim 9, , wherein said one or more memory bits are
included in an electronic chip identification macro.
11. A design structure according to claim 9 or 10, wherein said one or more memory bits
includes an electronic fuse.
12. A design structure according to claim 9, 10 or 11, wherein said means for determining
of said one or more optimal fuse programming conditions is conducted on a chip-by-chip
basis during manufacture testing of said chip.
13. A design structure according to any of claims 9 to 12, wherein said means for determining
of said one or more optimal fuse programming conditions includes:
a means for testing a plurality of test chips for optimal chip programming conditions;
a means for determining a plurality of test values of a correlating parameter from
said plurality of test chips, each of said plurality of test values being for one
of a plurality of fuse programming condition sets;
a means for testing said chip for an actual value of said correlating parameter;
a means for determining an optimal one of said plurality of fuse programming condition
sets for said chip by comparing said actual value to said plurality of test values;
and
a means for storing an indicator of said optimal one of said plurality of fuse programming
condition sets as said fuse programming condition identifier.
14. A design structure according to claim 13, wherein said correlating parameter is a
fuse programming current for said chip.
15. A design structure according to claim 14, wherein said fuse programming current is
determined by:
measuring a background current on a fuse programming source line of an electronic
fuse of said chip;
measuring an 'on' current on said fuse programming source line at a predetermined
value of a chip programming parameter without exposing said electronic fuse to said
'on' current; and
determining a difference between said 'on' current and said background current.
1. Verfahren (300) zum Programmieren einer elektronischen Sicherung eines Chips (100)
am Einsatzort durch einen Kunden des Chipherstellers, wobei das Verfahren
dadurch gekennzeichnet ist, dass es Folgendes umfasst:
Festlegen (316, 410) eines oder mehrerer optimaler Sicherungsprogrammierbedingungen
für eine oder mehrere elektronische Sicherungen eines Chips;
Speichern (318, 412) eines Hinweismerkers der einen oder mehreren optimalen Sicherungsprogrammierbedingungen
in einem oder mehreren Speicherbits auf dem Chip;
Liefern (414) des Chips an einen Kunden am Einsatzort; und
Anleiten (416) des Kunden, wie auf die eine oder die mehreren optimalen Sicherungsprogrammierbedingungen
von dem einen oder den mehreren Speicherbits zugegriffen werden kann, um den Kunden
zu befähigen, von der einen oder den mehreren elektronischen Sicherungen wenigstens
eine zu programmieren.
2. Verfahren nach Anspruch 1, wobei das eine oder die mehreren Speicherbits in einem
elektronischen Chipidentifizierungsmakro enthalten sind.
3. Verfahren nach Anspruch 1 oder 2, wobei das eine oder die mehreren Speicherbits eine
elektronische Sicherung enthalten.
4. Verfahren nach einem beliebigen vorhergehenden Anspruch, wobei die eine oder die mehreren
optimalen Sicherungsprogrammierbedingungen für jeden einzelnen Chip während der Fertigungsprüfung
des Chips festgelegt werden.
5. Verfahren nach Anspruch 4, wobei das Festlegen der einen oder der mehreren optimalen
Sicherungsprogrammierbedingungen Folgendes beinhaltet:
Prüfen einer Vielzahl von Prüfchips nach einer oder mehreren optimalen Sicherungsprogrammierbedingungen;
Bestimmen einer Vielzahl von Prüfwerten eines korrelierenden Parameters aus der Vielzahl
von Prüfchips, wobei jeder aus der Vielzahl von Prüfwerten für eine Gruppe aus einer
Vielzahl von Gruppen der Sicherungsprogrammierbedingungen gilt;
Prüfen des Chips nach einem tatsächlichen Wert des korrelierenden Parameters;
Festlegen einer optimalen Gruppe aus der Vielzahl von Gruppen der Sicherungsprogrammierbedingungen
für den Chip durch Vergleichen des tatsächlichen Werts mit der Vielzahl von Prüfwerten;
Speichern eines Hinweismerkers der optimalen Gruppe aus der Vielzahl von Gruppen der
Sicherungsprogrammierbedingungen als die Kennung der Sicherungsprogrammierbedingungen.
6. Verfahren nach Anspruch 5, wobei es sich bei dem korrelierenden Parameter um einen
Sicherungsprogrammierstrom für den Chip handelt.
7. Verfahren nach Anspruch 6, wobei der Sicherungsprogrammierstrom durch Folgendes festgelegt
ist:
Messen eines Hintergrundstroms in einer Leitung der Sicherungsprogrammierquelle einer
elektronischen Sicherung des Chips;
Messen eines "Ein"-Stroms in der Leitung der Sicherungsprogrammierquelle bei einem
zuvor festgelegten Wert eines Chip-Programmierparameters, ohne dass die elektronische
Sicherung dem "Ein"-Strom ausgesetzt wird; und
Bestimmen einer Differenz zwischen dem "Ein"-Strom und dem Hintergrundstrom.
8. Verfahren nach einem vorhergehenden Anspruch, wobei eine oder mehrere optimale Sicherungsprogrammierbedingungen
eine Bedingung enthalten, die aus der Gruppe ausgewählt ist, die eine Sicherungsprogrammiersourcespannung,
eine Sicherungsprogrammier-Gatespannung, einen Sicherungsprogrammierzeitpunkt und
beliebige Kombinationen hiervon enthält.
9. Gestaltungsstruktur (design structure) zum Programmieren einer elektronischen Sicherung
eines Chips, wobei die Gestaltungsstruktur
dadurch gekennzeichnet ist, dass sie Folgendes umfasst:
Mittel zum Festlegen (316, 410) einer oder mehrerer optimaler Sicherungsprogrammierbedingungen
für eine oder mehrere elektronische Sicherungen eines Chips;
Mittel zum Speichern (318, 412) eines Hinweismerkers einer oder mehrerer optimaler
Sicherungsprogrammierbedingungen in einem oder mehreren Speicherbits auf dem Chip;
ein Mittel zum Liefern (414) des Chips an einen Kunden am Einsatzort; und
ein Mittel zum Anleiten (416) des Kunden, wie auf eine oder mehrere Sicherungsprogrammierbedingungen
aus dem einen oder den mehreren Speicherbits zugegriffen werden kann, um den Kunden
zu befähigen, von der einen oder den mehreren elektronischen Sicherungen wenigstens
eine zu programmieren.
10. Gestaltungsstruktur nach Anspruch 9, wobei das eine oder die mehreren Speicherbits
in einem elektronischen Chipidentifizierungsmakro enthalten sind.
11. Gestaltungsstruktur nach Anspruch 9 oder 10, wobei das eine oder die mehreren Speicherbits
eine elektronische Sicherung enthalten.
12. Gestaltungsstruktur nach Anspruch 9, 10 oder 11, wobei die Mittel zum Festlegen der
einen oder mehreren optimalen Sicherungsprogrammierbedingungen für jeden einzelnen
Chip während der Fertigungsprüfung des Chips zum Einsatz kommen.
13. Gestaltungsstruktur nach einem der Ansprüche 9 bis 12, wobei die Mittel zum Festlegen
einer oder mehrerer optimaler Sicherungsprogrammierbedingungen Folgendes enthalten:
Mittel zum Prüfen einer Vielzahl von Prüfchips nach optimalen Chip-Programmierbedingungen;
Mittel zum Festlegen einer Vielzahl von Prüfwerten eines korrelierenden Parameters
aus der Vielzahl von Prüfchips, wobei jeder Prüfwert aus der Vielzahl von Prüfwerten
für eine Gruppe aus einer Vielzahl von Gruppen von Sicherungsprogrammierbedingungen
gilt;
Mittel zum Prüfen des Chips nach einem tatsächlichen Wert des korrelierenden Parameters;
Mittel zum Festlegen einer optimalen Gruppe aus der Vielzahl von Gruppen aus Sicherungsprogrammierbedingungen
für den Chip durch Vergleichen des tatsächlichen Werts mit der Vielzahl von Prüfwerten;
und
Mittel zum Speichern eines Hinweismerkers der optimalen Gruppe aus der Vielzahl von
Gruppe aus Sicherungsprogrammierbedingungen als Kennung der Sicherungsprogrammierbedingung.
14. Gestaltungsstruktur nach Anspruch 13, wobei es sich bei dem korrelierenden Parameter
um ein Sicherungsprogrammierstrom für den Chip handelt.
15. Gestaltungsstruktur nach Anspruch 14, wobei der Sicherungsprogrammierstrom durch Folgendes
festgelegt wird:
Messen eines Hintergrundstroms in einer Sicherungsprogrammier-Sourceleitung einer
elektronischen Sicherung des Chips;
Messen eines "Ein"-Stroms auf der Sicherungsprogrammier-Sourceleitung bei einem zuvor
festgelegten Wert eines Chip-Programmierparameters, ohne dass die elektronische Sicherung
dem "Ein"-Strom ausgesetzt wird; und
Bestimmen einer Differenz zwischen dem "Ein"-Strom und dem Hintergrundstrom.
1. Procédé (300) de programmation d'un fusible électronique d'une puce (100) sur le terrain
par un client du fabricant de la puce, le procédé étant
caractérisé par le fait de comprendre les étapes consistant à :
déterminer (316, 410) une ou plusieurs conditions de programmation de fusibles optimales
pour un ou plusieurs fusibles électroniques d'une puce,
mémoriser (318, 412) un indicateur desdites une ou plusieurs conditions de programmation
de fusibles optimales dans un ou plusieurs bits de mémoire sur ladite puce,
fournir (414) ladite puce à un client sur le terrain, et
donner pour instruction (416) audit client d'accéder auxdites une ou plusieurs conditions
de programmation de fusibles optimales à partir desdits un ou plusieurs bits de mémoire
pour permettre audit client de programmer au moins l'un desdits un ou plusieurs fusibles
électroniques.
2. Procédé selon la revendication 1, dans lequel lesdits un ou plusieurs bits de mémoire
sont inclus dans une macro d'identification de puce électronique.
3. Procédé selon la revendication 1 ou 2, dans lequel lesdits un ou plusieurs bits de
mémoire comprennent un fusible électronique.
4. Procédé selon l'une quelconque des revendications précédentes, dans lequel lesdites
une ou plusieurs conditions de programmation de fusibles optimales sont déterminées
sur une base puce par puce au cours d'un essai de fabrication de ladite puce.
5. Procédé selon la revendication 4, dans lequel ladite détermination desdites une ou
plusieurs conditions de programmation de fusibles optimales comprend les étapes consistant
à :
tester une pluralité de puces d'essai en ce qui concerne une ou plusieurs conditions
de programmation de fusibles optimales,
déterminer une pluralité de valeurs d'essai d'un paramètre de corrélation à partir
de ladite pluralité de puces d'essai, chaque valeur de ladite pluralité de valeurs
d'essai correspondant à un ensemble d'une pluralité d'ensembles de conditions de programmation
de fusibles,
tester ladite puce en ce qui concerne une valeur actuelle dudit paramètre de corrélation,
déterminer un ensemble optimal de ladite pluralité d'ensembles de conditions de programmation
de fusibles pour ladite puce en comparant ladite valeur actuelle à ladite pluralité
de valeurs d'essai,
mémoriser un indicateur dudit ensemble optimal de ladite pluralité d'ensembles de
conditions de programmation de fusibles comme ledit identificateur de conditions de
programmation de fusibles.
6. Procédé selon la revendication 5, dans lequel ledit paramètre de corrélation est un
courant de programmation de fusible pour ladite puce.
7. Procédé selon la revendication 6, dans lequel ledit courant de programmation de fusible
est déterminé en :
mesurant un courant de fond sur une ligne de source de programmation de fusible d'un
fusible électronique de ladite puce,
mesurant un courant « actif » sur ladite ligne de source de programmation de fusible
à une valeur prédéterminée d'un paramètre de programmation de puce sans exposer ledit
fusible électronique audit courant « actif », et
déterminant une différence entre ledit courant « actif » et ledit courant de fond.
8. Procédé selon l'une quelconque des revendications précédentes, dans lequel lesdites
une ou plusieurs conditions de programmation de fusibles optimales comprennent une
condition sélectionnée à partir du groupe constitué d'une tension de source de programmation
de fusible, d'une tension de grille de programmation de fusible, d'un temps de programmation
de fusible, et toute combinaison de ceux-ci.
9. Structure de conception destinée à programmer un fusible électronique d'une puce,
la structure de conception étant
caractérisée par le fait de comprendre :
un moyen destiné à déterminer (316, 410) une ou plusieurs conditions de programmation
de fusibles optimales pour un ou plusieurs fusibles électroniques d'une puce,
un moyen destiné à mémoriser (318, 412) un indicateur desdites une ou plusieurs conditions
de programmation de fusibles optimales dans un ou plusieurs bits de mémoire sur ladite
puce,
un moyen destiné à fournir (414) ladite puce à un client sur le terrain, et
un moyen destiné à donner pour instruction (416) audit client d'accéder auxdites une
ou plusieurs conditions de programmation de fusibles optimales à partir desdits un
ou plusieurs bits de mémoire pour permettre audit client de programmer au moins l'un
desdits un ou plusieurs fusibles électroniques.
10. Structure de conception selon la revendication 9, dans laquelle lesdits un ou plusieurs
bits de mémoire sont inclus dans une macro d'identification de puce électronique.
11. Structure de conception selon la revendication 9 ou 10, dans laquelle lesdits un ou
plusieurs bits de mémoire comprennent un fusible électronique.
12. Structure de conception selon la revendication 9, 10 ou 11, dans laquelle ledit moyen
de détermination desdites une ou plusieurs conditions de programmation de fusibles
optimales est commandé sur une base puce par puce au cours d'un essai de fabrication
de ladite puce.
13. Structure de conception selon l'une quelconque des revendications 9 à 12, dans laquelle
ledit moyen de détermination desdites une ou plusieurs conditions de programmation
de fusibles optimales comprend :
un moyen destiné à tester une pluralité de puces d'essai en ce qui concerne une ou
plusieurs conditions de programmation de fusibles optimales,
un moyen destiné à déterminer une pluralité de valeurs d'essai d'un paramètre de corrélation
à partir de ladite pluralité de puces d'essai, chaque valeur de ladite pluralité de
valeurs d'essai correspondant à un ensemble d'une pluralité d'ensembles de conditions
de programmation de fusibles,
un moyen destiné à tester ladite puce en ce qui concerne une valeur actuelle dudit
paramètre de corrélation,
un moyen destiné à déterminer un ensemble optimal de ladite pluralité d'ensembles
de conditions de programmation de fusibles pour ladite puce en comparant ladite valeur
actuelle à ladite pluralité de valeurs d'essai, et
un moyen destiné à mémoriser un indicateur dudit ensemble optimal de ladite pluralité
d'ensembles de conditions de programmation de fusibles comme ledit identificateur
de conditions de programmation de fusibles.
14. Structure de conception selon la revendication 13, dans laquelle ledit paramètre de
corrélation est un courant de programmation de fusible pour ladite puce.
15. Structure de conception selon la revendication 14, dans laquelle ledit courant de
programmation de fusible est déterminé en :
mesurant un courant de fond sur une ligne de source de programmation de fusible d'un
fusible électronique de ladite puce,
mesurant un courant « actif » sur ladite ligne de source de programmation de fusible
à une valeur prédéterminée d'un paramètre de programmation de puce sans exposer ledit
fusible électronique audit courant « actif », et
déterminant une différence entre ledit courant « actif » et ledit courant de fond.