(19)
(11) EP 2 408 280 B1

(12) EUROPEAN PATENT SPECIFICATION

(45) Mention of the grant of the patent:
20.11.2013 Bulletin 2013/47

(21) Application number: 11002112.8

(22) Date of filing: 14.03.2011
(51) International Patent Classification (IPC): 
H05K 1/02(2006.01)

(54)

Electronic device having a circuit board with co-layout design of multiple connector placement sites and related circuit board

Elektronische Vorrichtung mit Leiterplatte mit gleichem Aufbau mehrfacher Platzierungsstellen von Anschlüssen und zugehörige Leiterplatte

Dispositif électronique doté d'un circuit imprimé avec un design commun de sites de positionnement de connecteur multiple et circuit imprimé correspondant


(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 16.07.2010 US 364926 P
07.03.2011 US 201113041442

(43) Date of publication of application:
18.01.2012 Bulletin 2012/03

(73) Proprietor: MediaTek Inc.
Hsin-Chu (TW)

(72) Inventors:
  • Feng, Huai-Yuan
    Zhubei City Hsinchu County (TW)
  • Pan, Ching-Gu
    Hsinchu City (TW)
  • Luo, Yan-Bin
    Songshan District Taipei City (TW)
  • Wu, Hua
    Jhubei City Hsinchu County (TW)
  • Lin, Shang-Yi
    Jhubei City Hsinchu County (TW)

(74) Representative: Görz, Ingo 
Hoefer & Partner Patentanwälte Pilgersheimer Strasse 20
81543 München
81543 München (DE)


(56) References cited: : 
US-A1- 2006 158 864
US-A1- 2010 012 365
US-A1- 2008 059 685
   
       
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present invention relates to an electronic device having a circuit board with a co-layout design of multiple connector placement sites according to the pre-characterizing clauses of claims 1 and 9.

    [0002] In a conventional video processing system, certain functional blocks are implemented in different chips. For example, a scaler is integrated in one chip, and a timing controller (T-CON) is integrated in another chip. Therefore, the output interfaces (i.e., connectors) of the scaler and the timing controller are also separate, which increases the production cost inevitably.

    [0003] Recently, integrating the scaler and the timing controller into a single chip is getting more and more popular. Therefore, there is a need for an innovation layout design of the circuit board which carries the single chip with the scaler and the timing controller both integrated therein.

    [0004] US 2008/059685 A1 (HSU SHOU-KUO [TW] ET AL) 6 March 2008 (2008-03-06) discloses a motherboard including a chipset, a first connector pad suitable for receiving a first type of PCI connector (e.g., a PCI-expressx8 connector), a second connector pad suitable for receiving a second type of PCI connector (e.g., a PCI-expressx4 connector), a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of areas for mounting switches. US 2006/158864 A1 (GAY RAPHAEL [US]) 20 July 2006 (2006-07-20) discloses a circuit board including at least one slot which has a first electrical connection adapted to couple to an add-in card of a first type (e.g., PCI) and a second electrical connection adapted to couple to an add-in card of a second type (e.g., PCI-Express). US 2010/012365 A1 (HSIEH PO-CHUAN [TW] ET AL) 21 January 2010 (2010-01-21) discloses a printed circuit board including first and second connector pads, first and second connection components, and first, second, and third transmission lines, where the printed circuit board supports different types of connectors by setting the first and second connection components.

    [0005] This in mind, the present invention aims at providing an electronic device having a circuit board with a co-layout design of multiple connector placement sites to solve the above-mentioned problem.

    [0006] This is achieved by electronic devices according to claims 1 and 9. The dependent claims pertain to corresponding further developments and improvements.

    [0007] As will be seen more clearly from the detailed description following below, one claimed electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.

    [0008] Another claimed electronic device includes an integrated circuit, a circuit board, and a connector. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit, and has a plurality of connector placement sites, at least a group of passive component placement sites, and a plurality of signal traces. The connector placement sites includes at least a first connector placement site each dedicated to one of the first and second signal processing circuits and at least a second connector placement site each dedicated to the other of the first and second signal processing circuits. The group of passive component placement sites is disposed between the first and second connector placement sites and has no passive component installed thereon. The signal traces include first signal traces making the first connector placement site and the output port electrically connected in series, second signal traces making the first connector placement site and the passive component placement sites electrically connected in series, and third signal traces making the second connector placement site and the passive component placement sites electrically connected in series. The connector is installed on the first connector placement site.

    [0009] In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof

    FIG. 1 is a block diagram illustrating a first exemplary layout design of a circuit board according to the present invention,

    FIG. 2 is a block diagram illustrating a first exemplary electronic device employing the circuit board shown in FIG. 1 according to the present invention,

    FIG. 3 is a block diagram illustrating a second exemplary electronic device employing the circuit board shown in FIG. 1 according to the present invention,

    FIG. 4 is a block diagram illustrating a second exemplary layout design of a circuit board according to the present invention,

    FIG. 5 is a block diagram illustrating a first exemplary electronic device employing the circuit board shown in FIG. 4 according to the present invention,

    FIG. 6 is a block diagram illustrating a second exemplary electronic device employing the circuit board shown in FIG. 4 according to the present invention,

    FIG. 7 is a block diagram illustrating a third exemplary layout design of a circuit board according to the present invention,

    FIG. 8 is a block diagram illustrating a fourth exemplary layout design of a circuit board according to the present invention,

    FIG. 9 is a block diagram illustrating a first exemplary electronic device employing the circuit board shown in FIG. 8 according to the present invention,

    FIG. 10 is a block diagram illustrating a second exemplary electronic device employing the circuit board shown in FIG. 8 according to the present invention,

    FIG. 11 is a block diagram illustrating a fifth exemplary layout design of a circuit board according to the present invention,

    FIG. 12 is a block diagram illustrating a first exemplary electronic device employing the circuit board shown in FIG. 11 according to the present invention,

    FIG. 13 is a block diagram illustrating a second exemplary electronic device employing the circuit board shown in FIG. 11 according to the present invention,

    and

    FIG. 14 is a block diagram illustrating a sixth exemplary layout design of a circuit board according to the present invention.



    [0010] Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ...". Also, the term "couple/electrically connect" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection maybe through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

    [0011] The conception of the present invention is to have multiple connector placement sites defined on the same circuit board (e.g., a printed circuit board) and dedicated to the same chip with multiple signal processing circuits integrated therein. Based on which one of the signal processing circuits that is selected to be used, a connector corresponding to the selected signal processing circuit is installed on one of the connector placement sites defined on the circuit board. In a case where another signal processing circuit is required to be selected and used, the circuit board with the same layout design of the connector placement sites can be employed for allowing a connector corresponding to the selected signal processing circuit to be installed on another one of the connector placement sites defined on the circuit board. To put it simply, the proposed circuit board layout is capable of meeting the requirements of different applications, thereby increasing the flexibility in the use of the circuit board. Further details are discussed as follows.

    [0012] Please refer to FIG. 1, which is a block diagram illustrating a first exemplary layout design of a circuit board according to the present invention. The circuit board (e.g., a printed circuit board) 100 has an integrated circuit placement site 102, a plurality of connector placement sites including at least a first connector placement site 104_1 and at least a second connector placement site 106_1, and a plurality of signal traces including first signal traces 108_1-108_5 and second signal traces 110_1-110_5. The integrated circuit placement site 102 has a plurality of connection nodes 103, such as pads or plated through holes (vias). Similarly, the first connector placement site 104_1 has a plurality of connection nodes 105, such as plated through holes (vias); and the second connector placement site 106_1 has a plurality of connection nodes 107, such as plated through holes (vias). The first signal traces 108_1-108_5 are electrically connected between the integrated circuit placement site 102 and the first connector placement site 104_1, and the second signal traces 110_1-110_5 are electrically connected between the first connector placement site 104_1 and the second connector placement site 106 1. As can be seen from FIG. 1, the integrated circuit placement site 102, the first connector placement site 104_1, and the second connector placement site 106_1 are electrically connected in series through the first signal traces 108_1-108_5 and second signal traces 110_1-110_5. It should noted that the number of connector placement sites shown in FIG. 1 and the number of signal traces shown in FIG. 1 are for illustrative purposes only, and are not meant to be limitations of the present invention.

    [0013] The integrated circuit placement site 102 is defined to allow an integrated circuit (i.e., a chip) to be installed thereon, and the connector placement sites, including the first connector placement site 104_1 and the second connector placement site 106_1, are defined to allow a connector with a specific connector type to be installed on one of the connector placement sites. By way of example, but not limitation, the first connector placement site 104_1 and the second connector placement site 106_1 correspond to different connector types (i.e., different interface types). For instance, the connector installed on the first connector placement site 104_1 /second connector placement site 106_1 may be a mini-LVDS (mini Low Voltage Differential Signal) interface, an EPI (Embedded Point-Point Interface) interface, a PPML (Point to Point mini-LVDS) interface, an Advanced PPML interface, a CalDriCon (Calibration Driver Controller) interface, an LVDS (Low Voltage Differential Signal) interface, a V-by-One interface, or an iDP (Internal DisplayPort) interface, depending upon actual design requirement.

    [0014] Please refer to FIG. 2, which is a block diagram illustrating a first exemplary electronic device employing the circuit board 100 shown in FIG. 1 according to the present invention. The exemplary electronic device 200 includes, but is not limited to, an integrated circuit 202, the circuit board 100 shown in FIG. 1, and a connector 204. The integrated circuit 202 may be a system-on-a-chip (SOC) installed on the integrated circuit placement site 102 defined on the circuit board 100, and includes, but is not limited to, a first signal processing circuit 212, a second signal processing circuit 214, and an interface multiplexer 216. The first signal processing circuit 212 and the second signal processing circuit 214 are arranged to perform different signal processing operations. For example, the first signal processing circuit 212 may be a scaler for processing video data to be displayed, or may include a scaler for processing video data to be displayed and a frame-rate conversion (FRC) circuit for adjusting the frame rate of an input video stream to a different frame rate. Regarding the second signal processing circuit 214, it may be a timing controller (T-CON) used to drive a display panel, such as a liquid crystal display (LCD) panel, according to an output of the first signal processing circuit 212. As a person skilled in the art can readily understand operations and functions of the scaler, the FRC circuit, and the timing controller, further description is omitted here for brevity.

    [0015] The interface multiplexer 216 has a first input port P1 electrically connected to the first signal processing circuit 212, a second input port P2 electrically connected to the second signal processing circuit 214, and an output port arranged to be electrically connected to the first input port P1 or the second input port P2. In this exemplary embodiment, the output port may be simply represented by certain connection nodes (plated through holes or pads) 103 to which the interface multiplexer 216 is electrically connected.

    [0016] In this exemplary embodiment, the first connector placement site 104_1 is dedicated to the first signal processing circuit 212, and the second connector placement site 106_1 is dedicated to the second signal processing circuit 214. That is, if a connector is installed on the first connector placement site 104_1, the installed connector would act as an output interface of the first signal processing circuit 212. Similarly, if a connector is installed on the second connector placement site 106_1, the installed connector would act as an output interface of the second signal processing circuit 214.

    [0017] In a case where a particular application employs the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202 for driving an external display panel (not shown), the interface multiplexer 216 would be controlled to have its output port electrically connected to the second port P2, thereby allowing the output of the second signal processing circuit 214 to be transmitted from the integrated circuit 202 to the external display panel. To meet the requirement of the particular application, the connector 204 is installed on the second connector placement site 106_1 dedicated to the second processing circuit 214. In this way, with a proper cable connection between the connector 204 and the external display panel, the output of the second signal processing circuit 214 is transmitted from the integrated circuit 202 to the external display panel. It should be noted that the first connector placement site 104_1 has no connector installed thereon in this case.

    [0018] In another case where a particular application employs an external timing controller, instead of the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202, for driving an external display panel (not shown), the interface multiplexer 216 would be controlled to have its output port electrically connected to the first port P1, thereby allowing the output of the first signal processing circuit 212 to be transmitted from the integrated circuit 202 to the external timing controller for further processing. Please refer to FIG. 3, which is a block diagram illustrating a second exemplary electronic device employing the circuit board shown in FIG. 1 according to the present invention. To meet the requirement of the particular application, the connector 304 is installed on the first connector placement site 104_1 dedicated to the first processing circuit 212. In this way, with a proper cable connection between the connector 304 and the external timing controller which may be installed on another circuit board, the output of the first signal processing circuit 212 is transmitted from the integrated circuit 202 to the external timing controller. It should be noted that the second connector placement site 106_1 has no connector installed thereon in this case.

    [0019] In above exemplary embodiments, the first connector placement site 104_1 dedicated to the first signal processing circuit 212 is closer to the integrated circuit 202 than the second connector placement site 106_1 dedicated to the second signal processing circuit 214. However, this is for illustrative purposes only. In an alternative design, the second connector placement site 106_1 may be closer to the integrated circuit 202 than the first connector placement site 104_1. FIG. 4 is a block diagram illustrating a second exemplary layout design of a circuit board according to the present invention. The exemplary circuit board 400 has a layout design similar to that of the exemplary circuit board 100 shown in FIG. 1. The major difference between them is that the second connector placement site 106_1 dedicated to the second signal processing circuit 214 is closer to the integrated circuit placement site 102 than the first connector placement site 104_1 dedicated to the first signal processing circuit 212.

    [0020] Please refer to FIG. 5 and FIG. 6 in conjunction with FIG. 4. FIG. 5 is a block diagram illustrating a first exemplary electronic device employing the circuit board 400 shown in FIG. 4 according to the present invention. FIG. 6 is a block diagram illustrating a second exemplary electronic device employing the circuit board 400 shown in FIG. 4 according to the present invention. In a case where a particular application employs the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202 for driving an external display panel (not shown), the interface multiplexer 216 of the exemplary electronic device 500 would be controlled to have its output port electrically connected to the second port P2, and the connector 204 is installed on the second connector placement site 106_1 dedicated to the second processing circuit 214. In another case where a particular application employs an external timing controller, instead of the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202, for driving an external display panel (not shown), the interface multiplexer 216 of the exemplary electronic device 600 would be controlled to have its output port electrically connected to the first port P1, and the connector 304 is installed on the first connector placement site 104_1 dedicated to the first signal processing circuit 212.

    [0021] Regarding the layout design of each circuit board 100/400, only one connector placement site dedicated to the first signal processing circuit 212 and only one connector placement site dedicated to the second signal processing circuit 214 are defined on the circuit board 100/400. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. FIG. 7 is a block diagram illustrating a third exemplary layout design of a circuit board according to the present invention. The circuit board (e.g., a printed circuit board) 700 has an integrated circuit placement site 702, a plurality of connector placement sites 704_1-704_4, and a plurality of signal traces including first signal traces 706_1-706_5 electrically connected between the integrated circuit placement site 702 and the connector placement site 704_1, second signal traces 708_1-708_5 electrically connected between connector placement sites 704_1 and 704_2, third signal traces 710_1-710 5 electrically connected between connector placement sites 704_2 and 704_3, and fourth signal traces 712_1-712_5 electrically connected between connector placement sites 704 3 and 704_4. The integrated circuit placement site 702 has a plurality of connection nodes 703, such as pads or plated through holes (vias). Similarly, each of the connector placement sites 704_1-704_4 has a plurality of connection nodes 705, such as plated through holes (vias). As can be seen from FIG. 7, the integrated circuit placement site 702 and the connector placement sites 704_1-704_4 are electrically connected in series through the first signal traces 706_1-706_5, the second signal traces 708_1-708_5, the third signal traces 710_1-710_5, and the fourth signal traces 712_1-712_5.

    [0022] It should be noted that the connector placement sites 704_1-704_4 include more than one connector placement site dedicated to at least one of the first signal processing circuit 212 and the second signal processing circuit 214. By way of example, but not limitation, the connector placement sites 704_1-704_2 are both dedicated to the first signal processing circuit 212 but correspond to different connector types (i.e., different interface types), and the connector placement sites 704_3-704_4 are both dedicated to the second signal processing circuit 214 but correspond to different connector types (i.e., different interface types). As the circuit board 700 supports more connector types for either of the first signal processing circuit 212 and the second signal processing circuit 214, the flexibility in the use of the circuit board 700 can be improved greatly. That is, with a target connector properly installed on one of the connector placement sites 704_1-704_4 defined by the circuit board layout design, a resultant electronic device employing the circuit board 700 to carry the integrated circuit 202 can meet the requirement of a particular application.

    [0023] In an alternative design, the connector placement sites 704_1-704_2 may be both dedicated to the second signal processing circuit 214 but correspond to different connector types, and the connector placement sites 704_3-704_4 may be both dedicated to the first signal processing circuit 212 but correspond to different connector types. The similar objective of supporting more connector types for either of the first signal processing circuit 212 and the second signal processing circuit 214 is achieved.

    [0024] In yet alternative design, one of the connector placement sites 704_1-704_4 is dedicated to one of the first signal processing circuit 212 and the second signal processing circuit 214, and the remaining connector placement sites are all dedicated to the other of the first signal processing circuit 212 and the second signal processing circuit 214 but correspond to different connector types. The similar objective of supporting more connector types for one of the first signal processing circuit 212 and the second signal processing circuit 214 is achieved.

    [0025] Moreover, as a person skilled in the art can readily understand details of possible electronic devices each employing the circuit board 700 shown in FIG. 7 after reading the above paragraphs directed to the exemplary electronic devices 200, 300, 500, and 600, further description is omitted here for brevity.

    [0026] As shown in FIG. 3, the connector 304 is installed on the first connector placement site 104_1 closer to the integrated circuit 202 than the second connector placement site 106_1, and the second connector placement site 106_1 has no connector installed thereon. When the first signal processing circuit 212 is generating an output to an external processing circuit (e.g., an external timing controller) through the connector 304, the outer second connector placement site 106_1 is electrically connected to the inner first connector placement site 104_1 through the second traces 110_1-110_5. Thus, the second connector placement site 106_1, which is not used for connector installation but is electrically connected to the first connector placement site 104_1 with the connector 304 installed thereon, may degrade the signal transmission quality of the output of the first signal processing circuit 212. Similarly, regarding the exemplary embodiment shown in FIG. 5, the connector 204 is installed on the second connector placement site 106_1 closer to the integrated circuit 202 than the first connector placement site 104_1, and the first connector placement site 104_1 has no connector installed thereon. When the second signal processing circuit 214 is generating an output to an external apparatus (e.g., an external display panel) through the connector 204, the outer first connector placement site 104_1 is electrically connected to the inner second connector placement site 106_1 through the second traces 110_1-110_5. The first connector placement site 104_1, which is not used for connector installation but is electrically connected to the second connector placement site 106_1 with the connector 204 installed thereon, may degrade the signal transmission quality of the output of the second signal processing circuit 214. The present invention therefore proposed an improved circuit board layout design to prevent the undesired signal degradation.

    [0027] Please refer to FIG. 8, which is a block diagram illustrating a fourth exemplary layout design of a circuit board according to the present invention. The circuit board (e.g., a printed circuit board) 800 has an integrated circuit placement site 802, a plurality of connector placement sites including at least a first connector placement site 804_1 and at least a second connector placement site 806_1, at least a group of passive component placement sites 808_1-808_5 disposed between the first connector placement site 804_1 and the second connector placement site 806_1, and a plurality of signal traces including first signal traces 810_1-810_5, second signal traces 812_1-812_5, and third signal traces 814_1-814_5. The integrated circuit placement site 802 has a plurality of connection nodes 803, such as pads or plated through holes (vias). Similarly, the first connector placement site 804_1 has a plurality of connection nodes 805, such as plated through holes (vias); the second connector placement site 806_1 has a plurality of connection nodes 807, such as plated through holes (vias); and each of the passive component placement sites 808_1-808_5 has a plurality of connection nodes 809, such as plated through holes (vias). As shown in FIG. 8, the first signal traces 810_1-810_5 are electrically connected between the integrated circuit placement site 802 and the first connector placement site 804_1, the second signal traces 812_1-812_5 are electrically connected between the first connector placement site 804_1 and the group of passive component placement sites 808_1-808_5, and the third signal traces 814_1-814_5 are electrically connected between the group of passive component placement sites 808_1-808_5 and the second connector placement site 806_1. It should noted that the number of connector placement sites shown in FIG. 8, the number of signal traces shown in FIG. 8, and the number of passive component placement sites shown in FIG. 8 are for illustrative purposes only, and are not meant to be limitations of the present invention.

    [0028] The function of the integrated circuit placement site 802 is identical to that of the integrated circuit placement site 102, and the function of the connector placement sites, including the first connector placement site 804_1 and the second connector placement site 806_1, is identical to that of the connector placement sites, including the first connector placement site 104_1 and the second connector placement site 106_1. Further description is omitted here for brevity. Regarding each of the passive placement sites 808_1-808_5, it is defied to allow a passive component, such as a zero-ohm resistor, to be installed thereon.

    [0029] Please refer to FIG. 9, which is a block diagram illustrating a first exemplary electronic device employing the circuit board 800 shown in FIG. 8 according to the present invention. The exemplary electronic device 900 includes, but is not limited to, the integrated circuit 202, the circuit board 800 shown in FIG. 8, the connector 204 installed on the second connector placement site 806_1, and a plurality of passive components 902_1-902_5 (e.g., zero-ohm resistors) respectively installed on the passive component placement sites 808_1-808_5. In this exemplary embodiment, the first connector placement site 804_1 is dedicated to the first signal processing circuit 212, and the second connector placement site 806_1 is dedicated to the second signal processing circuit 214. In a case where a particular application employs the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202 for driving an external display panel (not shown), the interface multiplexer 216 would be controlled to have its output port electrically connected to the second port P2. Therefore, the connector 204 is installed on the second connector placement site 806_1 dedicated to the second processing circuit 214 for allowing the signal transmission between the second signal processing circuit 214 and the external display panel. The configuration of the exemplary electronic device 900 shown in FIG. 9 is similar to that of the exemplary electronic device 200 shown in FIG. 2. The major difference between them is that the second connector placement site 806_1, the first connector placement site 804_1, and the integrated circuit placement site 802 are electrically connected in series through the first signal traces 810_1-810_5, the second signal traces 812_1-812_5, the installed passive components 902_1-902_5, and the third signal traces 814_1-814_5.

    [0030] In another case where a particular application employs an external timing controller, instead of the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202, for driving an external display panel, the interface multiplexer 216 would be controlled to have its output port electrically connected to the first port P1, thereby allowing the output of the first signal processing circuit 212 to be transmitted from the integrated circuit 202 to the external timing controller (not shown). Please refer to FIG. 10, which is a block diagram illustrating a second exemplary electronic device employing the circuit board 800 shown in FIG. 8 according to the present invention. To meet the requirement of the particular application, the connector 304 is installed on the first connector placement site 804_1 dedicated to the first processing circuit 212. It should be noted that the passive component placement sites 808_1-808_5 have no passive component installed thereon. In other words, each of the passive component placement sites 808_1-808_5 acts as an open circuit. In this way, the second connector placement site 806_1 would be isolated from the first connector placement site 804_1 on which the connector 304 is installed, thereby avoiding the undesired signal degradation caused by the second connector placement site 806_1.

    [0031] In above exemplary embodiments shown in FIG. 9 and FIG. 10, the first connector placement site 804_1 dedicated to the first signal processing circuit 212 is closer to the integrated circuit 202 than the second connector placement site 806_1 dedicated to the second signal processing circuit 214. However, this is for illustrative purposes only. In an alternative design, the second connector placement site 806_1 may be closer to the integrated circuit 202 than the first connector placement site 804_1. FIG. 11 is a block diagram illustrating a fifth exemplary layout design of a circuit board according to the present invention. The exemplary circuit board 1100 has a layout design similar to that of the exemplary circuit board 800 shown in FIG. 8. The major difference between them is that the second connector placement site 806_1 is closer to the integrated circuit placement site 802 than the first connector placement site 804_1.

    [0032] Please refer to FIG. 12 and FIG. 13 in conjunction with FIG. 11. FIG. 12 is a block diagram illustrating a first exemplary electronic device employing the circuit board 1100 shown in FIG. 11 according to the present invention. FIG. 13 is a block diagram illustrating a second exemplary electronic device employing the circuit board shown 1100 in FIG. 11 according to the present invention. In a case where a particular application employs the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202 for driving an external display panel, the interface multiplexer 216 of the exemplary electronic device 1200 would be controlled to have its output port electrically connected to the second port P2, and the connector 204 is installed on the second connector placement site 806_1 dedicated to the second processing circuit 214. In another case where a particular application employs an external timing controller, instead of the internal timing controller (i.e., the second signal processing circuit 214) implemented in the integrated circuit 202, for driving an external display panel, the interface multiplexer 216 of the exemplary electronic device 1300 would be controlled to have its output port electrically connected to the first port P1, and the connector 304 is installed on the first connector placement site 804_1 dedicated to the first signal processing circuit 212. Regarding the electronic device 1300 shown in FIG. 13, the passive component placement sites 808_1-808_5 have passive components 902_1-902_5 installed thereon, respectively. Regarding the electronic device 1200 shown in FIG. 12, the passive component placement sites 808_1-808_5 have no passive component installed thereon, thereby improving the signal transmission quality.

    [0033] By way of example, but not limitation, the connector type and/or the interference tolerance may be taken into consideration when defining which one of the first connector placement site 804_1 and the second connector placement site 806_1 should be located closer to the integrated circuit placement site 802. Consider a case where one of the first connector placement site 804_1 and the second connector placement site 806_1 may be defined for allowing installation of an LVDS connector, and the other of the first connector placement site 804_1 and the second connector placement site 806_1 may be defined for allowing installation of a mini-LVDS connector. As the mini-LVDS connector is less resistant to interference, the connector placement site defined for allowing installation of a mini-LVDS connector would be closer to the integrated circuit placement site 802 than the connector placement site defined for allowing installation of an LVDS connector.

    [0034] Consider another case where one of the first connector placement site 804_1 and the second connector placement site 806_1 may be defined for allowing installation of a first connector with a first connector shape, and the other of the first connector placement site 804_1 and the second connector placement site 806_1 may be defined for allowing installation of a second connector with a second connector shape. If installing the first connector on a connector placement site closer to the integrated circuit placement site 802 is easier than installing the first connector on a connector placement site far away from the integrated circuit placement site 802, the connector placement site defined for allowing installation of the first connector with the first connector shape would be closer to the integrated circuit placement site 802 than the connector placement site defined for allowing installation of the second connector with the second connector shape.

    [0035] Regarding the layout design of each circuit board 800/1100, only one connector placement site dedicated to the first signal processing circuit 212 and only one connector placement site dedicated to the second signal processing circuit 214 are defined on the circuit board 800/1100. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. FIG. 14 is a block diagram illustrating a sixth exemplary layout design of a circuit board according to the present invention. The circuit board (e.g., a printed circuit board) 1400 has an integrated circuit placement site 1402, a plurality of connector placement sites 1404_1-1404_4, a plurality of groups of passive component placement sites 1406-1-1406_5, 1408-1-1408_5, and 1410-1-1410_5, and a plurality of signal traces including first signal traces 1412_1-1412_5 electrically connected between the integrated circuit placement site 1402 and the connector placement site 1404_1, second signal traces 1414_1-1414_5 electrically connected between the connector placement site 1404_1 and passive component placement sites 1406_1-1406_5, third signal traces 1416_1-1416_5 electrically connected between the connector placement site 1404_2 and passive component placement sites 1406_1-1406_5, fourth signal traces 1418_1-1418_5 electrically connected between the connector placement site 1404_2 and passive component placement sites 1408_1-1408_5, fifth signal traces 1420_1-1420_5 electrically connected between the connector placement site 1404_3 and passive component placement sites 1408_1-1408_5, sixth signal traces 1422_1-1422_5 electrically connected between the connector placement site 1404_3 and passive component placement sites 1410_1-1410_5, and seventh signal traces 1424_1-1424_5 electrically connected between the connector placement site 1404_4 and passive component placement sites 1410_1-1410_5.

    [0036] The integrated circuit placement site 1402 has a plurality of connection nodes 1403, such as pads or plated through holes (vias). Similarly, each of the connector placement sites 1404_1-1404_4 has a plurality of connection nodes 1405, such as plated through holes (vias), and each of the passive component placement sites 1406_1-1406_5, 1408_1-1408_5, and 1410_1-1410_5 has a plurality of connection nodes 1407, such as plated through holes (vias).

    [0037] It should be noted that the connector placement sites 1404_1-1404_4 have more than one connector placement site dedicated to at least one of the first signal processing circuit 212 and the second signal processing circuit 214. By way of example, but not limitation, the connector placement sites 1404_1-1404_2 are both dedicated to the first signal processing circuit 212 but correspond to different connector types (i.e., different interface types), and the connector placement sites 1404_3-1404_4 are both dedicated to the second signal processing circuit 214 but correspond to different connector types (i.e., different interface types). In an alternative design, the connector placement sites 1404_1-1404_2 may be both dedicated to the second signal processing circuit 214 but correspond to different connector types, and the connector placement sites 1404_3-1404_4 may be both dedicated to the first signal processing circuit 212 but correspond to different connector types. In yet alternative design, one of the connector placement sites 1404_1-1404_4 is dedicated to one of the first signal processing circuit 212 and the second signal processing circuit 214, and the remaining connector placement sites are all dedicated to the other of the first signal processing circuit 212 and the second signal processing circuit 214 but correspond to different connector types.

    [0038] Moreover, as a person skilled in the art can readily understand details of exemplary electronic devices each employing the circuit board 1400 shown in FIG. 14 after reading the above paragraphs directed to the exemplary electronic devices 900, 1000, 1200, and 1300, further description is omitted here for brevity.

    [0039] It should be noted that the connector placement sites defined on the same circuit board may correspond to different connector types. It is possible that connectors with different connector types may have different numbers of connection pins. In order to make connector placement sites on the circuit board layout design successfully support different connector types through only signal traces as shown in FIG. 1, FIG. 4 and FIG. 7 or a combination of signal traces and passive component placement sites as shown in FIG. 8, FIG. 11, and FIG. 14, each of the connector placement sites may be configured to have the number of connection nodes equal to a maximum value among the connection pin numbers of all supported connector types. To put it simply, part or all of the connection nodes defined in a connector placement site may be used for actual signal transmission, depending upon a connector type of a connector installed on the connector placement site.

    [0040] All combinations and sub-combinations of the above-described features which fall within the scope defined by the appended claims also belong to the invention.


    Claims

    1. An electronic device (200, 300, 500, 600, 900, 1300), characterized by:

    an integrated circuit (202), comprising:

    a first signal processing circuit (212);

    a second signal processing circuit (214); and

    an interface multiplexer (216), having a first input port electrically connected to the first signal processing circuit (212), a second input port electrically connected to the second signal processing circuit (214), and an output port arranged to be electrically connected to the first input port or the second input port;

    a circuit board (100, 400, 800, 1100, 700, 1400), carrying the integrated circuit (202) and comprising:

    a plurality of connector placement sites (104_1, 106_1, 804_1, 806_1, 704_1-704_4, 1404_1-1404_4), including at least a first connector placement site (104_1, 804_1) each dedicated to the first signal processing circuit (212) and at least a second connector placement site (106_1, 806_1) each dedicated to the second signal processing circuit (214), wherein the connector placement sites (104_1, 106_1, 804_1, 806_1) and the output port of the interface multiplexer (216) are electrically connected in series; and

    a connector (204, 304), installed on one of the connector placement sites (104_1, 106_1, 804_1, 806_1).


     
    2. The electronic device (300, 600, 1300) of claim 1, characterized in that the output port is electrically connected to the first input port, the connector (304) is installed on the first connector placement site (104_1, 804_1), and the second connector placement site has no connector installed thereon.
     
    3. The electronic device (300, 600, 1300) of claim 1, characterized in that the connector placement sites (704_1-704_4,1404_1-1404_4) includes a plurality of first connector placement sites dedicated to the first signal processing circuit (212), the output port is electrically connected to the first input port, the connector (304) is installed on one of the first connector placement sites, and each remaining first connector placement site and the second connector placement site have no connector installed thereon.
     
    4. The electronic device (200, 300, 500, 600, 900, 1300) of claim 1, characterized in that the first signal processing circuit (121) is a video processing circuit, and the second signal processing circuit (214) is a timing controller.
     
    5. The electronic device (200, 300, 900) of claim 4, characterized in that the first connector placement site (104_1, 804_1) is closer to the integrated circuit (202) than the second connector placement site (106_1, 806_1).
     
    6. The electronic device (500, 600, 1300) of claim 4, characterized in that the second connector placement site (106_1, 806_1) is closer to the integrated circuit (202) than the first connector placement site (104_1, 804_1).
     
    7. The electronic device (200, 300) of claim 1, characterized in that the circuit board further comprises:

    a plurality of signal traces (108_1-108_5, 110_1-110_5), including first signal traces (108_1-108_5) electrically connected between the first connector placement site (104_1) and the output port of the interface multiplexer (216) and second signal traces (110_1-110_5) electrically connected between the first connector placement site (104_1) and the second connector placement site (106_1), wherein the output port of the interface multiplexer (216), the first connector placement site (104_1), and the second connector placement site (106_1) are electrically connected in series through the first signal traces (108_1-108_5) and the second signal traces (110_1-110_5).


     
    8. The electronic device (900) of claim 1, characterized in that the circuit board (800) further comprises:

    a group of passive component placement sites (808_1-808_5), disposed between the first connector placement site (804_1) and the second connector placement site (806_1); and

    a plurality of signal traces (810_1-810_5, 812_1-812_5, 814_1-814_5), including first signal traces (810_1-810_5) electrically connected between the output port of the interface multiplexer (216) and the first connector placement site (804_1), second signal traces (812_1-812_5) electrically connected between the first connector placement site (804_1) and the group of passive component placement sites (808_1-808_5), and third signal traces (814_1-814_5) electrically connected between the second connector placement site (806_1) and the group of passive component placement sites (808_1-808_5); and

    the electronic device (900) further comprises a plurality of passive components (902_1-902_5) installed on the passive component placement sites (808_1-808_5), respectively, and the output port of the interface multiplexer (216), the first connector placement site (804_1), and the second connector placement site (806_1) are electrically connected in series through the passive components (902_1-902_5) and the first, second, and third signal traces (810_1-810_5, 812_1-812_5, 814_1-814_5).


     
    9. An electronic device (1000, 1200), characterized by:

    an integrated circuit (202), comprising:

    a first signal processing circuit (212);

    a second signal processing circuit (214); and

    an interface multiplexer (216), having a first input port electrically connected to the first signal processing circuit (212), a second input port electrically connected to the second signal processing circuit (214), and an output port arranged to be electrically connected to the first input port or the second input port;

    a circuit board (800, 1100), carrying the integrated circuit (202) and comprising:

    a plurality of connector placement sites (804_1, 806_1, 1404_1, 1404_2, 1404_3, 1404_4), including at least a first connector placement site (804_1, 806_1) each dedicated to one of the first and second signal processing circuits (212, 214) and at least a second connector placement site (806_1, 804_1) each dedicated to the other of the first and second signal processing circuits (212, 214);

    at least a group of passive component placement sites (808_1-808_5, 1406_1-1406_5, 1408_1-1408_5, 1410_1-1410_5), disposed between the first and second connector placement sites (804_1, 806_1) and having no passive component installed thereon; and

    a plurality of signal traces (810_1-810_5, 812_1-812_5, 814_1-814_5), including first signal traces (810_1-810_5) making the first connector placement site (804_1, 806_1) and the output port electrically connected in series, second signal traces (812_1-812_5) making the first connector placement site (804_1, 806_1) and the passive component placement sites (808_1-808_5) electrically connected in series, and third signal traces (814_1-814_5) making the second connector placement site (806_1, 804_1) and the passive component placement sites (814_1-814_5) electrically connected in series; and

    a connector (204, 304), installed on the first connector placement site.


     
    10. The electronic device (1000) of claim 9, characterized in that the output port is electrically connected to the first input port, the connector (304) is installed on the first connector placement site (804_1) dedicated to the first signal processing circuit (212), and the second connector placement site (806_1) dedicated to the second signal processing circuit (214) has no connector installed thereon.
     
    11. The electronic device (1200) of claim 9, characterized in that the output port is electrically connected to the second input port, the connector (204) is installed on the second connector placement site (806_1) dedicated to the second signal processing circuit (214), and the first connector placement site (804_1) dedicated to the first signal processing circuit (212) has no connector installed thereon.
     
    12. The electronic device (1000,1200) of claim 9, characterized in that connector placement sites (1404_1-1404_4) include a plurality of first connector placement sites and a plurality of second connector placement sites; and the circuit board includes a plurality of groups of passive component placement sites (1406_1-1406_5, 1408_1-1408_5, 1410_1-1410_5) each disposed between two adjacent connector placement sites of the connector placement sites.
     
    13. The electronic device (1000, 1200) of claim 9, characterized in that the first signal processing circuit (212) is a video processing circuit, and the second signal processing circuit (214) is a timing controller.
     


    Ansprüche

    1. Elektronische Vorrichtung (200, 300, 500, 600, 900, 1300), gekennzeichnet durch:

    eine integrierte Schaltung (202), umfassend:

    eine erste Signalverarbeitungsschaltung (212);

    eine zweite Signalverarbeitungsschaltung (214); und

    einen Interface-Multiplexer (216), der einen ersten Eingangsport, der an der ersten Signalverarbeitungsschaltung (212) elektrisch angeschlossen ist, einen zweiten Eingangsport, der an der zweiten Signalverarbeitungsschaltung (214) elektrisch angeschlossen ist, und einen Ausgangsport aufweist, der zum elektrischen Anschluss am ersten Eingangsport oder am zweiten Eingangsport angeordnet ist;

    eine Leiterplatte (100, 400, 800, 1100, 700, 1400), weiche die integrierte Schaltung (202) aufnimmt und umfasst:

    eine Mehrzahl von Verbindungselement-Einsatzstellen (104_1, 106_1, 804_1, 806_1, 704_1 - 704_4, 1404_1 - 1404_4), die zumindest eine erste Verbindungselement-Einsatzstelle (104_1, 804_1), die jeweils der ersten Signalverarbeitungsschaltung (212) zugeordnet ist, und zumindest eine zweite Verbindungselement-Einsatzstelle (106_1, 806_1) umfasst, die jeweils der zweiten Signalverarbeitungsschaltung (214) zugeordnet ist, wobei die Verbindungselement-Einsatzstellen (104_1, 106_1, 804_1, 806_1) und der Ausgangsport des Interface-Multiplexers (216) elektrisch in Reihe geschaltet sind; und

    ein Verbindungselement (204, 304), das an einer der Verbindungselement-Einsatzstellen (104_1, 106_1, 804_1, 806_1) montiert ist.


     
    2. Elektronische Vorrichtung (300, 600, 1300) nach Anspruch 1, dadurch gekennzeichnet, dass der Ausgangsport am ersten Eingangsport elektrisch angeschlossen ist, das Verbindungselement (304) auf der ersten Verbindungselement-Einsatzstelle (104_1, 804_1) montiert ist und die zweite Verbindungselement-Einsatzstelle kein daran montiertes Verbindungselement aufweist.
     
    3. Elektronische Vorrichtung (300, 600, 1300) nach Anspruch 1, dadurch gekennzeichnet, dass die Verbindungselement-Einsatzstellen (704_1 - 704_4, 1404_1 - 1404_4) eine Mehrzahl von ersten Verbindungselement-Einsatzstellen aufweisen, die der ersten Signalverarbeitungsschaltung (212) zugeordnet sind, der Ausgangsport am ersten Eingangsport elektrisch angeschlossen ist, das Verbindungselement (304) an einer der ersten Verbindungselement-Einsatzstellen montiert ist und jede verbleibende erste Verbindungselement-Einsatzstelle und zweite Verbindungselement-Einsatzstelle kein daran montiertes Verbindungselement aufweisen.
     
    4. Elektronische Vorrichtung (200, 300, 500, 600, 900, 1300) nach Anspruch 1, dadurch gekennzeichnet, dass die erste Signalverarbeitungsschaltung (121) eine Video-Verarbeitungsschaltung ist, und die zweite SignalVerarbeitungsschaltung (214) eine Zeitsteuerung ist.
     
    5. Elektronische Vorrichtung (200, 300, 900) nach Anspruch 4, dadurch gekennzeichnet, dass die erste Verbindungselement-Einsatzstelle (104_1, 804_1) näher an der integrierten Schaltung (202) als die zweite Verbindungselement-Einsatzstelle (106_1, 806_1) liegt.
     
    6. Elektronische Vorrichtung (500, 600, 1300) nach Anspruch 4, dadurch gekennzeichnet, dass die zweite Verbindungselement-Einsatzstelle (106_1, 806_1) näher an der integrierten Schaltung (202) als die erste Verbindungselement-Einsatzstelle (104_1, 804_1) liegt.
     
    7. Elektronische Vorrichtung (200, 300) nach Anspruch 1, dadurch gekennzeichnet, dass die Leiterplatte ferner umfasst:

    eine Mehrzahl von Signalspuren (108_1 - 108_5, 110_1 - 110_5) einschließlich ersten Signalspuren (108_1 - 108_5), die zwischen der ersten Verbindungselement-Einsatzstelle (104_1) und dem Ausgangsport des Interface-Multiplexers (216) elektrisch angeschlossen sind, und zweiten Signalspuren (110_1 - 110_5), die zwischen der ersten Verbindungselement-Einsatzstelle (104_1) und der zweiten Verbindungselement-Einsatzstelle (106_1 elektrisch angeschlossen sind, wobei der Ausgangsport des Interface-Multiplexers (216), die erste Verbindungselement-Einsatzstelle (104_1) und die zweite Verbindungselement-Einsatzstelle (106_1) durch die ersten Signalspuren (108_1 - 108_5) und die zweiten Signalspuren (110_1 - 110_5) elektrisch in Reihe geschaltet sind.


     
    8. Elektronische Vorrichtung (900) nach Anspruch 1, dadurch gekennzeichnet, dass die Leiterplatte (800) ferner umfasst:

    eine Gruppe von passiven Komponenten-Einsatzstellen (808_1 - 808_5), die zwischen der ersten Verbindungselement-Einsatzstelle (804_1) und der zweiten Verbindungselement-Einsatzstelle (806_1) angeordnet sind; und

    eine Mehrzahl von Signalspuren (810_1 - 810_5, 812_1 - 812_5, 814_1 - 814_5) einschließlich ersten Signalspuren (810_1 - 810-5), die zwischen dem Ausgangsport des Interface-Multiplexers (216) und der ersten Verbindungselement-Einsatzstelle (804_1) elektrisch angeschlossen sind, zweiten Signalspuren (812_1 - 812_5), die zwischen der ersten Verbindungselement-Einsatzstelle (804_1) und der Gruppe von passiven Komponenten-Einsatzstellen (808_1 - 808_5) elektrisch angeschlossen sind und dritten Signalspuren (814_1 - 814_5), die zwischen der zweiten Verbindungselement-Einsatzstelle (806_1) und der Gruppe von passiven Komponenten-Einsatzstellen (808_1 - 808_5) elektrisch angeschlossen sind; und

    die elektronische Vorrichtung (900) ferner eine Mehrzahl von passiven Komponenten (902_1 - 902_5) umfasst, die jeweils auf den passiven Komponenten-Einsatzstellen (808_1- 808_5) montiert sind, und der Ausgangsport des Interface-Multiplexers (216), die erste Verbindungselement Einsatzstelle (804_1) und die zweite Verbindungselement-Einsatzstelle (806_1) durch die passiven Komponenten (902_1 - 902_5) und die ersten, zweiten und dritten Signalspuren (810_1 - 810_5, 812_1 - 812_5, 814_1 - 814_5) elektrisch in Reihe geschaltet sind.


     
    9. Elektronische Vorrichtung (1000, 1200), gekennzeichnet durch:

    eine integrierte Schaltung (202), umfassend:

    eine erste Signalverarbeitungsschaltung (212);

    eine zweite Signalverarbeitungsschaltung (214); und

    einen Interface-Multiplexer (216), der einen ersten Eingangsport, der an der ersten Signalverarbeitungsschaltung (212) elektrisch angeschlossen ist, einen zweiten Eingangsport, der an der zweiten Signalverarbeitungsschaltung (214) elektrisch angeschlossen ist, und einen Ausgangsport aufweist, der zum elektrischen Anschluss am ersten Eingangsport oder am zweiten Eingangsport angeordnet ist;

    eine Leiterplatte (800, 1100), welche die integrierte Schaltung (202) aufnimmt und umfasst:

    eine Mehrzahl von Verbindungselement-Einsatzstellen (804_1, 806_1, 1404_1, 1404_2, 1404_3, 1404_4), die zumindest eine erste Verbindungselement-Einsatzstelle (804_1, 806_1), die jeweils einer der ersten oder zweiten Signalverarbeitungsschaltungen (212, 214) zugeordnet ist, und zumindest eine zweite Verbindungselement-Einsatzstelle (806_1, 804_1) umfasst, die jeweils der anderen der ersten und zweiten Signalverarbeitungsschaltungen (212, 214) zugeordnet ist;

    zumindest eine Gruppe von passiven Komponenten-Einsatzstellen (808_1 - 808_5, 1406_1 - 1406_5, 1408_1 - 1408_5, 1410_1 - 1410_5), die zwischen den ersten und zweiten Verbindungselement-Einsatzstellen (804_1, 806_1) angeordnet sind und keine darauf montierte passive Komponente aufweisen; und

    eine Mehrzahl von Signalspuren (810_1 - 810_5, 812_1 - 812_5, 814_1 - 814_5) einschließlich ersten Signalspuren (810_1-810_5), die eine elektrische Reihenschaltung der erste Verbindungselement-Einsatzstelle (804_1, 806_1) und des Ausgangsports bewirken, zweiten Signalspuren (812_1 -812_5), die eine elektrische Reihenschaltung der ersten Verbindungselement-Einsatzstelle (804_1, 806_1) und der passiven Komponenten-Einsatzstellen (808_1 - 808_5) bewirken, und dritten Signalspuren (814_1 - 814_5), die eine elektrische Reihenschaltung der zweiten Verbindungselement-Einsatzstelle (806_1, 804_1) und der passiven Komponenten-Einsatzstellen (814_1-814_5) bewirken; und

    einem Verbindungselement (204, 304), das auf der ersten Verbindungselement-Einsatzstelle montiert ist.


     
    10. Elektronische Vorrichtung (1000) nach Anspruch 9, dadurch gekennzeichnet, dass der Ausgangsport am ersten Eingangsport elektrisch angeschlossen ist, das Verbindungselement (304) auf der ersten Verbindungselement-Einsatzstelle (804_1) montiert ist, die der ersten Signalverarbeitungsschaltung (212) zugeordnet ist, und die zweite Verbindungselement-Einsatzstelle (806_1), die der zweiten Signalverarbeitungsschaltung (214) zugeordnet ist, kein darauf montiertes Verbindungselement aufweist.
     
    11. Elektronische Vorrichtung (1200) nach Anspruch 9, dadurch gekennzeichnet, dass der Ausgangsport am zweiten Eingangsport elektrisch angeschlossen ist, das Verbindungselement (204) auf der zweiten Verbindungselement-Einsatzstelle (806_1) montiert ist, die der zweiten Signalverarbeitungsschaltung (214) zugeordnet ist, und die erste Verbindungselement-Einsatzstelle (804_1), die der ersten Signalverarbeitungsschaltung (212) zugeordnet ist, kein darauf montiertes Verbindungselement aufweist.
     
    12. Elektronische Vorrichtung (1000, 1200) nach Anspruch 9, dadurch gekennzeichnet, dass die Verbindungselement-Einsatzstellen (1404_1 - 1404_4) eine Mehrzahl von ersten Verbindungselement-Einsatzstellen und eine Mehrzahl von zweiten Verbindungselement-Einsatzstellen umfassen; und die Leiterplatte eine Mehrzahl von Gruppen von passiven Komponenten-Einsatzstellen (1406_1 - 1406_5, 1408_1 - 1408_5, 1410_1 - 1410_5) umfasst, die jeweils zwischen zwei benachbarten Verbindungselement-Einsatzstellen der Verbindungselement-Einsatzstellen angeordnet sind.
     
    13. Elektronische Vorrichtung (1000, 1200) nach Anspruch 9, dadurch gekennzeichnet, dass die erste Signalverarbeitungsschaltung (212) eine Video-Verarbeitungsschaltung ist und die zweite Signalverarbeitungsschaltung (214) eine Zeitsteuerung ist.
     


    Revendications

    1. Dispositif électronique (200, 300, 500, 600, 900, 1300), caractérisé par :

    un circuit intégré (202), comprenant :

    un premier circuit de traitement de signal (212) ;

    un second circuit de traitement de signal (214) ; et

    un multiplexeur d'interface (216), ayant un premier port d'entrée électriquement connecté au premier circuit de traitement de signal (212), un second port d'entrée électriquement connecté au second circuit de traitement de signal (214), et un port de sortie disposé pour être électriquement connecté au premier port d'entrée ou au second port d'entrée ;

    une carte de circuit imprimé (100, 400, 800, 1100, 700, 1400), portant le circuit intégré (202) et comprenant :

    une pluralité de sites de mise en place de connecteur (104_1, 106_1, 804_1, 806_1, 704_1-704_4, 1404_1-1404_4), comprenant au moins un premier site de mise en place de connecteur (104_1, 804_1) chacun dédié au premier circuit de traitement de signal (212) et au moins un second site de mise en place de connecteur (106_1, 806_1) chacun dédié au second circuit de traitement de signal (214), où les sites de mise en place de connecteur (104_1, 106_1, 804_1, 806_1) et le port de sortie du multiplexeur d'interface (216) sont électriquement connectés en série ; et

    un connecteur (204, 304), installé sur une des sites de mise en place de connecteur (104_1, 106_1, 804_1, 806_1).


     
    2. Dispositif électronique (300, 600, 1300) selon la revendication 1, caractérisé en ce que le port de sortie est électriquement connecté au premier port d'entrée, le connecteur (304) est installé sur le premier site de mise en place de connecteur (104_1, 804_1), et le second site de mise en place de connecteur sur lequel aucun connecteur n'est installé.
     
    3. Dispositif électronique (300, 600, 1300) selon la revendication 1, caractérisé en ce que les sites de mise en place de connecteur (704_1 - 704_4, 1404_1-1404_4) comprennent une pluralité de premiers sites de mise en place de connecteur dédiés au premier circuit de traitement de signal (212), le port de sortie est électriquement connecté au premier port d'entrée, le connecteur (304) est installé sur un des premiers sites de mise en place de connecteur, et chaque premier site de mise en place de connecteur restant et le second site de mise en place de connecteur ne sont pourvus d'aucun connecteur.
     
    4. Dispositif électronique (200, 300, 500, 600, 900, 1300) selon la revendication 1, caractérisé en ce que le premier circuit de traitement de signal (121) est un circuit de traitement vidéo, et le second circuit de traitement de signal (214) est un contrôleur de synchronisation.
     
    5. Dispositif électronique (200, 300, 900) selon la revendication 4, caractérisé en ce que le premier site de mise en place de connecteur (104_1, 804_1) est plus proche du circuit intégré (202) que le second site de mise en place de connecteur (106_1, 806_1).
     
    6. Dispositif électronique (500, 600, 1300) selon la revendication 4, caractérisé en ce que le second site de mise en place de connecteur (106_1, 806_1) est plus proche du circuit intégré (202) que le premier site de mise en place de connecteur (104_1, 804_1).
     
    7. Dispositif électronique (200, 300) selon la revendication 1, caractérisé en ce que la carte de circuit imprimé comprend en outre :

    une pluralité de traces de signal (108_1-108_5, 110_1-110_5), comprenant des premières traces de signal (108_1-108_5) électriquement connectées entre le premier site de mise en place de connecteur (104_1) et le port de sortie du multiplexeur d'interface (216) et des deuxièmes traces de signal (110_1-110_5) électriquement connectées entre le premier site de mise en place de connecteur (104_1) et le second site de mise en place de connecteur (106_1), où le port de sortie du multiplexeur d'interface (216), le premier site de mise en place de connecteur (104_1), et le second site de mise en place de connecteur (106_1) sont électriquement connectés en série par l'intermédiaire des premières traces de signal (108_1-108_5) et des deuxièmes traces de signal (110_1-110_5).


     
    8. Dispositif électronique (900) selon la revendication 1, caractérisé en ce que la carte de circuit imprimé (800) comprend en outre :

    un groupe de sites de mise en place de composant passif (801_1-808_5), disposé entre le premier site de mise en place de connecteur (804_1) et le second site de mise en place de connecteur (806_1) ; et

    une pluralité de traces de signal (810_1-810_5, 812_1-812_5, 814_1-814-5), comprenant des premières traces de signal (810_1-810_5) électriquement connectées entre le port de sortie du multiplexeur d'interface (216) et le premier site de mise en place de connecteur (804_1), des deuxièmes traces de signal (812_1-812_5) électriquement connectées entre le premier site de mise en place de connecteur (804_1) et le groupe de sites de mise en place de composant passif (808_1-808_5), et des troisièmes traces de signal (814_1-814_5) électriquement connectées entre le second site de mise en place de connecteur (806_1) et le groupe de sites de mise en place de composant passif (808_1-808_5) ; et

    le dispositif électronique (900) comprend en outre une pluralité de composants passifs (902_1-902_5) installés sur les sites de mise en place de composant passif (808_1-808_5), respectivement, et le port de sortie du multiplexeur d'interface (216), le premier site de mise en place de connecteur (804_1), et le second site de mise en place de connecteur (806_1) sont électriquement connectés en série par l'intermédiaire des composants passifs (902_1-902_5) et les premières, deuxièmes, et troisièmes traces de signal (810_1-810_5, 812_1-812_5, 814_1-814_5).


     
    9. Dispositif électronique (1000, 1200), caractérisé par :

    un circuit intégré (202), comprenant :

    un premier circuit de traitement de signal (212) ;

    un second circuit de traitement de signal (214) ; et

    un multiplexeur d'interface (216), ayant un premier port d'entrée électriquement connecté au premier circuit de traitement de signal (212), un second port d'entrée électriquement connecté au second circuit de traitement de signal (214), et un port de sortie disposé pour être électriquement connecté au premier port d'entrée ou au second port d'entrée ;

    une carte de circuit imprimé (800, 1100), portant le circuit intégré (202) et comprenant :

    une pluralité de sites de mise en place de connecteur (804_1, 806_1, 1404_1, 1404_2, 1404_3, 1404_4), comprenant au moins un premier site de mise en place de connecteur (804_1, 806_1) chacun dédié à l'un des premier et second circuits de traitement de signal (212, 214) et au moins un second site de mise en place de connecteur (806_1, 804_1) chacun dédié à l'autre du premier et second circuits de traitement de signal (212, 214),

    au moins un groupe de sites de mise en place de composant passif (808_1-808_5, 1406_1-1406_5, 1408_1-1408_5, 1410_1-1410_5), disposés entre les premier et second sites de mise en place de connecteur (804_1, 806_1) et n'étant pas pourvus de composant passif ; et

    une pluralité de traces de signal (810_1-810_5, 812_1-812_5, 814_1-814-5), comprenant des premières traces de signal (810_1-810_5) amenant le premier site de mise en place de connecteur (804_1, 806_1) et le port de sortie à être électriquement connectés en série, des deuxièmes traces de signal (812_1-812_5) amenant le premier site de mise en place de connecteur (804_1, 806_1) et les sites de mise en place de composant passif (808_1-808_5) à être électriquement connectés en série, et des troisièmes traces de signal (814_1-814_5) amenant le second site de mise en place de connecteur (806_1, 804_1) et les sites de mise en place de composant passif (814_1-814_5) à être électriquement connectés en série ; et

    un connecteur (204, 304), installé sur le premier site de mise en place de connecteur.


     
    10. Dispositif électronique (1000) selon la revendication 9, caractérisé en ce que le port de sortie est électriquement connecté au premier port d'entrée, le connecteur (304) est installé sur le premier site de mise en place de connecteur (804_1) dédié au premier circuit de traitement de signal (212), et le second site de mise en place de connecteur (806_1) dédié au second circuit de traitement de signal (214) n'est pas pourvu de connecteur.
     
    11. Dispositif électronique (1200) selon la revendication 9, caractérisé en ce que le port de sortie est électriquement connecté au second port d'entrée, le connecteur (204) est installé sur le second site de mise en place de connecteur (806_1) dédié au second circuit de traitement de signal (214), et le premier site de mise en place de connecteur (804_1) dédié au premier circuit de traitement de signal (212) n'est pas pourvu de connecteur.
     
    12. Dispositif électronique (1000, 1200) selon la revendication 9, caractérisé en ce que des sites de mise en place de connecteur (1404_1-1404_4) comprennent une pluralité de premiers sites de mise en place de connecteur et une pluralité de seconds sites de mise en place de connecteur ; et la carte de circuit imprimé comprend une pluralité de groupes de sites de mise en place de composant passif (1406_1-1406 5, 1408_1-1408_5, 1410_1-1410_5) chacun disposé entre deux sites de mise en place de connecteur adjacents des sites de mise en place de connecteur.
     
    13. Dispositif électronique (1000, 1200) selon la revendication 9, caractérisé en ce que le premier circuit de traitement de signal (212) est un circuit de traitement vidéo, et le second circuit de traitement de signal (214) est un contrôleur de synchronisation.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description