Field of the Invention
[0001] The present invention relates to a method of making semiconductor devices and more
particularly to the use of photoresist in such method.
Related Art
[0002] As manufacturing of semiconductors has involved smaller and smaller dimensions the
photolithography has been moving to smaller and smaller wavelengths. The light provided
at these reduced wavelengths has resulted in the need for different photoresists.
This has been caused not just by the change in character of the light due to wavelength
but also the reduced intensity of the light. With these required changes in the photoresist,
the photoresists have also changed in their composition and thus in their response
to etchants. One of the adverse effects has typically been that the photoresist etches
more rapidly than previous photoresists. For example at 248 nanometers the ratio of
etch rates for polysilicon to photoresist was about 3 to 1. For photoresists useful
at 193 nanometers this ratio has been significantly reduced to about 1.5 to 1. Increasing
the thickness of the photoresist is undesirable due to issues relating to depth of
focus. Another adverse characteristic is that during the etch process the photoresist,
for small dimensions, can even collapse during the thinning that inherently occurs
during the etch. This collapsing issue is believed to be due to the reduced hardness
of the photoresist used for lower wavelengths. For example, the Young's modulus, which
is a typical measure of hardness, is about 40 % less for a common 193 nanometer photoresist
than for a common 248 nanometer photoresist.
[0003] US 2002/0142607 A1 discloses a method of forming a semiconductor device comprising: trimming a patterned
photoresist overlying a substrate, and fluorinating the exposed surfaces of said layer
by exposing said layer to a fluorine-based plasma.
[0004] Thus, there is a need for a semiconductor manufacturing process that alleviates or
reduces one or more of these problems.
Brief Description of the Drawings
[0005] The present invention is illustrated by way of example and not limited by the accompanying
figures, in which like references indicate similar elements, and in which:
FIG. 1 is a cross section of a semiconductor device at a stage in processing according
to the prior art;
FIG. 2 is a cross section of the semiconductor device of FIG. 1 at a subsequent stage
in processing useful according to the prior art;
FIG. 3 is a cross section of the semiconductor device of FIG. 2 at a subsequent stage
according to the prior art;
FIG. 4 is a top view of the semiconductor device of FIG. 3;
FIG. 5 is a cross section of the semiconductor device of FIG. 2 at a subsequent stage
in processing according to an embodiment of the invention;
FIG. 6 is a cross section of the semiconductor device of FIG. 5 at a subsequent stage
in processing according to the embodiment of the invention;
FIG. 7 is a cross section of the semiconductor device of FIG. 6 at a subsequent stage
in processing according to the embodiment of the invention FIG. 8 is a top view of
the semiconductor device of FIG. 7;
FIG. 9 is a cross section of the semiconductor device of FIGs. 7 and 8 at a subsequent
stage in processing according to the embodiment of the invention; and
FIG. 10 is a cross section of the semiconductor device of FIG. 9 at a subsequent stage
in processing according to the embodiment of the invention.
[0006] Skilled artisans appreciate that elements in the figures are illustrated for simplicity
and clarity and have not necessarily been drawn to scale. For example, the dimensions
of some of the elements in the figures may be exaggerated relative to other elements
to help improve the understanding of the embodiments of the present invention.
Detailed Description of the Drawings
[0007] In one aspect, a semiconductor device is made by patterning a conductive layer for
forming gates of transistors. The process for forming the gates has a step of patterning
photoresist that overlies the conductive layer. The patterned photoresist is trimmed
so that its width is reduced. Molecular fluorine F
2, is applied to the trimmed photoresist to increase its hardness and its selectivity
to the conductive layer. Using the trimmed and fluorinated photoresist as a mask,
the conductive layer is etched to form conductive features useful as gates. Transistors
are formed in which the conductive pillars are gates. This is better understood with
reference to the drawings and the following description.
[0008] Shown in FIG. 1 is a semiconductor device 10 comprising a substrate 12, a dielectric
14 over substrate 12, a layer 16, a photoresist feature 18, a photoresist feature
20, and a photoresist feature 22. Substrate 12 has a semiconductor layer below dielectric
14 that is useful for forming sources and drains. Substrate 12 may be a SOI substrate
in which a dielectric layer is below the semiconductor layer. Layer 16 is polysilicon
in this example, but could be another material, especially a conductive material such
as a metal. Further, other layers that are not shown may also be included. For example
an antireflective coating (ARC) may be on layer 16 and thus between layer 16 and photoresist
features 18, 20, and 22. Photoresist features 18-22 are formed of a commercially available
193 nanometer photoresist material that contains hydrogen. Photoresist features 18-22
may have minimum dimensions such as 100 nanometers for a 193 nanometer technology.
[0009] Shown in FIG. 2 is device 10 after a trim step in which photoresist features 18-22
are reduced in width to about 40% of the original width so that the resulting width
is about 40 nanometers for each one. This trimming is achieved with an isotropic etch
process that is preferably a dry isotropic etch. It is desirable for the lateral etch
rate to be relatively high but that is difficult compared to the etch rate that reduces
the height of photoresist features 18-22. The height of photoresist features 18-22
may actually be reduced more than the width. These photoresist features 18-22 as trimmed
in FIG. 2 are intended to be the masks for formation of gates of transistors.
[0010] Shown in FIG. 3 is a partial etch of layer 16 using photoresist features 18-22 as
a mask. The partial etch as shown is about one third of the way through layer 16 showing
portions of intended gates 36, 38, and 40 formed in layer 16. A common result is that
the photoresist features either fall over or are deformed. Photoresist piece 30 is
a result of photoresist feature 18 falling over during etching. Deformed photoresist
features 32 and 34 are formed from photoresist features 20 and 22, respectively, under
etching conditions. Exemplary etch conditions for layer 16 being polysilicon are plasma
containing chlorine, hydrogen bromine, oxygen, and argon with the pressure below one
hundred millitorr, the temperature in the range of 30 to 100 degrees Celsius, flow
rates for the various gases in the range of 10-200 SCCM, source power in the range
of 200-2000 watts, and bias power in the range of 0-200 watts. The deformed photoresist
features are likely also to fall over in continued processing and even if that does
not happen they will shadow etching of layer 16. Collapsed photoresist feature 30
blocks etching in a much wider area than is desired but also is so thin that it will
be completely etched through so that the polysilicon is etched where a gate is to
be formed. This is a location of defect that cannot be repaired and would cause a
failure that would prevent the device from operating properly.
[0011] Shown in FIG. 4 is a top view of device 10 of FIG. 3. This shows that photoresist
features 30, 32, and 34 have a low frequency and a high frequency variation that negatively
impacts the utility of these features. A variation 40 in the edge of feature 30 in
an area where it has not fallen over shows the magnitude of the effect of the low
frequency variation. A magnitude of 20 nanometers for variation 40 is not unusual.
The high frequency variation can often be 8 nanometers. These high frequency and low
frequency variations are preferably as low as possible.
[0012] Shown in FIG. 5 is a preferred alternative of fluorinating photoresist features 18-22
according to the invention prior to beginning the etch of layer 16 using a fluorine
source 52.
[0013] Fluorine source 52 provides fluorine in the form F
2 (molecular fluorine). This transforms the character of photoresist features 18, 20,
and 22 to be fluorinated photoresist features 54, 56, and 58, respectively, as shown
in FIG. 6 in semiconductor device 50. Molecular fluorine is preferred to atomic fluorine,
F, because it will not just react at the surface of photoresist features 18-22 but
also diffuse into the interior before reacting. With photoresist features 18-22 being
so thin, the resulting fluorinated photoresist features 54-58 have fluorine throughout.
The fluorine is applied preferably as molecular fluorine gas diluted in nitrogen.
The temperature is preferably 30 degrees Celsius. Alternatively an effective temperature
range is may be 10 to 40 degrees Celsius. Other temperatures may also be effective
but deleterious effects have been found at higher temperatures such as 70 degrees
Celsius. The fluorine concentration is about 1%. This concentration can be altered.
Lower concentration will increase the time required. Ten minutes has been found to
be effective for the 1% concentration. The pressure is preferably atmospheric but
there may be advantages of reduced pressure such as being able to use the same chamber,
or at least the same tool, in which the layer of polysilicon is etched. If the pressure
is reduced, the initial fluorine concentration needs to increase proportionally to
keep the processing time the same. Typically the whole tool is kept below atmospheric
pressure. The fluorine is believed to have the effect of replacing hydrogen atoms
so that fluorinated features 54-58 not only have more fluorine than photoresist features
18-22 but also less hydrogen. This has the effect of reducing the etch rate and increasing
the stiffness of fluorinated photoresist features 54-58. After this fluorination step,
the etching of layer 16 is performed.
[0014] Shown in FIG. 7 is semiconductor device 50 after a partial etch of layer 16 under
the same time and conditions as the etch of semiconductor device 10 shown in FIGs.
3 and 4. With the reduced etch rate and increased stiffness of fluorinated photoresist
features 54-58, these features 54-58 do not collapse and retain their shape and form
portions of intended gates 60, 62, and 64 in layer 16. The amount of size reduction
is significantly less than that for photoresist features 32 and 34 as shown in FIGs.
3 and 4. Shown in FIG. 8 is a top view of semiconductor device 50 of FIG. 7. This
shows that there is improvement in high frequency and low frequency variation. These
variations are not likely to be completely eliminated but are significantly reduced.
Even a reduction of 1/3 is a significant improvement.
[0015] Shown in FIG. 9 is semiconductor device 50 after completion of the etch of layer
16. This shows the completion of the formation of gates 60, 62, and 64 from layer
16. This is the desired result for gate formation. Fluorinated photoresist portions
54-58 have substantial height remaining even after completion of the patterning of
layer 16. This provides for margin in the process and also may provide for the opportunity
to reduce the photoresist thickness and thereby increasing the photoresist process
focus budget.
[0016] Shown in FIG. 10 is semiconductor device 50 after formation of transistors 80, 82,
and 84 using gates 60, 62, and 64. Around gates 60, 62, and 64 are sidewall spacers
66, 68, and 70, respectively. Source/drain region 72 is adjacent to gate 60 on one
side, source/drain region 74 is between gates 60 and 62, source/drain region 76 is
between gates 62 and 64, and source/drain region 78 is on a side of gate 64 opposite
from source/drain region 76. Source/drain region 74 is in common for transistors 80
and 82 but may preferably be separated into two regions by an isolation region. Similarly
source/drain region is in common for transistors 82 and 84 but may be separated into
two regions by an isolation region.
[0017] Thus, it is seen that a process for using 193 nanometer photoresist can be used to
produce gates that have been trimmed to dimensions far below the resolution of the
lithography itself and that this process can be performed in a single tool. After
the photoresist has been applied, the semiconductor device can enter a single conventional
tool and be processed therein until the gates are completed.
[0018] In addition to fluorinating photoresist features after trimming, fluorinating may
also be applied prior to trimming, according to an embodiment not forming part of
the invention, especially for measurement purposes. Typically even the process of
measuring widths of 193 nanometer photoresist degrades the photoresist. Atomic fluorination
may be applied prior to trim, followed by a measurement to ensure that the beginning
width of the photoresist is as desired. If so, the trim process can begin even with
the fluorinated photoresist. Because the use of atomic fluorination only results in
an outer coating of fluorination, after the outer layer of fluorination is removed,
the trim process can continue substantially as if there had not been a fluorination
step. The fluorination can be at any stage for which a measurement is to be taken.
The fluorination can be used as a protectant so that the wafer may be able to be removed
from the tool for any variety of purposes and then be returned to the tool for continued
processing.
[0019] Also, but not forming part of the invention, another halogen, especially chlorine,
may be substituted for fluorine to achieve a similar purpose. For example, wherever
fluorine is used, chlorine may be substituted. Also, another halogen might also be
effective and then simply a halogen can be substituted for fluorine. In such case
the process of treating a photoresist feature with halogen to replace hydrogen atoms
with halogen atoms can be considered to be halogenation of the photoresist feature.
1. A method for forming a semiconductor device using a substrate, comprising;
providing a layer (16) to be patterned overlying the substrate;
providing a patterned photoresist layer (18, 20, 22) overlying the layer to be patterned,
the patterned photoresist layer having a minimum dimension;
trimming the patterned photoresist layer (24, 26, 28);
fluorinating the trimmed patterned photoresist layer by applying molecular fluorine
gas to the trimmed patterned photoresist layer (24, 26, 28) to change a property of
the photoresist layer (54, 56, 58) to be more resistant to a subsequent etch processing;
and
transferring the pattern of the trimmed patterned photoresist layer (54, 56, 58) into
the layer to be patterned.
2. The method of claim 1, wherein the layer to be patterned includes a stack of layers.
3. The method of claim 2, wherein the stack of layers includes a sacrificial layer overlying
an underlying layer to be patterned,
4. The method of claim 1, wherein the trimming includes reducing the minimum dimension
via at least one of mechanical and chemical processing.
5. The method of claim 4, further mechanical processing includes at least one of reactive
ionic etching (RIE) and ionic bombardment etching.
6. The method of claim 4, wherein the chemical processing includes reacting with at least
oxygen.
7. The method of claim 4, wherein the minimum dimension is reduced by up to 80 percent
of the minimum dimension.
8. The method of claim 4
wherein the minimum dimension is on the order of 100 nanometers and wherein by trimming,
the minimum dimension is reduced to within a range of on the order of 20-80 nanometers.
9. The method of claim 1, wherein property includes at least one of a chemical and a
physical nature,
1. Verfahren zur Bildung einer Halbleitervorrichtung unter Verwendung eines Substrats,
das umfasst:
Bereitstellung einer zu bemusternden Schicht (16), die über dem Substrat liegt;
Bereitstellung einer bemusterten Fotolackschicht (18, 20, 22), die über der zu bemusternden
Schicht liegt, wobei die bemusterte Fotolackschicht über ein Mindestmaß verfügt;
Trimmung der bemusterten Fotolackschicht (24, 26, 28);
Behandlung der getrimmten bemusterten Fotolackschicht mit Fluorid durch Zuführung
von molekularem Fluorgas auf die getrimmte bemusterte Fotolackschicht (24, 26, 28),
um eine Eigenschaft der Fotolackschicht (54, 56, 58) dahingehend zu ändern, dass sie
gegenüber einem nachfolgenden Ätzverfahren widerstandsfähiger wird; und
Übertragung des Musters der getrimmten bemusterten Fotolackschicht (54, 56, 58) in
die zu bemusternde Schicht.
2. Verfahren gemäß Anspruch 1, wobei die zu bemusternde Schicht einen Stapel von Schichten
umfasst.
3. Verfahren gemäß Anspruch 2, wobei der Stapel von Schichten eine Opferschicht umfasst,
die über einer darunter liegenden zu bemusternden Schicht liegt.
4. Verfahren gemäß Anspruch 1, wobei die Trimmung eine Verringerung des Mindestmaßes
über eine mechanische und/oder chemische Verarbeitung umfasst.
5. Verfahren gemäß Anspruch 4, wobei eine weitere mechanische Verarbeitung eine reaktive
lonenätzung (RIE) und/oder lonenbeschussätzung umfasst.
6. Verfahren gemäß Anspruch 4, wobei die chemische Verarbeitung eine Reaktion mit mindestens
Sauerstoff umfasst.
7. Verfahren gemäß Anspruch 4, wobei das Mindestmaß um bis zu 80 Prozent des Mindestmaßes
verringert wird.
8. Verfahren gemäß Anspruch 4, wobei das Mindestmaß die Größenordnung von 100 Nanometern
aufweist und wobei das Mindestmaß durch Trimmung auf einen Größenordnungsbereich von
20 - 80 Nanometern verringert wird.
9. Verfahren gemäß Anspruch 1, wobei eine Eigenschaft eine Eigenschaft chemischer und/oder
physischer Natur umfasst.
1. Procédé pour former un dispositif à semi-conducteurs en utilisant un substrat, comprenant
:
la fourniture d'une couche (16) à structurer recouvrant le substrat ;
la fourniture d'une couche de résine photosensible structurée (18, 20, 22) recouvrant
la couche à structurer, la couche de résine photosensible structurée ayant une dimension
minimum ;
la coupe de la couche de résine photosensible structurée (24, 26, 28) ;
la fluoration de la couche de résine photosensible structurée coupée en appliquant
du fluor gazeux moléculaire à la couche de résine photosensible structurée (24, 26,
28) coupée pour modifier une propriété de la couche de résine photosensible (54, 56,
58) pour qu'elle soit plus résistante à un traitement de gravure suivant ; et
le transfert du motif de la couche de résine photosensible structurée (54, 56, 58)
coupée à la couche à structurer.
2. Procédé selon la revendication 1, dans lequel la couche à structurer comprend une
pile de couches.
3. Procédé selon la revendication 2, dans lequel la pile de couches comprend une couche
sacrificielle recouvrant une couche sous-jacente à structurer.
4. Procédé selon la revendication 1, dans lequel la coupe comprend la réduction de la
dimension minimum par l'intermédiaire d'au moins l'un de traitements mécaniques et
chimiques.
5. Procédé selon la revendication 4, dans lequel en outre le traitement mécanique comprend
au moins l'une d'une gravure ionique réactive (RIE) et d'une gravure par bombardement
ionique.
6. Procédé selon la revendication 4, dans lequel le traitement chimique comprend une
réaction au moins avec de l'oxygène.
7. Procédé selon la revendication 4, dans lequel la dimension minimum est réduite de
80 % au maximum de la dimension minimum.
8. Procédé selon la revendication 4, dans lequel la dimension minimum est de l'ordre
de 100 nanomètres, et dans lequel, par la coupe, la dimension minimum est réduite
dans une plage de l'ordre de 20 à 80 nanomètres.
9. Procédé selon la revendication 1, dans lequel la propriété comprend au moins l'une
d'une nature chimique et d'une nature physique.