DYNAMIC SWITCH DRIVER FOR LOW-DISTORTION PROGRAMMABLE-GAIN AMPLIFIER

Description

Field

[0001] The disclosure describes generally a programmable-gain amplifier, and more specifically a low-noise, dynamic switch driver useful in applications including, but not limited to low-distortion programmable-gain amplifiers with discrete controllable gain settings implemented with high-voltage, complementary, metal-oxide semiconductor (CMOS) switches.

Background

[0002] Low-distortion programmable-gain amplifiers have many applications. For example they are useful in processing analog audio signals where it is important to preserve the integrity of the signals. One prior art implementation of a low-distortion programmable-gain amplifier is shown in Fig. 1. An input signal, which may be AC or DC, is applied to the input V_IN. The output signal appears at the output V_OUT. In this embodiment the high-gain operational amplifier A₁ is configured as a non-inverting amplifier. This configuration is preferred for low-noise applications over the inverting configuration since the feedback network can be made low impedance to minimize its thermal noise contribution without compromising the amplifier input impedance, which may be set independently via resistor R_IN. The feedback network around operational amplifier A₁ is tapped at any one of a plurality of points by selectively controlling the corresponding electronic switch elements S₁ through S_N. These switch elements are typically each constructed of complementary metal-oxide semiconductor (CMOS) devices. Control signals (C₁ through C_N) select the desired gain by turning on the associated switch. Such an approach has the benefit that the variations in ON-resistance of electronic switches S₁ through S_N due to changes in input voltage do not affect the linearity of the output signal since no signal current flows through these switches. This minimizes distortion, so long as one and only one of electronic switches S₁ through S_N is turned on at any one moment in time.

[0003] However, the ON-resistance of each of these switches does contribute thermal noise to the total input noise of the amplifier. One way to decrease the ON-resistance of CMOS electronic switches (and thus to reduce the amplifier's input noise) is to increase the physical width of the CMOS devices which make up the switches. In an integrated circuit, however, an increase in the width of a switch results in an increased die area. Since the approach illustrated in Fig. 1 requires one switch for each desired gain setting, the necessary area taken by the switches in an integrated circuit can be a significant issue.

[0004] Another aspect of CMOS electronic switches is that modem CMOS processes often do not allow large voltages to be applied between the gate and channel (source and drain) of the switches, even for so-called "high-voltage" CMOS processes. This can limit the analog voltages which may be switched by CMOS electronic switches, thus restricting the maximum analog voltages, Vin, which can be applied at input of the switch.

[0005] Document. US 2004/119522 A1 discloses an analog switch circuit with appropriate breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an nMOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

[0006] Thus, according to an aspect, it is a problem to provide a dynamic switch driver, which has improved control capabilities of the turn-on and turn-off times of the switch, which minimises the charge injection of the switch, and which avoid breakdown of high-voltage CMOS switches in low-distortion programmable-gain amplifier applications.

Summary

[0007] In accordance with one aspect of the invention, this problem is solved by a switching circuit for switching a time-varying input signal as specified in claim 1. In accordance with another aspect of the invention, a method of switching a time varying input signal is provided as specified in claim 2. A preferred embodiment of the inventive method is subject of dependent claim 3.

[0008] Although reference is made herein to switching "AC signals", it should be understood that the term "AC signals" is not intended to be limited to signals that return to ground (with no DC component), but also include any time varying signals whose amplitude varies over time, and can include DC signals of either polarity, and signals whose amplitude can include DC components so as to include both polarities over time.

Brief Description of the Drawings

[0009] Reference is made to the attached drawings, wherein elements having the same reference character designations represent like elements throughout, and wherein:

Fig. 1 is a partial schematic, partial block diagram of a prior art implementation of a low-distortion, programmable-gain amplifier;

Fig. 2 is a partial schematic, partial block diagram of one embodiment of a more area-efficient, single-ended amplifier constructed in accordance with the teachings described in the Copending Application and further described herein;

Fig. 3 is a partial schematic, partial block diagram of a CMOS transmission gate that can be used as each of the switches shown in the Fig. 2 embodiment;

Fig. 4 is an amplitude-time graphical illustration of exemplary OFF-voltage waveforms for switch gates s_f1∼s_fn, shown in Fig. 2;

Fig. 5 is an amplitude-time graphical illustration of exemplary ON-voltage waveforms for switch gates S_F1 through S_Fn shown in Fig. 2;

Fig. 6 is an amplitude-time graphical illustration of exemplary ON-voltage waveforms for switch gates S₁ through S_N shown in Fig. 2;

Fig. 7 is an amplitude-time graphical illustration of exemplary OFF-voltage waveforms for switch gates S₁ through S_N shown in Fig. 2;

Fig. 8 is a block diagram of one embodiment of a switch driver that can be used to operate the amplifier
shown in Fig. 2;

Fig. 9 is a schematic diagram of one embodiment of an N-channel gate drive circuit that can be implemented as a part of the switch driver shown in Fig. 8 for operating the N-channel MOSFET of the CMOS transmission gate shown in Fig. 3; and

Fig. 10 is a schematic diagram of one embodiment of an P-channel gate drive circuit that can be implemented as a part of the switch driver shown in Fig. 8 for operating the P-channel MOSFET of the CMOS transmission gate shown in Fig. 3.

Detailed Description of the Drawings

[0010] In the drawings, Fig. 2 is a schematic representation of an embodiment of a more area-efficient programmable-gain amplifier

[0011] High-gain operational amplifier A₁ is configured as a non-inverting amplifier, with the input voltage V_IN being applied to the non-inverting input of the amplifier. Resistor R_IN substantially sets the amplifier input impedance. Resistors R₁ through R_N+1 are connected in series between the output of the amplifier A₁ and system ground or a reference node, and comprise a tapped resistor string that provides feedback via a series of discrete voltage dividers selected via electronic switches S₁ though S_N. Control signals C_C1 through C_CN are used to select one of a series of individual closed-loop gain settings by turning on a corresponding one of the electronic switches S₁ through S_N so as to connect a single point along the tapped resistor string to the inverting input of amplifier A1. In addition, one or more of the resistors R_F1 through R_FM modify the closed-loop gain when they are connected in parallel with resistor R₁ via electronic switches S_F1 through S_FM. Control signals C_F1 through C_FM determine the state of switches S_F1 through S_FM respectively, selectively turning one or more of them on so as to connect those resistors R_F1 through R_FM (for which the corresponding switches S_F have been turned on) in parallel with resistor R₁.

[0012] Electronic switches S₁ through S_N and S_F, and S_Fm each include a CMOS transmission gate. Such transmission gates comprise an N-channel MOS transistor and a P-channel MOS transistor in parallel, as illustrated in Fig. 3. One source-drain terminal of P-channel MOSFET M_A is connected to one source-drain terminal of N-channel MOSFET M_B. The remaining source-drain terminals of M_A and M_B are also connected together. In operation, the body connection of P-channel MOSFET M_A is connected to a voltage Vdd more positive than the maximum expected voltage on either of its source-drain terminals. The body connection of N-channel MOSFET M_B is connected to a voltage V_SS more negative than the maximum expected voltage on either of its source-drain terminals. These are often the positive and negative power supply voltages used with the integrated circuit containing one or more of these switches.

[0013] Control of the state of each transmission gate is accomplished via the gate terminals of the two MOSFETS, M_A and M_B. More specifically, when the gate of P-channel MOSFET M_A is made sufficiently negative with respect to its source-drain terminals, and the gate of N-channel MOSFET M_B is made sufficiently positive with respect to its source-drain terminals, both devices are considered to be operating in the triode region, and are characterized by a relatively low resistance between the two source-drain terminals SD₁ and SD₂. This resistance between the source-drain terminals of each device is often referred to as the ON-resistance (thereby defining the ON-state of the device), and can be approximately characterized by the following equation:

wherein µ is the mobility of the carriers in the channel,

C_OX is the gate capacitance per unit area,

W and L are the channel width and length, respectively,

V_GS is the gate-source voltage, and

V_t is the threshold voltage (the threshold voltage is that gate-source voltage above which a channel is present); and

V_eff is the effective gate-source voltage, V_GS - V_t.

[0014] From equation (1), it is clear that reducing ON-resistance requires some combination of increased carrier mobility, increased gate capacitance per unit area, increased gate width, reduced gate length, and/or increased effective gate-source voltage. Carrier mobility may be adjusted over a limited range (approximately 20:1 for electrons and 10:1 for holes at room temperature) by adjusting the doping concentration in the source and drain regions. However, increasing doping concentrations in the source and drain reduces breakdown voltage, which reduces the signal voltages that can be applied when the switch is in the OFF-state. Increasing gate capacitance per unit area requires thinner gate oxide. Reducing the gate-oxide thickness reduces the gate-source breakdown voltage, and, thus can compromise the transmission gate's ability to handle large signal voltages. As many applications for MOS switches involve DC, rather than AC, signals, high-voltage CMOS processes often trade the lower gate-source breakdown voltage that results from thinner gate oxide for the lower ON-resistance that this brings. The resulting devices exhibit lower gate-source breakdown voltages than drain-source breakdown voltages. For applications where the source stays at a fixed voltage, and the switched load is in series with the drain, the gate-source voltage can easily be limited to the V_eff required to reach the minimum ON-resistance for the device where it is no longer governed by equation (1), but is limited by other ohmic resistances. The improvements described herein allow the use of such devices for switching varying voltages that exceed the gate-source breakdown voltage.

[0015] Referring again to Fig. 2, gain-control switches S_F1 through S_FM (hereafter referred to as the "S_Fi" switches) will be exposed to signal voltages on the terminals labeled 2 and 3 corresponding to the source-drain terminals of the CMOS switch of the type shown in Fig. 3. When any of these switches is in the OFF-state, one side of the switch, labeled as terminal 3 in Fig. 2, will be at the same voltage as the output voltage, V_OUT, of amplifier A₁. The other side of the switch, labeled as terminal 2 in Fig. 2, will be at a voltage equal to a fraction of V_OUT determined by the settings of the other S_Fi switches and by the voltage division provided by the string of resistors R₁ through R_N+1. This voltage is labeled V₁ in Fig. 2.

[0016] By definition, the source terminal for the N-channel MOSFET in the CMOS switch in Fig. 3 is the terminal at the more negative potential, while the drain terminal of the N-channel MOSFET is the terminal at the more positive potential. In order to keep the N-channel MOSFET in the OFF-state, the gate voltage must be less than or equal to the source voltage. Similarly, the source terminal for the P-channel MOSFET in Fig. 3 is defined as the more positive of the two source-drain terminals, while the drain terminal of the P-channel MOSFET is the more negative of the two. To keep the P-channel MOSFET in the OFF-state, the gate terminal voltage on the P-channel MOSFET must be greater than or equal to the source voltage.

[0017] If the switch is fabricated in a process in which the gate-source breakdown voltage is equal to or greater than the source-drain voltage, common practice to turn the CMOS switch off is to connect the N-channel MOSFET gate to the most negative power supply voltage applied to the integrated circuit, and the P-channel MOSFET gate to the most positive power supply voltage applied to the integrated circuit in order to ensure that both MOSFETs stay OFF for any possible signal voltage within range of the power supplies.

[0018] However, for high-voltage CMOS processes as described above, in which the gate-source breakdown voltage is substantially less than the source-drain breakdown voltage, this practice could lead to breakdown of the gate oxide and damage to the device. In an example of one embodiment, the CMOS switch is fabricated in a high-voltage CMOS process in which the source-drain breakdown voltage of each of the N-channel and P-channel devices exceeds 40V, but the gate-source breakdown voltage for each of the devices is 20V. The typical power supply voltages utilized in the example are +15V and -15V. The signal voltages at V_IN and V_OUT can be anywhere within the range defined by these voltages. If, for example, the gate of the N-channel MOSFET were connected to -15V to turn it OFF, a voltage greater than +5V at V₁ would cause the gate-source voltage to exceed the N-channel MOSFET's maximum gate-source voltage rating. Similarly, a voltage at V₁ less the-5V would cause the gate-source voltage of the P-channel MOSFET to exceed its maximum rating.

[0019] In order to keep both MOSFETS in the OFF-state, but at the same time not violate the maximum gate source voltage, a gate-drive circuit can be used to maintain the N-channel MOSFET gate voltage at or slightly below the source voltage at all times. The source voltage for the N-channel MOSFET in the SF_i switches in Fig. 2 will be the lesser of V₁ and V_OUT. The source voltage for the P-channel MOSFET in the SF_i switches in Fig. 2 will be the greater of V₁ and V_OUT. Accordingly, the gate voltages of the N-channel MOSFETs are driven in the OFF-state with a voltage slightly below the lesser of V₁ and V_OUT, and the gates of the P-channel MOSFETs with a voltage slightly above the greater of V₁ and V_OUT, as illustrated in Fig. 4. In Fig. 4, V_OFFN is thus a gate voltage capable of maintaining the N-channel MOSFET in the OFF-state, and V_OFFP is the preferred gate voltage capable of maintaining the P-channel MOSFET in the OFF-state.

[0020] Referring again to Fig. 2, whenever any of the S_Fi switches are turned on, the source and drain voltages of both MOSFETs for that switch will be at approximately V₁. In order to maintain both MOSFETs of that switch in the ON-state, the gate-source voltage of the NMOS device must be kept sufficiently positive to provide the desired ON-resistance, and the gate-source of the PMOS device must be kept sufficiently negative for the same reason. In prior art designs that utilize low power supply voltages, this is typically done by connecting the NMOS gate to a voltage substantially equal to the positive power supply voltage, and the PMOS gate to a voltage substantially equal to the negative supply voltage.

[0021] However, in order to accommodate signal voltages that exceed the gate-source breakdown voltage, a simple connection to a voltage substantially equal to the positive or negative supply voltages is not possible. In order to prevent breakdown of the gate oxide, the NMOS device gate-source voltage is preferably kept equal to V₁ plus a sufficient positive offset to ensure low ON-resistance. Likewise, the PMOS device gate-source voltage is preferably kept equal to V₁ plus a sufficient negative offset to ensure low ON-resistance. This is illustrated in Fig. 5, which shows an example of a signal voltage V₁, and a gate voltage V_ONN applied to maintain the NMOS device in the ON-state, and a gate voltage V_ONP applied to maintain the PMOS device in the ON-state. Since the gate-source voltage of each device is kept substantially constant with changes in signal voltage, any distortion contribution due to variation in switch ON-resistance with signal voltage is minimized. In an example of one embodiment, the offset voltage between V₁ and V_ONN is approximately +9V, and the offset voltage between V₁ and V_ONP is approximately -9V.

[0022] Gain-control switches S₁ through S_N in Fig. 2 require similar protection from damaging gate-source voltages.

[0023] Switches S₁ through S_N are utilized by turning only one of these switches on at a time, which minimizes any distortion contribution from the switch due to variations in ON-resistance with signal voltage. Thus, the switch that is turned on will have input signal voltage V_IN on the source and drain of both MOSFETs, as long as amplifier A₁ is operating in its linear region. The rest of the gain-control switches S₁ through S_N will see this same voltage on the terminals 3 in Fig. 2. The terminals of these switches labeled 2 in Fig. 2 will be at a voltage equal to a fraction of V_OUT determined by the settings of the S_Fi switches and by the voltage division provided by the string of resistors R₁ through R_N+1. These voltages are labeled as V₁ through V_N in Fig. 2.

[0024] As described above for the switches S_F1 through S_FM, in one example the magnitude of the gate-source breakdown voltage of the NMOS and PMOS devices that make up switches S₁ through S_N is 20V and the typical power supply voltages for opamp A₁ are +15 V and -15 V. If the gate of each of the NMOS devices were tied to +15 V and the gate of each of the PMOS devices were tied to -15 V in order to keep the desired switches S₁ through S_N in the ON-state, input signal voltages at terminal V_IN in excess of +5 V or -5V would exceed the maximum gate-source voltage on devices in switches. Similarly as with switches S_F1 through S_FM, in order to protect against exceeding the maximum gate-source voltage, the NMOS gate-source voltage for switches S₁ through S_N is preferably kept equal to the voltage at the inverting input of operational amplifier A₁ plus a sufficient positive offset to ensure low ON-resistance. Similarly, the PMOS gate-source voltage for switches S₁ through S_N is preferably kept equal to the voltage at the inverting input of operational amplifier A₁ plus a sufficient negative offset to ensure low ON-resistance. This is illustrated in Fig. 6, which shows an example of an operational amplifier A₁ inverting input voltage, V_IN-, and a preferred gate voltage V_ONN to maintain the NMOS device in the ON-state, and a preferred gate voltage V_ONP to maintain the PMOS device in the ON-state. In one example of the illustrated embodiment, the offset voltage between V_IN-and V_ONN is approximately +9V, and the offset voltage between V_IN- and V_ONP is approximately -9V.

[0025] The MOSFETs in those switches S₁ through S_N that are turned OFF may also potentially be exposed to excessive gate-source voltages if the gates were driven to the power supply voltages to maintain the MOSFETs in the OFF-state. In particular, even at the highest gain settings (typically achieved when switch S_N in Fig. 2 is turned on), switches S₂ through S_N can be exposed to large voltage swings on both signal terminals. One way in which this can occur is if operational amplifier A₁ is of the type known in the art that includes protection from excessive differential input voltages, such as those including back-to-back diodes across their input terminals. In such case, the inverting and non-inverting inputs of operational amplifier A₁ will never be more than 1 volt apart. Thus, large input voltages at terminal V_IN will be largely reflected to the inverting input terminal. At high gain settings, such large input voltages will cause the output of operational amplifier A₁ to clip at the maximum possible output voltage, typically within a few volts or less of the supply voltages, while the high input signal level itself causes the large input voltage to appear at terminals 3 of switches S₁ through S_N. Thus, each of those switches S₁ through S_N-1 may be exposed to signal voltages that approach either of the supply voltages on both signal terminals (2 and 3).

[0026] As described above for gain-control switches S_F1 through S_FM, the preferred gate voltage for maintaining the N-channel MOSFETs in the OFF-state while not violating the maximum gate-source voltage is a voltage equal to or slightly less than the source voltage. For the N-channel MOSFETs in gain-control switches S₁ through S_N, the source voltage will be the lesser of the voltage at the inverting input of operational amplifier A₁ (V_IN-) and the voltage (V_N for switch S_N) at the other side of the switch. Similarly, the preferred gate voltage for the P-channel MOSFETs in the OFF-state will be equal to or slightly greater than the source voltage, which will be the greater of V_IN- or V_N for switch S_N. These waveforms are illustrated in Figure 7.

[0027] Fig. 8 is a partial schematic and partial block diagram illustrating one embodiment of a circuit for generating gate-control voltages for the transmission-gate of the N-channel and P-channel MOSFETs. Referring to Fig. 8, a CMOS transmission gate includes MOSFETs M_A and M_B. Signal voltages V_SD1 and V_SD2, appearing at the inputs SD1 and SD2 and applied to the source-drain terminals SD₁ and SD₂, are also buffered by unity-gain amplifiers, Buffer₁ and Buffer₂, respectively, to prevent any loading of the gain-control network (an embodiment of which is shown in Fig. 2 as including resistors R1 through RN+1 and R1 through RFM). The output of amplifier Buffer₁ is connected to the negative terminal of offset voltage source V_OS1, the positive terminal of offset voltage source V_OS2, the first input of "less-than-or-equal-to" Block₁ and the first input of "greater-than-or-equal-to" Block₂, all of which comprise the switch-driver circuit SDC. Thus, the voltage V_ONN at the positive terminal of voltage source V_OS1 will be equal to the voltage at terminal SD₁ plus a positive offset determined by the voltage provided by V_OS1. If the offset voltage V_OS1 is chosen appropriately as described above, then voltage V_ONN will be a suitable gate voltage to maintain N-channel MOSFET M_B in the ON-state in accordance with the present disclosure. Similarly, the voltage V_ONP at the negative terminal of voltage source V_OS2 will be equal to the voltage at terminal SD₁ plus a negative offset determined by the voltage provided by V_OS2. If the offset voltage V_OS2 is chosen appropriately as described above, then voltage V_ONP will be a suitable gate voltage to maintain P-channel MOSFET M_A in the ON-state.

[0028] The output of amplifier Buffer₂ is connected to the second input of "less-than-or equal-to" Block₁ and the second input of "greater-than-or-equal-to" Block₂. The output of Block₁ V_OFFN, will be a voltage equal to the more negative of the two voltages at its inputs, or the voltage at both inputs if the input voltages are equal. The output of Block₂, V_OFFP, will be a voltage equal to the more positive of the two voltages at its inputs, or the voltage at both inputs if the input voltages are equal. Thus, the voltage V_OFFN at the output of Block₁ will be equal to the more negative of the voltages at switch terminals SD₁ and SD₂, and will be a suitable gate voltage to maintain N-channel MOSFET M_B in the OFF-state. Similarly, the voltage V_OFFP at the output of Block₂ will be the more positive of the voltages at switch terminals SD₁ and SD₂, and will be a suitable gate voltage to maintain P-channel MOSFET M_A in the ON-state.

[0029] Switches SW₁ and SW₂ are representative of electronic switches that are controlled by control signal V_CONTROL. Control signal V_CONTROL preferably has two states; an "ON" state for turning MOSFETs M_A and M_B on, and an "OFF" state for turning MOSFETs M_A and M_B OFF. When control signal V_CONTROL is in the "ON" state, terminals 2 and 3 of switch SW₁ are connected, and terminals 2 and 3 of switch SW₂ are connected, applying the appropriate gate voltages V_ONN and V_ONP to MOSFETs M_B and M_A, respectively, to maintain both MOSFETs in the ON-state. When control signal V_CONTROL is in the "OFF" state, terminals 1 and 2 of switch SW₁ are connected, and terminals 1 and 2 of switch SW₂ are connected, applying the appropriate gate voltages V_OFFN and V_OFFP to MOSFETs M_B and M_A, respectively to maintain both in the OFF-state.

[0030] It should be noted that the negative terminal of offset voltage source V_OS1 and/or the positive terminal of offset voltage source V_OS2 could be alternatively connected to the output of amplifier Buffer₂ instead of the output of amplifier Buffer₁ with no loss of functionality, since, when MOSFETs M_A and M_B are on, there is little voltage difference across the terminals SD₁ and SD₂.

[0031] Figs. 9 and 10 schematically illustrate in more detail, one embodiment of switch driver circuitry of the type described herein. Fig. 9 shows a schematic diagram of circuitry for interfacing to a control signal, as well as the NMOS gate driver circuitry for the CMOS switch. Fig. 10 shows schematically the PMOS gate driver circuitry for the CMOS switch.

[0032] Referring to Fig. 9, N-channel MOSFET differential pair M₁ and M₂ provides an interface between a control voltage V_CONTROL and the gate driver circuitry via terminal V_CONTROL. Control voltage V_CONTROL is preferably a logic signal that is set to one of two levels, a high level greater than threshold voltage V_THR or a low level less than threshold voltage V_THR. When control voltage V_CONTROL is set to the high level, N-channel MOSFET M₁ is turned on and conducts substantially all of the current from current source I₁, and N-channel MOSFET M₂ is substantially OFF. When control voltage V_CONTROL is set to the low level, N-channel MOSFET M₂ conducts substantially all of the current from current source I₁, and N-channel MOSFET M₁ is substantially in an OFF- state. In this manner, control voltage V_CONTROL steers the current from current source I₁ to flow through one of either diode-connected P-channel MOSFET M₃ or M₄.

[0033] Source-drain voltage terminal V_SD1 is preferably connected to one of the two signal terminals of the CMOS switch to be controlled by the gate driver circuitry, and source-drain voltage terminal V_SD2 is preferably connected to the other of the two signal terminals of the CMOS switch to be controlled. For example referring to Fig. 3, terminal V_SD1 would preferably be connected to terminal SD₁ of the CMOS switch and V_SD2 would preferably be connected to terminal SD₂ of the CMOS switch. Terminal V_CONN is preferably connected to the gate terminal of the N-channel MOSFET in the CMOS switch to be controlled.

[0034] Referring again to Fig. 9, P-channel MOSFET M₁₁, along with diode-connected P-channel MOSFET M₉, diode-connected N-channel MOSFET M₁₀. and current source I₂ in Fig. 9 form a source-follower buffer for source-drain voltage V_SD1, such that the voltage V_ONN at the source of MOSFET M₉ is substantially given by:

where V_SG11, V_GS10, and V_SG9 are the gate-source (or source-gate) voltages of M₁₁, M₁₀, and M₉, respectively, and all are positive quantities.

[0035] The gate-source voltages are substantially constant with changes in source-drain voltageV_SD1 to the extent that current source I₂ is constant, since the gate of N-channel MOSFET M₁₂ provides negligible loading on the source of MOSFET M₉. MOSFET M₁₁ is preferably of the minimum geometry allowed by the process design rules and voltage requirements in order to minimize the capacitive loading on the voltage V_SD1. In an example of one embodiment, the value of current source I₂ is approximately 10 µA, and the nominal value of the sum of gate-source voltages of MOSFETs M₉ though M₁₁ is 9V. Thus the voltage V_ONN at the source of MOSFET M₉ will substantially equal the preferred ON-voltage for the N-channel MOSFET in the CMOS switch to be controlled, as described above.

[0036] N-channel MOSFET M₁₂ and current source I₃ act as a source-follower buffer for voltage V_ONN such that the voltage at the source of MOSFET M₁₂ is substantially equal to V_ONN - V_GS12, where V_GS12 is the gate-source voltage of MOSFET M₁₂. The preferred value for current source I₃ is equal to the value of current source I₁. When control voltage V_CONTROL is high, the current from current source I₁ is steered via MOSFETs M₁ to M₃. Further, since there is substantially no current flowing in MOSFET M₄, there is also substantially no current flowing in P-channel MOSFET M₅, N-channel MOSFET M₆, or N-channel MOSFET M₇. The gate and source terminals of MOSFET M₃ are connected to the gate and source terminals, respectively, of P-channel MOSFET M₈, forming a current mirror. MOSFET M₈ preferably has a gate width equal to one half of the gate-width of MOSFET M₃, resulting in a current equal to one half of the value of current source I₁ being sourced from the drain of M₈. The current flows through diode-connected P-channel MOSFET M₁₄, since N-channel MOSFET M₇ is turned OFF. The fact that MOSFET M₇ is turned OFF also ensures that diode-connected P-channel MOSFET M₁₇ conducts substantially no current. Under these conditions, MOSFETs M₁₂ and M₁₄ will each be operating with a source-drain current equal to one half the value of current source I₁. Since MOSFETs M₁₂ and M₁₄ are, under these conditions, operating at substantially the same current, their gate-source voltages will be substantially the same. Therefore, the voltage at terminal V_CONN will be substantially equal to the voltage at the source of MOSFET M₉ or V_ONN which, as described above, is the preferred ON voltage for the N-channel MOSFET portion of a single CMOS switch in a programmable-gain amplifier.

[0037] N-channel MOSFET M₁₃, along with current source I₄, forms a second source-follower buffer for voltage V_SD1. N-channel MOSFET M₁₆, along with current source I₅, forms a source-follower buffer for CMOS switch signal voltage V_SD2. MOSFETs M₁₃ and M₁₆ are preferably of the minimum geometry allowed by the process design rules and voltage requirements in order to minimize the capacitive loading on the voltage V_SD1 and V_SD2, respectively. Current sources I₄ and I₅ are preferably substantially the same value, each equal to 10 µA in one illustrative embodiment. The voltages at the sources of MOSFETs M₁₃ and M₁₆ will be substantially V_S13 = V_SD1 - V_GS13 and V_S16 = V_SD2 - V_GS16, respectively, where V_GS13 and V_GS16 are the gate-source voltages of MOSFETs M₁₃ and M₁₆, respectively. Since MOSFETs M₁₃ and M₁₆ operate at the same current, their gate-source voltages will be substantially equal.

[0038] P-channel MOSFETs M₁₅ and M₁₈, along with current source I₆ form a "less-than or equal-to" circuit. M₁₅ and M₁₈ are preferably identical-geometry devices. If the voltage V_S13 is substantially less than the voltage V_S16, then substantially all of the current from current source I₆ will be conducted by MOSFET M₁₅, and the voltage V_S15 at the junction of the sources of MOSFETs M₁₅ and M₁₈ will be: V_S15 = V_SD1 - V_GS13 + V_SG15, where V_SG15 is the source-gate voltage of M₁₅. If the voltage V_S16 is substantially less than the voltage V_S13, then substantially all of the current from current source I₆ will be conducted by MOSFET M₁₈, and the voltage at the junction of the sources of MOSFETs M₁₅ and M₁₈ will be:

V_S15 = V_SD2 - V_GS16 + V_SG18, where V_SG18 is the source-gate voltage of MOSFET M₁₈. Noting that the gate-source voltages of N-channel and P-channel MOSFETs are of opposite polarities, the voltage V_S15 will be the lesser of V_SD1 or V_SD2, plus an offset voltage equal to the difference between the magnitudes of the gate-source voltages of one N-channel MOSFET and one P-channel MOSFET. While it should be clear that it is possible to ensure that this offset voltage is approximately zero, this can only be done approximately, since the threshold voltages of N-channel and P-channel devices are subject to independent process variations. However, this level of accuracy is sufficient in most instances, as will be shown below.

[0039] When control voltage V_CONTROL is low, the current from current source I₁ is steered via MOSFETs M₂ to M₄. Further, since there is substantially no current flowing in MOSFET M₃, there is also substantially no current flowing in MOSFET M₈, and MOSFET M₁₄ is turned OFF. The gate and source terminals of MOSFET M₄ are connected to the gate and source terminals, respectively, of P-channel MOSFET M₅, forming a current mirror. MOSFET M₅ preferably has a gate width equal to one half of the gate-width of MOSFET M₄, resulting in a current equal to one half of the value of current source I₁ being sourced from the drain of MOSFET M₅. The current flows through diode-connected MOSFET M₆ and is mirrored to MOSFET M₇. Thus, a current equal to one half of the value of current source I₁ is sunk by MOSFET M₇, which flows through diode-connected MOSFET M₁₇. In one implementation the value of the current provided by current source I₆ is equal to the value of I₁. Thus, half of the current from source I₆ flows through MOSFET M₁₇, while the balance is available for either MOSFETs M₁₅ or M₁₈, or both, depending on the relative levels of the voltage V_SD1 and V_SD2 provided respectively at the terminals S_D1 and S_D2. The voltage at terminal V_CONN under these conditions will be substantially equal to the lesser of V_SD1 or V_SD2 plus the aforementioned offset dependent on the difference between N-channel and P-channel gate-source voltages, minus the gate-source voltage of M₁₇. The magnitude of the gate-source voltage of M₁₇ is always sufficient to ensure that the voltage at V_CONN will be slightly below the lesser of voltages V_SD1 or V_SD2, which, as described above, is one implementation of the OFF-voltage for the N-channel MOSFET portion of a single CMOS switch in a programmable-gain amplifier according to the present invention.

[0040] Fig. 10 schematically illustrates additional circuitry to create a gate drive signal for the P-channel MOSFET in the CMOS switch to be controlled. The terminals labeled V_MON and V_MOFF are intended to be connected to the identically named terminals in Fig. 9. Thus, the gate and drain terminals of MOSFETs M₃ and M₄ in Fig. 9 are connected to the gate terminals of P-channel MOSFETs M₁₉ and M₂₂ in Fig. 10, respectively. The terminals labeled V_SD1 and V_SD2 in Fig. 10 connect to the identically named terminals in Fig. 9, as well as to the signal terminals SD₁ and SD₂ of the CMOS switch to be controlled as illustrated in Fig. 3. In one implementation, terminal V_CONP is connected to the gate terminal of the P-channel MOSFET in the CMOS switch to be controlled.

[0041] N-channel MOSFET M₂₃, along with diode-connected P-channel MOSFET M₂₄, diode-connected N-channel MOSFET M₂₅, and current source I₇ in Fig. 10 form a third source-follower buffer for source-drain voltage V_SD1, such that the voltage V_ONP at the source of M₂₅ is substantially given by: V_ONP = V_SD1 - V_GS23 - V_SG24 - V_GS25, where V_GS23, V_SG24, and V_GS25 are the gate-source (or source-gate) voltages of M₂₃, M₃₄, and M₂₅, respectively, and all are positive quantities. These gate-source voltages are substantially constant with changes in source-drain voltage V_SD1 to the extent that current source I₇ is constant, since the gate of N-channel MOSFET M₂₇ provides negligible loading on the source of MOSFET M₂₅. MOSFET M₂₃ is preferably of the minimum geometry allowed by the process design rules and voltage requirements in order to minimize the capacitive loading on the voltage V_SD1. In an example of one embodiment, the value of current provided by current source I₇ is approximately 10 µA, and the nominal value of the sum of gate-source voltages of MOSFETs M₂₃ though M₂₅ is 9V. Thus, the voltage V_ONP at the source of MOSFET M₂₅ will substantially equal the preferred ON-voltage for the N-channel MOSFET in the CMOS switch to be controlled, as described above.

[0042] P-channel MOSFET M₂₇ and current source Is act as a source-follower buffer for voltage V_ONP such that the voltage at the source of MOSFET M₂₇ is substantially equal to V_ONP + V_SG27, where voltage V_SG27 is the source-gate voltage of MOSFET M₂₇. The preferred value for current source I₈ is equal to the value of current provided by current source I₁ in Fig. 9. Referring to Fig. 9, when control voltage V_CONTROL is high, the current from current source I₁ is steered via MOSFETs M₁ to M₃, and there will be substantially no current flowing in MOSFET M₄. Since the gates and drains of MOSFET M₄ (Fig. 8) and MOSFET M₂₂ (Fig. 9) are connected together, there will be substantially no current flowing in P-channel MOSFET M₂₂. Similarly, the gate and source terminals of MOSFET M₃ (Fig. 8) are connected to the gate and source terminals, respectively, of P-channel MOSFET M₁₉ (Fig. 9), forming a current mirror. MOSFET M₁₉ preferably has a gate width equal to one half of the gate-width of MOSFET M₃, resulting in a current equal to one half of the value of current provided by current source I₁ being sourced from the drain of MOSFET M₁₉. Referring to Fig. 10, the current flows through diode-connected N-channel MOSFET M₂₀, which forms a current mirror with N-channel MOSFET M₂₁. Therefore the drain current of MOSFET M₂₁ will be substantially equal to one half of the drain current of current source I₁ in Fig. 9. The drain current will flow through diode-connected P-channel MOSFET M₂₈, since (as noted above) MOSFET M₂₂ is turned OFF. The fact that MOSFET M₂₂ is turned OFF also ensures that diode-connected N-channel MOSFET M₃₂ conducts substantially no current. Under these conditions, MOSFET M₂₇ and M₂₈ will each be operating with a source-drain current equal to one half the value of current provided by current source I₁. Since MOSFETs M₂₇ and M₂₈ are, under these conditions, operating at substantially the same current level, their gate-source voltages will be substantially the same. Therefore, the voltage at terminal V_CONP will be substantially equal to the voltage at the source of MOSFET M₂₅ (or V_ONP) which, as described above, is the preferred ON-voltage for the P-channel MOSFET portion of a single CMOS switch in a programmable-gain amplifier.

[0043] P-channel MOSFET M₂₆, along with current source I₉, forms a fourth source-follower buffer for voltage V_SD1. N-channel MOSFET M₃₀, along with current source I₁₀, forms a second source-follower buffer for CMOS switch signal voltage V_SD2. MOSFETs M₂₆ and M₃₀ are preferably of the minimum geometry allowed by the process design rules and voltage requirements in order to minimize the capacitive loading on the voltages V_SD1 and V_SD2, respectively. Current sources I₉ and I₁₀ are preferably substantially the same value, each equal to 10 µA in one example of an embodiment. The voltages at the sources of MOSFETs M₂₆ and M₃₀ will be substantially V_S26 = V_SD1 + V_SG26 and V_S30 = V_SD2 + V_SG30, respectively, where voltages V_SG26 and V_SG30 are the source-gate voltages of MOSFETs M₂₆ and M₃₀, respectively. Since MOSFETs M₂₆ and M₃₀ operate at the same current level, their source-gate voltages will be substantially equal. N-channel MOSFETs M₂₉ and M₃₁, along with current source I₁₁, form a "greater-than or equal-to" circuit. MOSFET M₂₉ and M₃₁ are preferably identical-geometry devices. If the voltage V_S26 is substantially greater than the voltage V_S30, then substantially all of the current from I₁₁ will be conducted by M₂₉, and the voltage V_S29 at the junction of the sources of MOSFETs M₂₉ and M₃₁ will be: V_S29 = V_SD1 + V_SG26 - V_GS29. If the voltage V_S30 is substantially greater than the voltage V_S26, then substantially all of the current from current source I₁₁ will be conducted by MOSFET M₃₁, and the voltage at the junction of the sources of MOSFETs M₂₉ and M₃₁ will be: V_S29 = V_SD2 + V_SG30 - V_GS31. Noting that the gate-source voltages of N-channel and P-channel MOSFETs are of opposite polarities, the voltage V_S29 will be the greater of either voltage V_SD1 or V_SD2, plus an offset voltage equal to the difference between the magnitudes of the gate-source voltages of one N-channel MOSFET and one P-channel MOSFET.

[0044] Referring to Fig. 9, when control voltage V_CONTROL is low, the current from current source I₁ is steered via MOSFET M₂ to M₄. Further, since there is substantially no current flowing in MOSFET M₃, there is also substantially no current flowing in MOSFET M₁₉ in Fig. 10. Therefore MOSFETs M₂₀, M₂₁, and M₂₈ in Fig. 10 are also turned OFF. The gate and source terminals of MOSFET M₄ are connected to the gate and source terminals, respectively, of P-channel MOSFET M₂₂ in Fig. 10, forming a current mirror. MOSFET M₂₂ preferably has a gate width equal to one half of the gate-width of MOSFET M₄, resulting in a current equal to one half of the value of current source I₁ being sourced from the drain of MOSFET M₂₂, which flows through diode-connected MOSFET M₃₂. The value of current source I₁₁ is preferably equal to the value of the current provided by current source I₁. Thus, half of the current from current source I₁₁ flows through MOSFET M₃₂, while the balance is available for either MOSFETs M₂₉ or M₃₁, or both, depending on the relative levels of the voltages V_SD1 and V_SD2. The voltage at terminal V_CONP under these conditions will be substantially equal to the greater of the two voltages V_SD1 and V_SD2, plus the aforementioned offset dependent on the difference between N-channel and P-channel gate-source voltages, plus the gate-source voltage of MOSFET M₃₂. The magnitude of the gate-source voltage of MOSFET M₃₂ is always sufficient to ensure that the voltage V_CONP will be slightly above the greater of the voltages V_SD1 and V_SD2, which, as described above, is the preferred OFF voltage for the P-channel MOSFET portion of a single CMOS switch in a programmable-gain amplifier according to the present invention.

[0045] An additional advantage of this architecture is the ability to control the turn-on and turn-off times of the CMOS switches in the programmable-gain amplifier. In audio applications in particular, fast voltage transitions on the gates of the MOSFETs making up the switches can be capacitively coupled to the channels via the gate-to-channel capacitance, resulting in audible "clicks" during gain transitions. This phenomenon, sometimes referred to as "charge injection," can be minimized by choosing geometries for the N-channel and P-channel devices that make up the switch that result in matched gate-channel capacitances between the N-channel and P-channel devices. (In this approach, the gate of each device is driven from an opposite-moving signal, so that the two signals inject equal and opposite charge into the signal path, which theoretically cancel each other out.) However, this approach is almost never completely successful in eliminating audible clicks when the gates are driven with very fast rise times. Thus, providing a voltage ramp with a predetermined rate of change between the ON-voltage and OFF-voltage to the gates of the MOSFETs in the switch is a desirable characteristic for the gate drive circuitry of a programmable gain amplifier for audio applications.

[0046] Referring to Fig. 9, when a fast low-to-high transition in the voltage V_CONTROL is applied to the V_CONTROL terminal, (a) the current from current source I₁ is steered from MOSFETs M₄ to M₃, (b) MOSFET M₁₇ is turned OFF, and (c) MOSFET M₈ is turned ON. This current steering occurs very quickly as all of the relevant nodes are relatively low-impedance. However, when MOSFET M₈ turns ON, its drain current will not immediately flow through MOSFET M₁₄, but must first charge any load capacitance connected to the V_CONN terminal. Preferably, the primary load capacitance on this node is the gate-to-channel capacitance of the N-channel device in the CMOS switch. This can be quite significant, as the geometries required for the low-on resistance switches needed in a low-noise programmable-gain amplifier are very large compared with the geometries of the devices in the gate drive circuitry. By scaling the value of current source I₁, and with it the values of current sources I₃ and I₆ in proportion, the rate of change between the OFF and ON-states of the N-channel device in the switch can be controlled.

[0047] Similarly, when a fast high-to-low transition in V_CONTROL is applied, MOSFET M₈ turns OFF and MOSFET M₇ turns on very quickly. The current sunk by MOSFET M₇ charges the load capacitance (not shown) on the V_CONN terminal, providing a controlled ramp between the ON and OFF-states of the switch. It should be clear to those skilled in the art that the drive circuitry for the P-channel MOSFET in the switch, shown in Fig. 10, will behave in a similar fashion as that for the N-channel MOSFET.

[0048] In a preferred embodiment, the geometries of the CMOS switches are scaled in size to suit the requirements for noise and distortion performance required of the analog gain amplifier at its various programmable gains. Typically, gain-control switches S₁ through S_N shown in Fig. 2 would be scaled such that the switches that activate the highest gain setting would have the lowest ON-resistance, and thus be the widest switches. For instance, in Fig. 2, gain control switch S_N would be the widest and switch S₁ would be the narrowest. Gain-control switches SF₁ through SF_M would preferably be scaled such that the ON-resistance of each would be chosen to have negligible compared to its associated series resistor R_F1 through R_FM. Once these geometries are chosen, the values of I₁, I₃, I₆, I₈, and I₁₁ of the corresponding current sources may be chosen for each of the individual gate drive circuits to provide the same ramp rate for gate voltage transitions for all switches. Larger switches, which have larger capacitance, would have larger values for currents I₁, I₃, I₆, I₈ and I₁₁, while smaller switches, which have smaller capacitances, would have smaller values for currents I₁, I₃, I₆, I₈, and I₁₁. In one example, these currents ranged from 1 µA to 16 µA to achieve an approximately 20 µsec transition time between ON and OFF-states for all switches.

[0049] Alternatively to scaling the value of I₁ and other currents proportionately for each geometry of switch, the values of current I₁ and its proportionate other currents could be constant for all drive circuits, and the ratio of the widths of MOSFET M₃ to M₈, as well as MOSFETs M₁₉, M₂₀, and M₂₁, and M₄ to M₅, M₆, M₇, and M₂₂, could be scaled inversely to the width of the devices in the associated switch to achieve similar results. Further, scaling the ratio of the width of MOSFETs M₇ to M₈ and MOSFETs M₂₁ to M₂₂ can be done if different rates of change of gate drive voltage for ON-to-OFF and OFF-to-ON transitions are desired.

[0050] It should be clear that the general approach described herein can be applied to other programmable-gain amplifier and/or switching topologies.

[0051] It may also be employed for other programmable-gain amplifier topologies, and for simple switching topologies, where low distortion, low noise, and high-voltage capability are desired. Further, changes in the types of semiconductor devices employed may be made.

[0052] It should be noted that although the MOSFETs M_A and M_B of the switch shown in Figs. 3 is described as having a source and drain, it should be appreciated that in the context that these devices are being used (as switches with time varying signals applied), which terminal of each MOSFET is the source and which is the drain switches as the signal changes polarity. In one embodiment the MOSFETs are physically symmetrical devices, and the bias conditions distinguish and therefore determine which terminal is functioning as the source and which is functioning as the drain. For N-channel devices, the terminal that is at the lower potential (with respect to the gate) is the source and the terminal with the higher potential is the drain. The opposite is true for the P-channel device. So the gate drive circuit maintains the proper "gate-source voltage" with respect to the correct terminal. In the implementation of Fig. 8, the gate drive circuit maintains the proper "gate-source voltage" as a function of the outputs of the "less-than-or-equal-to" Block₁ and the "greater-than-or-equal-to" Block₂ of the SDC. Accordingly, it should be understood that each MOSFET is described as including two source-drain terminals because each terminal is capable of operating as either depending on how the MOSFET is biased.

Claims

1. A switching circuit for switching a time-varying input signal, the switching circuit comprising:

at least one switch (SC1-SCN, SF1-SFM), each respective switch (SC1-SCN, SF1-SFM) including a n-channel MOSFET (M_B) and a p-channel MOSFET (M_A), each having a gate configured to receive a drive signal (CN) to change the ON/OFF state of each MOSFET (M_A, M_B) of the respective switch (SC1-SCN, SF1-SFM), wherein the n-channel MOSFET (M_B) and the p-channel MOSFET (M_A) each include a source and a drain terminal, wherein the n-channel MOSFET (M_B) and the p-channel MOSFET (M_A) are connected in parallel at their respective source and drain terminals thereby forming two switch terminals (SD1, SD2) of said respective switch (SC1-SCN, SF1-SFM); and

a drive circuit (SDC) configured and arranged so as to selectively apply a pair of drive signals (V_CONN, V_CONP) to the gates of the n-channel MOSFET (M_B) and the p-channel MOSFET (M_A) of each of said switches (SC1-SCN, SF1-SFM), respectively, so as to change the ON/OFF state of the at least one switch (SC1-SCN, SF1-SFM) and to keep the gate-source voltages of each of said MOSFETs (M_A, M_B) within the gate-source breakdown limit of each of said MOSFETs (M_A, M_B), the drive circuit (SDC) being configured and arranged to generate the drive signals (V_CONN, V_CONP) such that:

(a) in response to receiving an OFF control signal (V_CONTROL), the drive signals (V_CONN, V_CONP) maintain the n-channel MOSFET (M_B) gate voltage at or below the source voltage at all times and maintain the p-channel MOSFET (M_A) gate voltage at or above the source voltage at all times; and

(b) in response to receiving an ON control signal (V_CONTROL), the drive signals (V_CONN, V_CONP) maintain the n-channel MOSFET (M_B) gate voltage above the source voltage by a constant offset voltage, supplied by a first offset voltage source (V_OS1), at all times and maintain the p-channel MOSFET (M_A) gate voltage below the source voltage by a constant offset voltage, supplied by a second offset voltage source (V_OS2), at all times;

wherein the drive circuit (SDC) comprises:

first and second electronically-controlled selector switches (SW₁, SW₂), each selector switch (SW₁, SW₂) having first and second input terminals (1, 3) and one output terminal (2) and one control terminal, wherein the control terminal is configured to receive a control signal (V_CONTROL), corresponding to the OFF and ON control signals, respectively, that determines whether the first input terminal (1) or the second input terminal (3) is electrically coupled to the output terminal (2), and wherein the control terminals of the two selector switches (SW₁, SW₂) are coupled to one another;

(a) a first buffer amplifier (Buffer₁) having an input terminal connected to a first (SD1) one of said two switch terminals (SD1, SD2),

(b) a second buffer amplifier (Buffer₂) having an input terminal connected to a second one (SD2) of said two switch terminals (SD1, SD2),

(c) a first offset voltage generator including the first offset voltage source (V_OS1) and having a negative terminal coupled to the output of the first buffer amplifier (Buffer₁), the first offset voltage generator including a positive terminal coupled to the first input terminal (3) of the first electronically controlled selector switch (SW₁), and

(d) a second offset voltage generator including the second offset voltage source (V_OS2) and having a positive terminal coupled to the output terminal of the first buffer amplifier (Buffer₁), and a negative terminal coupled to the first input terminal (3) of the second electronically controlled selector switch (SW₂);

a less-than-or-equal-to circuit (Block₁) including a first input terminal (In1) for receiving a first input signal, and second input terminal (In2) for receiving a second input signal, and an output terminal (Out) for producing an output signal proportional to the more negative of the first and the second input signals; and

a greater-than-or-equal-to circuit (Block₂) including a first input terminal (In1) for receiving said first input signal, and second input terminal (In2) for receiving said second input signal, an output terminal (Out) for producing an output signal proportional to the more positive of the third and the fourth input signals;

wherein the output terminal of the first buffer amplifier (Buffer₁) is coupled to the first input terminal (In1) of the less-than-or-equal-to circuit (Block₁) and to the first input terminal (In1) of the greater-than-or-equal-to circuit (Block₂), the output terminal of the second buffer amplifier is coupled to the second input terminal (In2) of the less-than-or-equal-to circuit (Block₁) and to the second input terminal (In2) of the greater-than-or-equal-to circuit (Block₂), the output terminal (Out) of the less-than-or-equal-to circuit (Block₁) is coupled to the second input terminal (1) of the first electronically controlled selector switch (SW₁), and the output terminal (Out) of the greater-than-or-equal-to circuit (Block₂) is coupled to the second input terminal (1) of the second electronically controlled selector switch (SW₂), wherein when the ON control signal (V_CONTROL) is applied to the two selector switches (SW₁, SW₂), the offset voltage produced by the first offset voltage generator added to the output signal from the first buffer amplifier (Buffer₁) is coupled to the gate of the n-channel MOSFET (M_B) of the at least one switch (SC1-SCN, SF1-SFM) and the offset voltage produced by the second offset voltage generator subtracted from the output signal from the first buffer amplifier (Buffer₁) is coupled to the gate of the p-channel MOSFET (M_A) of the at least one switch (SC1-SCN, SF1-SFM) and when the OFF control signal (V_CONTROL) is applied to the two selector switches (SW₁, SW₂), the more negative of the outputs of the two buffer amplifiers (Buffer₁, Buffer₂) is coupled to the gate of the n-channel MOSFET (M_B) and the more positive of the outputs from the two buffer amplifiers (Buffer₁, Buffer₂) is coupled to the p-channel MOSFET (M_A) of the at least one switch (SC1-SCN, SF1-SFM).

2. A method of switching a time-varying input signal using at least one switch (SC1-SCN, SF1-SFM), each respective switch (SC1-SCN, SF1-SFM) including a n-channel MOSFET (M_B) and a p-channel MOSFET (M_A), each having a gate configured to receive a drive signal (CN) to change the ON/OFF state of each MOSFET (M_A, M_B) of the respective switch (SC1-SCN, SF1-SFM), wherein the n-channel MOSFET(M_B) and the p-channel MOSFET (M_A) each include a source and drain terminal, wherein the n-channel MOSFET (M_B) and the p-channel MOSFET (M_A) are connected in parallel at their respective source and drain terminals to form a coupled MOSFET pair (M_A, M_B), the method comprising:

selectively applying a pair of drive signals (V_CONN, V_CONP) to the gates of the n-channel MOSFET (M_B) and the p-channel MOSFET (M_A);

changing an ON/OFF state of the at least one switch (SC1-SCN, SF1-SFM) and keeping the gate-source voltages of each MOSFET (M_A, M_B) within the gate-source breakdown limit of each MOSFET (M_A, M_B) by generating the drive signals (V_CONN, V_CONP) such that:

(a) in response to receiving an OFF control signal (V_CONTROL), the drive signals (V_CONN, V_CONP) maintain the n-channel MOSFET (M_B) gate voltage at or below the source voltage at all times and maintain the p-channel MOSFET (M_A) gate voltage at or above the source voltage at all times; and

(b) in response to receiving an ON control signal (V_CONTROL), the drive signals (V_CONN, V_CONP) maintain the n-channel MOSFET (M_B) gate voltage above the source voltage by a constant offset voltage, supplied by a first offset voltage source (V_OS1), at all times and maintain the p-channel MOSFET (M_A) gate voltage below the source voltage by a constant offset voltage, supplied by a second offset voltage source (V_OS2), at all times, the method further including:

receiving a control signal (V_CONTROL) corresponding to the OFF and ON control signals at respective control terminals of a first and a second electronically-controlled selector switch (SW₁, SW₂), the control signal (V_CONTROL) determining whether a first input terminal (1) of the first and second selector switches (SW₁, SW₂) or a second input terminal (3) of the first and second selector switches (SW₁, SW₂) is electrically coupled to an output terminal (2) of the respective selector switch (SW₁, SW₂);

buffering a first signal voltage (V_SD1) appearing at a first one of the source or drain terminals of the coupled MOSFET pair (M_A, M_B) thereby generating a first buffered signal;

buffering a second signal voltage (V_SD2) appearing at a second one of the source or drain terminals of the coupled MOSFET pair (M_A, M_B) thereby generating a second buffered signal;

generating a first offset voltage and applying the first offset voltage plus the first buffered signal to the second input terminal (3) of the first selector switch (SW₁);

generating a second offset voltage and applying the second offset voltage minus the second buffered signal to the second input terminal (3) of the second selector switch (SW₂);

producing a first output signal proportional to the more negative of the first buffered signal and the second buffered signal and applying the first output signal to the first input terminal (1) of the first selector switch (SW₁);

producing a second output signal proportional to the more positive of the first buffered signal and the second buffered signal and applying the second output signal to the first input terminal (1) of the second selector switch (SW₂); and

electrically coupling the first input terminal (1) of the first and second selector switches (SW₁, SW₂) or the second input terminal of the first and second selector switches (SW₁, SW₂) to the output terminal (2) of the respective selector switch (SW₁, SW₂) in accordance with the received control signal (V_CONTROL).

3. A method according to claim 2, wherein the transition of the drive signal (C_N) of the at least one switch (SC1-SCN, SF1-SFM) between an ON and OFF state occurs at a predetermined rate.

Ansprüche

1. Schaltkreis zum Schalten eines zeitvariablen Eingangssignals, wobei der Schaltkreis umfasst:

mindestens einen Schalter (SC1-SCN, SF1-SFM), wobei jeder Schalter (SC1-SCN, SF1-SFM) jeweils einen n-Kanal MOSFET (M_B) und einen p-Kanal MOSFET (M_A) umfasst, die jeweils ein Gate haben, welches dafür konfiguriert ist, ein Steuersignal (CN) zum Ändern des EIN/AUS-Zustands jedes MOSFET (M_A, M_B) des jeweiligen Schalters (SC1-SCN, SF1-SFM) zu ändern, wobei der n-Kanal MOSFET (M_B) und der p-Kanal MOSFET (M_A) jeweils einen Source- und einen Drain-Anschluss enthalten, wobei der n-Kanal MOSFET (M_B) und der p-Kanal MOSFET (M_A) an ihren jeweiligen Source- und Drain-Anschlüssen parallel geschaltet sind, wodurch sie zwei Schalteranschlüsse (SD1, SD2) des jeweiligen Schalters (SC1-SCN, SF1-SFM) bilden; und

eine Steuerschaltung (SDC), welche so konfiguriert und angeordnet ist, dass sie wahlweise zwei Steuersignale (V_CONN, V_CONP) jeweils den Gates des n-Kanal MOSFET (M_B) und des p-Kanal MOSFET (M_A) jedes der Schalter (SC1-SCN, SF1-SFM) zuführt, um den EIN/AUS-Zustand des mindestens einen Schalters (SC1-SCN, SF1-SFM) zu ändern und die Gate-Source-Spannungen jedes der MOSFETs (M_A, M_B) innerhalb der Gate-Source-Durchbruch-Grenze jedes der MOSFESTs (M_A, M_B) zu halten, wobei die Steuerschaltung (SDC) so konfiguriert und angeordnet ist, dass sie die Steuersignale (V_CONN, V_CONP) derart erzeugt, dass:

(a) auf den Empfang eines AUS-Steuersignals (V_CONTROL) hin, die Steuersignale (V_CONN, V_CONP) die Gate-Spannung des n-Kanal MOSFET (M_B) jederzeit auf oder unter der Source-Spannung halten und die Gate-Spannung des p-Kanal MOSFET (M_A) jederzeit auf oder unter der Source-Spannung halten; und

(b) auf den Empfang eines EIN-Steuersignals (V_CONTROL) hin, die Steuersignale (V_CONN, V_CONP) die Gate-Spannung des n-Kanal MOSFET (M_B) durch eine konstante Versatz-Spannung, welche durch eine erste Versatzspannungsquelle (V_OS1) zugeführt wird, jederzeit oberhalb der Source-Spannung halten, und die Gate-Spannung des p-Kanal MOSFET (B_A) durch eine konstante Versatz-Spannung, welche durch eine zweite Versatzspannungsquelle (V_OS2) zugeführt wird, jederzeit unterhalb der Source-Spannung halten;

wobei die Steuerschaltung (SDC) umfasst:

einen ersten und einen zweiten elektronisch gesteuerten Wahlschalter (SW₁, SW₂), wobei jeder Wahlschalter (SW₁, SW₂) einen ersten und einen zweiten Eingangsanschluss (1, 3) und einen Ausgangsanschluss (2) und einen Steueranschluss hat, wobei der Steueranschluss dafür konfiguriert ist, ein Steuersignal (V_CONTROL) zu empfangen, welches dem AUS- oder dem EIN-Steuersignal entspricht, welches bestimmt, ob der erste Eingangsanschluss (1) oder der zweite Eingangsanschluss (3) mit dem Ausgangsanschluss (2) elektrische gekoppelt wird, und wobei die Steueranschlüsse der beiden Wahlschalter (SW₁, SW₂) miteinander gekoppelt sind;

(a) wobei ein erster Pufferverstärker (Buffer₁) einen Eingangsanschluss hat, welcher mit einem ersten (SD1) der beiden Schalteranschlüsse (SD1, SD2) verbunden ist,

(b) wobei ein zweiter Pufferverstärker (Buffer₂) einen Eingangsanschluss hat, welcher mit einem zweiten (SD2) der beiden Schalteranschlüsse (SD1, SD2) verbunden ist,

(c) wobei ein erster Versatzspannungsgenerator die erste Versatzspannungsquelle (V_OS1) enthält und einen negativen Anschluss hat, welcher mit dem Ausgang des ersten Pufferverstärkers (Buffer₁) gekoppelt ist, wobei der erste Versatzspannungsgenerator einen positiven Anschluss hat, welcher mit dem ersten Eingangsanschluss (3) des ersten elektronisch gesteuerten Wahlschalters (SW₁) gekoppelt ist, und

(d) wobei ein zweiter Versatzspannungsgenerator die zweite Versatzspannungsquelle (V_OS2) enthält und einen positiven Anschluss hat, welcher mit dem Ausgangsanschluss des ersten Pufferverstärkers (Buffer₁) gekoppelt ist, und einen negativen Anschluss hat, welcher mit dem ersten Eingangsanschluss (3) des zweiten elektronisch gesteuerten Wahlschalters (SW₂) gekoppelt ist;

eine Kleiner-Gleich-Schaltung (Block₁) mit einem ersten Eingangsanschluss (In1) zum Empfangen eines ersten Eingangssignals und einem zweiten Eingangsanschluss (In2) zum Empfangen eines zweiten Eingangssignals sowie einem Ausgangsanschluss (Out) zum Erzeugen eines Ausgangssignals, welches proportional zu dem negativeren von erstem und zweitem Eingangssignal ist; und

eine Größer-Gleich-Schaltung (Block₂) mit einem ersten Eingangsanschluss (In1) zum Empfangen des ersten Eingangssignals und einem zweiten Eingangsanschluss (In2) zum Empfangen des zweiten Eingangssignals, einem Ausgangsanschluss (Out) zum Erzeugen eines Ausgangssignals, welches proportional zu dem positiveren von drittem und viertem Eingangssignal ist;

wobei der Ausgangsanschluss des ersten Pufferverstärkers (Buffer₁) mit dem ersten Eingangsanschluss (In1) der Kleiner-Gleich-Schaltung (Block₁) und mit dem ersten Eingangsanschluss (In1) der Größer-Gleich-Schaltung (Block₂) gekoppelt ist, der Ausgangsanschluss des zweiten Pufferverstärkers (Buffer₂) mit dem zweiten Eingangsanschluss (In2) der Kleiner-Gleich-Schaltung (Block₁) und mit dem zweiten Eingangsanschluss (In2) der Größer-Gleich-Schaltung (Block₂) gekoppelt ist, der Ausgangsanschluss (Out) der Kleiner-Gleich-Schaltung (Block₁) mit dem zweiten Eingangsanschluss (1) des ersten elektronisch gesteuerten Wahlschalters (SW₁) gekoppelt ist und der Ausgangsanschluss (Out) der Größer-Gleich-Schaltung (Block₂) mit dem zweiten Eingangsanschluss (1) des zweiten elektronisch gesteuerten Wahlschalters (SW₂) gekoppelt ist, wobei, wenn den beiden Wahlschaltern (SW₁, SW₂) das EIN-Steuersignal (V_CONTROL) zugeführt wird, die durch den ersten Versatzspannungsgenerator erzeugte, zu dem Ausgangssignal von dem ersten Pufferverstärker (Buffer₁) addierte Versatzspannung an das Gate des n-Kanal MOSFET (MB) des mindestens einen Schalters (SC1-SCN, SF1-SFM) gekoppelt wird und die von dem zweiten Versatzspannungsgenerator erzeugte, von dem Ausgangssignal von dem ersten Pufferverstärker (Buffer₁) subtrahierte Versatzspannung an das Gate des p-Kanal MOSFET (M_A) des mindestens einen Schalters (SC1-SCN, SF1-SFM) gekoppelt wird, und wenn den beiden Wahlschaltern (SW₁, SW₂) das AUS-Steuersignal zugeführt wird, der negativere der Ausgänge der beiden Pufferverstärker (Buffer₁, Buffer₂) an das Gate des n-Kanal MOSFET (M_B) gekoppelt wird und der positivere der Ausgänge der beiden Pufferverstärker (Buffer₁, Buffer₂) an das Gate des p-Kanal MOSFET (M_A) des mindestens einen Schalters gekoppelt wird.

2. Verfahren zum Schalten eines zeitvariablen Eingangssignals unter Verwendung mindestens eines Schalters (SC1-SCN, SF1-SFM), wobei jeder Schalter (SC1-SCN, SF1-SFM) jeweils einen n-Kanal MOSFET (M_B) und einen p-Kanal MOSFET (M_A) umfasst, die jeweils ein Gate haben, welches dafür konfiguriert ist, ein Steuersignal (CN) zum Ändern des EIN/AUS-Zustands jedes MOSFET (M_A, M_B) des jeweiligen Schalters (SC1-SCN, SF1-SFM) zu ändern, wobei der n-Kanal MOSFET (M_B) und der p-Kanal MOSFET (M_A) jeweils einen Source- und einen Drain-Anschluss enthalten, wobei der n-Kanal MOSFET (M_B) und der p-Kanal MOSFET (M_A) an ihren jeweiligen Source- und Drain-Anschlüssen parallel geschaltet sind, um ein gekoppeltes MOSFET-Paar (M_A, M_B) zu bilden, wobei das Verfahren umfasst:

wahlweises Zuführen zweier Steuersignale (V_CONN, V_CONP) zu den Gates des n-Kanal MOSFET (M_B) und des p-Kanal MOSFET (M_A);

Ändern des EIN/AUS-Zustands des mindestens einen Schalters (SC1-SCN, SF1-SFM) und Halten der Gate-Source-Spannungen jedes der MOSFETs (M_A, M_B) innerhalb der Gate-Source-Durchbruch-Grenze jedes der MOSFESTs (M_A, M_B), durch derartiges Erzeugen der Steuersignale (V_CONN, V_CONP), dass:

(a) auf den Empfang eines AUS-Steuersignals (V_CONTROL) hin, die Steuersignale (V_CONN, V_CONP) die Gate-Spannung des n-Kanal MOSFET (M_B) jederzeit auf oder unter der Source-Spannung halten und die Gate-Spannung des p-Kanal MOSFET (M_A) jederzeit auf oder oberhalb der Source-Spannung halten; und

(b) auf den Empfang eines EIN-Steuersignals (V_CONTROL) hin, die Steuersignale (V_CONN, V_CONP) die Gate-Spannung des n-Kanal MOSFET (M_B) durch eine konstante Versatz-Spannung, welche durch eine erste Versatzspannungsquelle (V_OS1) zugeführt wird, jederzeit oberhalb der Source-Spannung halten, und die Gate-Spannung des p-Kanal MOSFET (M_A) durch eine konstante Versatz-Spannung, welche durch eine zweite Versatzspannungsquelle (V_OS2) zugeführt wird, jederzeit unterhalb der Source-Spannung halten; wobei das Verfahren ferner enthält:

Empfangen eines Steuersignals (V_CONTROL) entsprechend dem AUS- und dem EIN-Steuersignal an jeweiligen Steueranschlüssen eines ersten und eines zweiten elektronisch gesteuerten Wahlschalters (SW₁, SW₂), wobei das Steuersignal (V_CONTROL) bestimmt, ob ein erster Eingangsanschluss (1) des ersten und des zweiten Wahlschalters (SW₁, SW₂) oder ein zweiter Eingangsanschluss (3) des ersten und des zweiten Wahlschalters (SW₁, SW₂) mit einem Ausgangsanschluss (2) des jeweiligen Wahlschalters (SW₁, SW₂) elektrisch gekoppelt wird;

Puffern einer ersten Signalspannung (V_SD1), welche an einem ersten des Source- oder des Drain-Anschlusses des gekoppelten MOSFET-Paars (M_A, M_B) auftritt, wodurch ein erstes gepuffertes Signal erzeugt wird;

Puffern einer zweiten Signalspannung (V_SD2), welche an einem zweiten des Source- oder des Drain-Anschlusses des gekoppelten MOSFET-Paars (M_A, M_B) auftritt, wodurch ein zweites gepuffertes Signal erzeugt wird;

Erzeugen einer ersten Versatzspannung und Zuführen der ersten Versatzspannung zusammen mit dem ersten gepufferten Signal zu dem zweiten Eingangsanschluss (3) des ersten Wahlschalters (SW₁);

Erzeugen einer zweiten Versatzspannung und Zuführen der zweiten Versatzspannung zusammen mit dem zweiten gepufferten Signal zu dem zweiten Eingangsanschluss (3) des zweiten Wahlschalters (SW₂);

Erzeugen eines ersten Ausgangssignals proportional zu dem negativeren von erstem gepufferten Signal und zweiten gepufferten Signal und Zuführen des ersten Ausgangssignals zu dem ersten Eingangsanschluss (1) des ersten Wahlschalters (SW₁);

Erzeugen eines zweiten Ausgangssignals proportional zu dem positiveren von erstem gepufferten Signal und zweiten gepufferten Signal und Zuführen des zweiten Ausgangssignals zu dem ersten Eingangsanschluss (1) des zweiten Wahlschalters (SW₂);

elektrisches Koppeln des ersten Eingangsanschlusses (1) des ersten und des zweiten Wahlschalters (SW₁, SW₂) oder des zweiten Eingangsanschlusses des ersten und des zweiten Wahlschalters (SW₁, SW₂) mit dem Ausgangsanschluss (2) des jeweiligen Wahlschalters (SW₁, SW₂) entsprechend dem empfangenen Steuersignal (V_CONTROL).

3. Verfahren nach Anspruch 2, wobei der Übergang des Steuersignals (CN) des mindestens einen Schalters (SC1-SCN, SF1-SFM) zwischen einem EIN- und einem AUS-Zustand mit einer vorgegebenen Geschwindigkeit erfolgt.

Revendications

1. Circuit de commutation pour commuter un signal d'entrée variable dans le temps, le circuit de commutation comprenant :

au moins un commutateur (SC1-SCN, SF1-SFM), chaque commutateur respectif (SC1-SCN, SF1-SFM) incluant un MOSFET à canal n (M_B) et un MOSFET à canal p (M_A), chacun ayant une porte configurée pour recevoir un signal d'entraînement (CN) pour changer l'état allumé/éteint de chaque MOSFET (M_A, M_B) du commutateur respectif (SC1-SCN, SF1-SFM), dans lequel le MOSFET à canal n (M_B) et le MOSFET à canal p (M_A) incluent chacun une borne de source et une borne d'évacuation, dans lequel le MOSFET à canal n (M_B) et le MOSFET à canal p (M_A) sont connectés en parallèle à leurs bornes de source et d'évacuation respectives, formant de ce fait deux bornes de commutateur (SD1, SD2) dudit commutateur respectif (SC1-SCN, SF1-SFM) ; et

un circuit d'entraînement (SDC) configuré et agencé de manière à appliquer sélectivement une paire de signaux d'entraînement (V_CONN, V_CONP) aux portes du MOSFET à canal n (M_B) et du MOSFET à canal p (M_A) de chacun desdits commutateurs (SC1-SCN, SF1-SFM), respectivement, de manière à changer l'état allumé/éteint de l'au moins un commutateur (SC1-SCN, SF1-SFM) et à conserver les tensions de porte-source de chacun desdits MOSFET (M_A, M_B) au sein de la limite de claquage de porte-source de chacun desdits MOSFET (M_A, M_B), le circuit d'entraînement (SDC) étant configuré et agencé pour générer les signaux d'entraînement (V_CONN, V_CONP) de sorte que :

(a) en réponse à la réception d'un signal de commande éteint (V_CONTROL), les signaux d'entraînement (V_CONN, V_CONP) maintiennent la tension de porte du MOSFET à canal n (M_B) à ou en dessous de la tension source à tout moment et maintiennent la tension de porte du MOSFET à canal p (M_A) à ou au-dessus de la tension source à tout moment ; et

(b) en réponse à la réception d'un signal de commande allumé (V_CONTROL), les signaux d'entraînement (V_CONN, V_CONP) maintiennent la tension de porte du MOSFET à canal n (M_B) au-dessus de la tension source par une tension décalée constante, fournie par une première source de tension décalée (V_OS1), à tout moment et maintiennent la tension de porte du MOSFET à canal p (M_A) en dessous de la tension source par une tension décalée constante, fournie par une seconde source de tension décalée (V_OS2), à tout moment ;

dans lequel le circuit d'entraînement (SDC) comprend :

des premier et second commutateurs de sélection à commande électronique (SW₁, SW₂), chaque commutateur de sélection (SW₁, SW₂) ayant des première et seconde bornes d'entrée (1, 3) et une borne de sortie (2) et une borne de commande, dans lequel la borne de commande est configurée pour recevoir un signal de commande (V_CONTROL) correspondant aux signaux de commande éteint et allumé, respectivement, qui détermine si la première borne d'entrée (1) ou la seconde borne d'entrée (3) est électriquement couplée à la borne de sortie (2), et dans lequel les bornes de commande des deux commutateurs de sélection (SW₁, SW₂) sont couplées l'une à l'autre ;

(a) un premier amplificateur tampon (Buffer₁) ayant une borne d'entrée connectée à une première (SD1) desdites deux bornes de commutateur (SD1, SD2),

(b) un second amplificateur tampon (Buffer₂) ayant une borne d'entrée connectée à une seconde (SD2) desdites deux bornes de commutateur (SD1, SD2),

(c) un premier générateur de tension décalée incluant la première source de tension décalée (V_OS1) et ayant une borne négative couplée à la sortie du premier amplificateur tampon (Buffer₁), le premier générateur de tension décalée incluant une borne positive couplée à la première borne d'entrée (3) du premier commutateur de sélection à commande électronique (SW₁), et

(d) un second générateur de tension décalée incluant la seconde source de tension décalée (V_OS2) et ayant une borne positive couplée à la borne de sortie du premier amplificateur tampon (Buffer₁) et une borne négative couplée à la première borne d'entrée (3) du second commutateur de sélection à commande électronique (SW₂) ;

un circuit inférieur ou égal à (Block₁) incluant une première borne d'entrée (In1) pour recevoir un premier signal d'entrée et une seconde borne d'entrée (In2) pour recevoir un second signal d'entrée, et une borne de sortie (Out) pour produire un signal de sortie proportionnel au plus négatif des premier et second signaux d'entrée ; et

un circuit supérieur ou égal à (Block₂) incluant une première borne d'entrée (In1) pour recevoir ledit premier signal d'entrée et une seconde borne d'entrée (In2) pour recevoir ledit second signal d'entrée, une borne de sortie (Out) pour produire un signal de sortie proportionnel au plus positif des troisième et quatrième signaux d'entrée ;

dans lequel la borne de sortie du premier amplificateur tampon (Buffer₁) est couplée à la première borne d'entrée (In1) du circuit inférieur ou égal à (Block₁) et à la première borne d'entrée (In1) du circuit supérieur ou égal à (Block₂), la borne de sortie du second amplificateur tampon est couplée à la seconde borne d'entrée (In2) du circuit inférieur ou égal à (Block₁) et à la seconde borne d'entrée (In2) du circuit supérieur ou égal à (Block₂), la borne de sortie (Out) du circuit inférieur ou égal à (Block₁) est couplée à la seconde borne d'entrée (1) du premier commutateur de sélection à commande électronique (SW₁), et la borne de sortie (Out) du circuit supérieur ou égal à (Block₂) est couplée à la seconde borne d'entrée (1) du second commutateur de sélection à commande électronique (SW₂), dans lequel lorsque le signal de commande allumé (V_CONTROL) est appliqué aux deux commutateurs de sélection (SW₁, SW₂), la tension décalée produite par le premier générateur de tension décalée ajoutée au signal de sortie provenant du premier amplificateur tampon (Buffer₁) est couplée à la porte du MOSFET à canal n (M_B) de l'au moins un commutateur (SC1-SCN, SF1-SFM) et la tension décalée produite par le second générateur de tension décalée soustraite du signal de sortie provenant du premier amplificateur tampon (Buffer₁) est couplée à la porte du MOSFET à canal p (M_A) de l'au moins un commutateur (SC1-SCN, SF1-SFM), et lorsque le signal de commande éteint (V_CONTROL) est appliqué aux deux commutateurs de sélection (SW₁, SW₂), la plus négative des sorties des deux amplificateurs tampons (Buffer₁, Buffer₂) est couplée à la porte du MOSFET à canal n (M_B) et la plus positive des sorties des deux amplificateurs tampons (Buffer₁, Buffer₂) est couplée au MOSFET à canal p (M_A) de l'au moins un commutateur (SC1-SCN, SF1-SFM).

2. Procédé de commutation d'un signal d'entrée variable dans le temps utilisant au moins un commutateur (SC1-SCN, SF1-SFM), chaque commutateur respectif (SC1-SCN, SF1-SFM) incluant un MOSFET à canal n (M_B) et un MOSFET à canal p (M_A), chacun ayant une porte configurée pour recevoir un signal d'entraînement (CN) pour changer l'état allumé/éteint de chaque MOSFET (M_A, M_B) du commutateur respectif (SC1-SCN, SF1-SFM), dans lequel le MOSFET à canal n (M_B) et le MOSFET à canal p (M_A) incluent chacun une borne de source et une borne d'évacuation, dans lequel le MOSFET à canal n (M_B) et le MOSFET à canal p (M_A) sont connectés en parallèle à leurs bornes de source et d'évacuation respectives pour former une paire de MOSFET (M_A, M_B) couplée, le procédé comprenant :

appliquer sélectivement une paire de signaux d'entraînement (V_CONN, V_CONP) aux portes du MOSFET à canal n (M_B) et du MOSFET à canal p (M_A) ;

changer un état allumé/éteint de l'au moins un commutateur (SC1-SCN, SF1-SFM) et conserver les tensions de porte-source de chaque MOSFET (M_A, M_B) au sein de la limite de claquage de porte-source de chaque MOSFET (M_A, M_B) en générant les signaux d'entraînement (V_CONN, V_CONP) de sorte que :

(a) en réponse à la réception d'un signal de commande éteint (V_CONTROL), les signaux d'entraînement (V_CONN, V_CONP) maintiennent la tension de porte du MOSFET à canal n (M_B) à ou en dessous de la tension source à tout moment et maintiennent la tension de porte du MOSFET à canal p (M_A) à ou au-dessus de la tension source à tout moment ; et

(b) en réponse à la réception d'un signal de commande allumé (V_CONTROL), les signaux d'entraînement (V_CONN, V_CONP) maintiennent la tension de porte du MOSFET à canal n (M_B) au-dessus de la tension source par une tension décalée constante, fournie par une première source de tension décalée (V_OS1), à tout moment et maintiennent la tension de porte du MOSFET à canal p (M_A) en dessous de la tension source par une tension décalée constante, fournie par une seconde source de tension décalée (V_OS2), à tout moment, le procédé incluant en outre :

recevoir un signal de commande (V_CONTROL) correspondant aux signaux de commande éteint et allumé au niveau de bornes de commande respectives d'un premier et d'un second commutateur de sélection à commande électronique (SW₁, SW₂), le signal de commande (V_CONTROL) déterminant si une première borne d'entrée (1) des premier et second commutateurs de sélection (SW₁, SW₂) ou une seconde borne d'entrée (3) des premier et second commutateurs de sélection (SW₁, SW₂) est électriquement couplée à une borne de sortie (2) du commutateur de sélection respectif (SW₁, SW₂) ;

tamponner une première tension de signal (V_SD1) apparaissant au niveau d'une première des bornes de source ou d'évacuation de la paire de MOSFET (M_A, M_B) couplée, générant de ce fait un premier signal tamponné ;

tamponner une seconde tension de signal (V_SD2) apparaissant au niveau d'une seconde des bornes de source ou d'évacuation de la paire de MOSFET (M_A, M_B) couplée, générant de ce fait un second signal tamponné ;

générer une première tension décalée et appliquer la première tension décalée plus le premier signal tamponné à la seconde borne d'entrée (3) du premier commutateur de sélection (SW₁) ;

générer une seconde tension décalée et appliquer la seconde tension décalée moins le second signal tamponné à la seconde borne d'entrée (3) du second commutateur de sélection (SW₂) ;

produire un premier signal de sortie proportionnel au plus négatif du premier signal tamponné et du second signal tamponné, et appliquer le premier signal de sortie à la première borne d'entrée (1) du premier commutateur de sélection (SW₁) ;

produire un second signal de sortie proportionnel au plus positif du premier signal tamponné et du second signal tamponné, et appliquer le second signal de sortie à la première borne d'entrée (1) du second commutateur de sélection (SW₂) ; et

coupler électriquement la première borne d'entrée (1) des premier et second commutateurs de sélection (SW₁, SW₂) ou la seconde borne d'entrée des premier et second commutateurs de sélection (SW₁, SW₂) à la borne de sortie (2) du commutateur de sélection respectif (SW₁, SW₂) conformément au signal de commande reçu (V_CONTROL).

3. Procédé selon la revendication 2, dans lequel la transition du signal d'entraînement (C_N) de l'au moins un commutateur (SC1-SCN, SF1-SFM) entre un état allumé et éteint se produit à une vitesse prédéterminée.

Drawing