CROSS-REFERENCE TO RELATED APPLICATION
[0001] This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean
Patent Application No.
10-2018-0080463, filed on July 11, 2018 in the Korean Intellectual Property Office, the entire contents of which are hereby
incorporated by reference.
BACKGROUND
[0002] The present inventive concepts relate to semiconductor packages.
[0003] A semiconductor package is provided to implement an integrated circuit chip to qualify
for use in electronic products. A semiconductor package is typically configured such
that a semiconductor chip is mounted on a printed circuit board (PCB) and bonding
wires or bumps are used to electrically connect the semiconductor chip to the printed
circuit board. With the development of electronic industry, many studies have been
conducted to improve reliability and durability of semiconductor packages.
SUMMARY
[0004] Some example embodiments of the present inventive concepts provide semiconductor
packages having improved reliability.
[0005] According to an example embodiment of the present inventive concepts, a semiconductor
package includes a first substrate, a first semiconductor structure mounted on the
first substrate, the first semiconductor structure including a first sidewall and
a second sidewall opposite to the first sidewall, a second semiconductor structure
mounted on the first substrate and spaced apart from the first semiconductor structure,
the second semiconductor structure being adjacent to the first sidewall of the first
semiconductor structure, a heat sink covering at least portions of the first semiconductor
structure, the second semiconductor structure, and the first substrate, and a thermal
interface material layer between the first semiconductor structure and the heat sink
and between the second semiconductor structure and the heat sink, the thermal interface
material layer including a first thermal interface material segment between the first
and second semiconductor structures and a second thermal interface material segment
that protrudes beyond the second sidewall, a first distance from a top surface of
the first substrate to a lowest point of a bottom surface of the first thermal interface
material segment being less than a second distance from the top surface of the first
substrate to a lower surface of a bottom surface of the second thermal interface material
segment.
[0006] According to an example embodiment of the present inventive concepts, a semiconductor
package includes a first substrate, a first semiconductor structure mounted on the
first substrate, the first semiconductor structure including a first sidewall and
a second sidewall opposite to the first sidewall, a second semiconductor structure
mounted on the first substrate and spaced apart from the first semiconductor structure,
the second semiconductor structure being adjacent to the first sidewall of the first
semiconductor structure, a heat sink covering at least portions of the first semiconductor
structure, the second semiconductor structure, and the first substrate, and a thermal
interface material layer between the first semiconductor structure and the heat sink
and between the second semiconductor structure and the heat sink, the thermal interface
material layer including a first thermal interface material segment adjacent to the
first sidewall and a second thermal interface material segment adjacent to the second
sidewall, the first thermal interface material segment being thicker than the second
interface material segment.
[0007] According to an example embodiment of the present inventive concepts, a semiconductor
package includes a package substrate a first semiconductor structure and a second
semiconductor structure that are mounted on the package substrate and are spaced apart
from each other in a direction parallel to a top surface of the package substrate,
a heat sink covering at least portions of the first semiconductor structure, the second
semiconductor structure, and the package substrate, and a thermal interface material
layer between the first semiconductor structure and the heat sink and between the
second semiconductor structure and the heat sink, the thermal interface material layer
having different thicknesses according to positions thereof, the thermal interface
material layer having a greatest thickness at a position between the first and second
semiconductor structures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008]
FIG. 1 illustrates a plan view showing a semiconductor package according to an example
embodiment of the present inventive concepts.
FIG. 2 illustrates a cross-sectional view taken along line II-II' of FIG. 1.
FIG. 3 illustrates an enlarged view showing section III of FIG. 2.
FIG. 4 illustrates a partial perspective view of FIG. 2.
FIG. 5 illustrates a cross-sectional view taken along line V-V' of FIG. 1.
FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor
package in conjunction with FIG. 2.
FIG. 7 illustrates a cross-sectional view of a semiconductor package taken along line
II-II' of FIG. 1, according to an example embodiment of the present inventive concepts.
FIG. 8 illustrates an enlarged view showing section VIII of FIG. 7.
FIGS. 9 and 10 illustrate plan views showing semiconductor packages according to some
example embodiments of the present inventive concepts.
FIG. 11 illustrates a cross-sectional view taken along line XI-XI' of FIGS. 9 or 10.
FIG. 12 illustrates a cross-sectional view showing a semiconductor package according
to an example embodiment of the present inventive concepts.
FIGS. 13 and 14 illustrate enlarged views showing section XIII of FIG. 12.
FIGS. 15 to 17 illustrate cross-sectional views showing semiconductor packages according
to some example embodiments of the present inventive concepts.
DETAILED DESCRIPTION OF EMBODIMENTS
[0009] Some example embodiments of the present inventive concepts will now be described
in detail with reference to the accompanying drawings to thoroughly and completely
explain the present inventive concepts to those skilled in the art.
[0010] FIG. 1 illustrates a plan view showing a semiconductor package according to an example
embodiment of the present inventive concepts. FIG. 2 illustrates a cross-sectional
view taken along line II-II' of FIG. 1. FIG. 3 illustrates an enlarged view showing
section III of FIG. 2. FIG. 4 illustrates a partial perspective view of FIG. 2. FIG.
5 illustrates a cross-sectional view taken along line V-V' of FIG. 1.
[0011] Referring to FIGS. 1 to 5, a semiconductor package 100 may include a first substrate
10. A second substrate 30 may be provided on the first substrate 10. A first semiconductor
chip 50 may be mounted on the second substrate 30. A second semiconductor chip 60
may further be mounted on the second substrate 30. The second semiconductor chip 60
may be spaced apart in a first direction X from the first semiconductor chip 50. A
heat sink 80 may cover at least portions of the first semiconductor chip 50, the second
semiconductor chip 60, the second substrate 30, and the first substrate 10. An adhesive
layer 82 may be interposed between the first substrate 10 and a bottom surface of
the heat sink 80. A thermal interface material layer 70 may be interposed between
the heat sink 80 and the first semiconductor chip 50 and between the heat sink 80
and the second semiconductor chip 60.
[0012] The first substrate 10 may be, for example, a printed circuit board. The first substrate
10 may be referred to as a package substrate. The first substrate 10 may include a
first core 11, first substrate upper conductive patterns 13 on a top surface of the
first core 11, a first substrate upper passivation layer 17 covering the top surface
of the first core 11, first substrate lower conductive patterns 15 on a bottom surface
of the first core 11, and a first substrate lower passivation layer 19 covering the
bottom surface of the first core 11. The first substrate upper conductive patterns
13 may be electrically connected to the first substrate lower conductive patterns
15, although not specifically illustrated in the drawings. External connection terminals
22 may be attached to the first substrate lower conductive patterns 15. The external
connection terminals 22 may be, for example, solder balls. The external connection
terminals 22 may include, for example, one or more of tin or lead.
[0013] The first core 11 may include, but not limited to, a thermosetting resin (e.g., epoxy
resin), a thermoplastic resin (e.g., polyimide), a resin (e.g., prepreg) in which
a thermosetting or thermoplastic resin is impregnated with a stiffener (e.g., glass
fiber and/or inorganic filler), or a photosensitive resin. The first substrate upper
passivation layer 17 and the first substrate lower passivation layer 19 may include
photosensitive solder resist (PSR). The photosensitive solder resist may include a
photosensitive polymer. The photosensitive polymer may include one or more of photosensitive
polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, or benzocyclobutene (BCB)
polymer. The photosensitive solder resist may further include an inorganic filler.
The first substrate upper conductive patterns 13 and the first substrate lower conductive
patterns 15 may include one or more of copper, aluminum, or gold.
[0014] The second substrate 30 may be, for example, an interposer substrate. The second
substrate 30 may include a second core 31, second substrate upper conductive patterns
33 on a top surface of the second core 31, a second substrate upper passivation layer
37 covering the top surface of the second core 31, second substrate lower conductive
patterns 35 on a bottom surface of the second core 31, and a second substrate lower
passivation layer 39 covering the bottom surface of the second core 31.
[0015] The second core 31 may include, for example, silicon. The second substrate upper
passivation layer 37 and the second substrate lower passivation layer 39 may include
photosensitive solder resist (PSR). The photosensitive solder resist may include a
photosensitive polymer. The photosensitive polymer may include one or more of photosensitive
polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, or benzocyclobutene (BCB)
polymer. The photosensitive solder resist may further include an inorganic filler.
The second substrate upper conductive patterns 33 and the second substrate lower conductive
patterns 35 may include one or more of copper, aluminum, or gold.
[0016] The first and second substrates 10 and 30 may be electrically connected to each other
through first internal connection terminals 26. The first internal connection terminals
26 may electrically connect the first substrate upper conductive patterns 13 to the
second substrate lower conductive patterns 35. The first internal connection terminals
26 may be solder balls, conductive bumps, conductive pillars, or any combination thereof.
The first internal connection terminals 26 may include one or more of copper, tin,
or lead. A first under-fill layer 24 may be interposed between the first and second
substrates 10 and 30.
[0017] The first semiconductor chip 50 may include a first chip body 51, first chip conductive
pads 53 on a bottom surface of the first chip body 51, and a first chip passivation
layer 55 covering the bottom surface of the first chip body 51. Although not specifically
illustrated in FIGS. 1-5, the first chip body 51 may include a plurality of transistors
and connection lines disposed on a semiconductor substrate. The first chip conductive
pads 53 may include metal (e.g., aluminum or copper). The first chip passivation layer
55 may be formed of, for example, a silicon nitride layer or a polyimide layer. The
first chip conductive pads 53 may be electrically connected through second internal
connection terminals 40 to corresponding ones of the second substrate upper conductive
patterns 33. The second internal connection terminals 40 may be solder balls, conductive
bumps, conductive pillars, or any combination thereof. The second internal connection
terminals 40 may include one or more of copper, tin, or lead. A second under-fill
layer 42 may be interposed between the first semiconductor chip 50 and the second
substrate 30. The first semiconductor chip 50 may include a first chip right-side
wall 50sr adjacent to the second semiconductor chip 60 and a first chip left-side
wall 50sl opposite to the first chip right-side wall 50sr. As shown in FIG. 1, the
first semiconductor chip 50 may further include a first chip front-side wall 50sf
that connects the first chip right-side wall 50sr to the first chip left-side wall
50sl at a front side of the first semiconductor chip 50, and a first chip back-side
wall 50sb that is opposite to the first chip front-side wall 50sf and connects the
first chip right-side wall 50sr to the first chip left-side wall 50sl at a back (or
rear) side of the first semiconductor chip 50. The first semiconductor chip 50 may
have a top surface 50u spaced apart at a first distance D1 from a top surface of the
second substrate 30.
[0018] The second semiconductor chip 60 may include a second chip body 61, second chip conductive
pads 63 on a bottom surface of the second chip body 61, and a second chip passivation
layer 65 covering the bottom surface of the second chip body 61. Although not specifically
illustrated in FIGS. 1-5, the second chip body 61 may include a plurality of transistors
and connection lines disposed on a semiconductor substrate. The second chip conductive
pads 63 may include metal (e.g., aluminum or copper). The second chip passivation
layer 65 may be formed of, for example, a silicon nitride layer or a polyimide layer.
The second chip conductive pads 63 may be electrically connected through third internal
connection terminals 44 to corresponding ones of the second substrate upper conductive
patterns 33. The third internal connection terminals 44 may be solder balls, conductive
bumps, conductive pillars, or any combination thereof. The third internal connection
terminals 44 may include one or more of copper, tin, or lead. A third under-fill layer
46 may be interposed between the second semiconductor chip 60 and the second substrate
30. The second semiconductor chip 60 may include a second chip left-side wall 60sl
adjacent to the first semiconductor chip 50 and a second chip right-side wall 60sr
opposite to the second chip left-side wall 60sl. As shown in FIG. 1, the second semiconductor
chip 60 may further include a second chip front-side wall 60sf that connects the second
chip right-side wall 60sr to the second chip left-side wall 60sl at a front side of
the second semiconductor chip 60, and a second chip back-side wall 60sb that is opposite
to the second chip front-side wall 60sf and connects the second chip right-side wall
60sr to the second chip left-side wall 60sl at a back (or rear) side of the first
semiconductor chip 50. The second semiconductor chip 60 may have a top surface 60u
spaced apart at a second distance D2 from the top surface of the second substrate
30.
[0019] The first distance D1 may be equal to the second distance D2. For example, the top
surface 50u of the first semiconductor chip 50 may be located at the same height (or
level) as that of the top surface 60u of the second semiconductor chip 60.
[0020] The first and second semiconductor chips 50 and 60 may be each independently selected
from a system LSI (large scale integration), a logic circuit, an image sensor (e.g.,
CIS (CMOS image sensor), a MEMS (microelectromechanical system) device, an ASIC (application
specific integrated circuit) device, and a memory device (e.g., Flash memory, DRAM,
SRAM, EEPROM, PRAM, MRAM, ReRAM, HBM (high bandwidth memory), or HMC (hybrid memory
cubic)).
[0021] The first, second, and third under-fill layers 24, 42, and 46 may include a thermosetting
resin or a photosensitive resin. The first, second, and third under-fill layers 24,
42, and 46 may further include an organic or inorganic filler. The second under-fill
layer 42 may be spaced apart from the third under-fill layer 46. The second under-fill
layer 42 may include a second under-fill protrusion 42a that protrudes beyond the
first chip right-side wall 50sr of the first semiconductor chip 50. The third under-fill
layer 46 may include a third under-fill protrusion 46a that protrudes beyond the second
chip left-side wall 60sl of the second semiconductor chip 60.
[0022] The heat sink 80 may be, for example, a metal plate. The thermal interface material
layer 70 may include, for example, a thermosetting resin layer. The thermal interface
material layer 70 may further include filler particles (not shown) distributed in
the thermosetting resin layer. The filler particles may include one or more of silica,
alumina, zinc oxide, or boron nitride. The thermal interface material layer 70 may
include first to sixth thermal interface material segments 70a to 70f. The first to
sixth thermal interface material segments 70a to 70f may constitute a single body.
The first thermal interface material segment 70a may be interposed between the heat
sink 80 and the top surface 50u of the first semiconductor chip 50. The second thermal
interface material segment 70b may be interposed between the heat sink 80 and the
top surface 60u of the second semiconductor chip 60. The third thermal interface material
segment 70c may be interposed between the first chip right-side wall 50sr of the first
semiconductor chip 50 and the second chip left-side wall 60sl of the second semiconductor
chip 60. The third thermal interface material segment 70c may have an upper surface
at the same height as either the top surface 50u of the first semiconductor chip 50
or the top surface 60u of the second semiconductor chip 60. The fourth thermal interface
material segment 70d may be interposed vertically between the third thermal interface
material segment 70c and the heat sink 80. The fourth thermal interface material segment
70d may also be interposed horizontally between the first and second thermal interface
material segments 70a and 70b. The fifth thermal interface material segment 70e may
protrude beyond the first chip left-side wall 50sl of the first semiconductor chip
50. The sixth thermal interface material segment 70f may protrude beyond the second
chip right-side wall 60sr of the second semiconductor chip 60.
[0023] As shown in FIG. 1, the fifth thermal interface material segment 70e may extend to
protrude beyond the first chip front-side wall 50sf. The fifth thermal interface material
segment 70e may also protrude beyond the first chip back-side wall 50sb. The sixth
thermal interface material segment 70f may extend to protrude beyond the second chip
front-side wall 60sf. The sixth thermal interface material segment 70f may also protrude
beyond the second chip back-side wall 60sb. The fourth thermal interface material
segment 70d may extend to lie between the first and sixth thermal interface material
segments 70a and 70f. The third thermal interface material segment 70c may lie between
the first and sixth thermal interface material segments 70a and 70f.
[0024] A third distance D3 from the top surface of the second substrate 30 to a lowest point
of a bottom surface of the third thermal interface material segment 70c may be less
than a fourth distance D4 from the top surface of the second substrate 30 to a lowest
point of a bottom surface of the fifth thermal interface material segment 70e. A fifth
distance D5 from the top surface of the second substrate 30 to a lowest point of a
bottom surface of the sixth thermal interface material segment 70f may be greater
than the third distance D3. In some example embodiments, the third distance D3 may
be less than each of the fourth and fifth distances D4 and D5. The fourth distance
D4 may be equal or substantially similar to the fifth distance D5. Any of the third,
fourth, and fifth distances D3, D4, and D5 may be less than the first and second distances
D1 and D2. The first and second semiconductor chips 50 and 60 may be spaced apart
from each other at a sixth distance D6 equal to or less than, for example, about 1
mm. The thermal interface material layer 70 may have different thicknesses depending
on position. For example, as illustrated in FIG. 5, a seventh distance D7 or a minimum
distance from the lowest point of the bottom surface of the fifth thermal interface
material segment 70e to the heat sink 80 may be less than an eighth distance D8 or
a minimum distance from the lowest point of the bottom surface of the third thermal
interface material segment 70c to the heat sink 80. The thermal interface material
layer 70 may be thickest between the first semiconductor chip 50 and the second semiconductor
chip 60, and thinnest between the heat sink 80 and the first semiconductor chip 50
or between the heat sink 80 and the second semiconductor chip 60. A thickness of the
thermal interface material layer 70 between the first and second semiconductor chips
50 and 60 may correspond to a sum of thicknesses of the third and fourth thermal interface
material segments 70c and 70d.
[0025] Referring to FIGS. 2 to 5, a gap region AR1 may be provided between the first and
second semiconductor chips 50 and 60. An upper end of the gap region AR1 may be limited
either by the height of the top surface 50u of the first semiconductor chip 50 or
by the height of the top surface 60u of the second semiconductor chip 60. A lower
end of the gap region AR1 may be limited by the top surface of the second substrate
30. One side of the gap region AR1 may be limited by the first chip right-side wall
50sr of the first semiconductor chip 50. Another side of the gap region AR1, which
is opposite to the one side of the gap region AR1, may be limited by the second chip
left-side wall 60sl of the second semiconductor chip 60.
[0026] The gap region AR1 may have therein an empty space AG1 that is not occupied by the
third thermal interface material segment 70c, the second under-fill protrusion 42a,
and the third under-fill protrusion 46a. The empty space AG1 may separate the third
thermal interface material segment 70c from the second and third under-fill protrusions
42a and 46a. In such cases, the empty space AG1 may be present between the third thermal
interface material segment 70c, the second under-fill protrusion 42a, and the third
under-fill protrusion 46a.
[0027] The thermal interface material layer 70 may have different physical properties (e.g.,
thermal expansion coefficient or elastic modulus) from those of the second and third
under-fill layers 42 and 46. The fabrication of the semiconductor package 100 may
undergo a temperature variation, for example, between room temperature and about 200°C.
When the thermal interface material layer 70 contacts any of the second under-fill
protrusion 42a or the third under-fill protrusions 46a in the gap region AR1, one
or more of the second under-fill layer 42 or the third under-fill layer 46 may suffer
from cracks due to stress resulting from a difference in physical properties between
the thermal interface material layer 70, the second under-fill protrusion 42a, and
the third under-fill protrusion 46a. For example, a crack may be generated at an interface
between the second substrate 30 and one or more of the second under-fill layer 42
or the third under-fill layer 46. In case that the crack is generated, the degree
of cracking may considerably increase due to a rapid temperature variation during
a subsequent test process on semiconductor packages. Thus, a problem such as a bump-open
(referring to a problem that one or ones of the second and third internal connection
terminals 40 and 44 are disconnected from the second substrate upper conductive patterns
33) may occur.
[0028] However, according to the present inventive concepts, because the empty space AG1
separates the third thermal interface material segment 70c from the second and third
under-fill protrusions 42a and 46a, even when the semiconductor packages undergo the
temperature variation, the crack issue may be mitigated or avoided due to no occurrence
of stress between the third thermal interface material segment 70c and the second
and third under-fill protrusions 42a and 46a. Accordingly, the semiconductor package
100 may improve in reliability.
[0029] A sum of volumes of the third thermal interface material segment 70c, the second
under-fill protrusion 42a, and the third under-fill protrusion 46a that are positioned
in the gap region AR1 may be equal to or less than about 90% of a total volume of
the gap region AR1. A volume of the empty space AG1 in the gap region AR1 between
the first and second semiconductor chips 50 and 60 may be equal to or greater than
about 10% of the total volume of the gap region AR1. If these conditions are satisfied,
even when the thermal interface material layer 70, the second under-fill layer 42,
and the third under-fill layer 46 are thermally expanded during fabrication and testing
of semiconductor packages, the empty space AG1 may still exist and separate the third
thermal interface material segment 70c from the second and third under-fill protrusions
42a and 46a. Thus, the semiconductor package 100 may exhibit improved reliability.
[0030] FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor
package in conjunction with FIG. 2.
[0031] Referring to FIG. 6, a first substrate 10 may be prepared. The first substrate 10
may include a first core 11, first substrate upper conductive patterns 13 on a top
surface of the first core 11, a first substrate upper passivation layer 17 covering
the top surface of the first core 11, first substrate lower conductive patterns 15
on a bottom surface of the first core 11, and a first substrate lower passivation
layer 19 covering the bottom surface of the first core 11. A second substrate 30 may
be attached to the first substrate 10 with one or more first internal connection terminals
26 interposed therebetween. The second substrate 30 may include a second core 31,
second substrate upper conductive patterns 33 on a top surface of the second core
31, a second substrate upper passivation layer 37 covering the top surface of the
second core 31, second substrate lower conductive patterns 35 on a bottom surface
of the second core 31, and a second substrate lower passivation layer 39 covering
the bottom surface of the second core 31.
[0032] A first under-fill layer 24 may be formed between the first and second substrates
10 and 30. For example, the first under-fill layer 24 may be formed by providing a
thermosetting or photosensitive resin solution into a space between the first and
second substrates 10 and 30, and then curing the resin solution. A first semiconductor
chip 50 may be mounted on the second substrate 30 with one or more second internal
connection terminals 40 interposed therebetween. A second under-fill layer 42 may
be formed between the first semiconductor chip 50 and the second substrate 30. Similarly
to the formation of the first under-fill layer 24, the second under-fill layer 42
may be formed by providing a thermosetting or photosensitive resin solution into a
space between the second substrate 30 and the first semiconductor chip 50, and then
curing the resin solution. A portion of the second under-fill layer 42 may protrude
beyond a first chip right-side wall 50sr of the first semiconductor chip 50, thereby
forming a second under-fill protrusion 42a. A second semiconductor chip 60 may be
mounted on the second substrate 30 with one or more third internal connection terminals
44 interposed therebetween.
[0033] FIG. 6 shows a dotted line that indicates a gap region AR1 between the first and
second semiconductor chips 50 and 60. The second under-fill protrusion 42a may be
present in the gap region AR1 shown in FIG. 6.
[0034] Subsequently, referring to FIG. 2, a third under-fill layer 46 may be formed between
the second semiconductor chip 60 and the second substrate 30. A resin solution may
be coated on a top surface 50u of the first semiconductor chip 50 and a top surface
60u of the second semiconductor chip 60, and then cured at a temperature of about
200°C while a jig or the like presses down a heat sink 80 covering the resin solution,
to provide a thermal interface material layer 70. In this step, the resin solution
may be pressed downwardly and then compelled to move outwardly beyond edges of the
first and second semiconductor chips 50 and 60. The outward movement of the resin
solution may form third, fourth, fifth, and sixth thermal interface material segments
70c, 70d, 70e, and 70f. As semiconductor packages are highly integrated, a spacing
between the first and second semiconductor chips 50 and 60 may be reduced such that
the resin solutions pushed outwardly beyond the edges of the first and second semiconductor
chips 50 and 60 may be connected to cause the thermal interface material layer 70
to have a relatively large thickness between the first and second semiconductor chips
50 and 60. The aforementioned processes may fabricate a semiconductor package 100
configured as shown in FIG. 2. A lower end of the heat sink 80 may be attached through
the adhesive layer 82 to a top surface of the first substrate 10. The adhesive layer
82 may include the same material as that of the thermal interface material layer 70.
The adhesive layer 82 and the thermal interface material layer 70 may be formed at
the same time. Subsequently, external connection terminals 22 may be attached to the
first substrate lower conductive patterns 15.
[0035] According to the example embodiment, because the empty space AG1 separates the third
thermal interface material segment 70c from the second and third under-fill protrusions
42a and 46a, even when the fabrication of the semiconductor package 100 undergoes
the temperature variation, the crack issue may be mitigated or avoided due to no occurrence
of stress between the third thermal interface material segment 70c and the second
and third under-fill protrusions 42a and 46a. Thus, the semiconductor package 100
may improve in reliability, decrease in defect rate, and/or increase in manufacturing
yield.
[0036] FIG. 7 illustrates a cross-sectional view showing a semiconductor package taken along
line II-II' of FIG. 1, according to an example embodiment of the present inventive
concepts. FIG. 8 illustrates an enlarged view showing section VIII of FIG. 7.
[0037] Referring to FIGS. 7 and 8, a semiconductor package 101 may be configured such that
the second under-fill protrusion 42a may extend to contact the first chip right-side
wall 50sr of the first semiconductor chip 50. The third under-fill protrusion 46a
may extend to contact the second chip left-side wall 60sl of the second semiconductor
chip 60. The second under-fill protrusion 42a may also contact the third under-fill
protrusion 46a. A ninth distance D9 may be provided between the top surface of the
second substrate 30 and an upper end of the second under-fill protrusion 42a. The
ninth distance D9 may be equal to or less than about 50% of the first distance D1.
A tenth distance D10 may be provided between the top surface of the second substrate
30 and an upper end of the third under-fill protrusion 46a. The tenth distance D10
may be equal to or less than about 50% of the first distance D1. In the gap region
AR1, the third thermal interface material segment 70c may have a relatively large
volume compared to the case of the semiconductor package 100 of FIG. 2. Nevertheless,
the empty space AG1 may still exist and separate the third thermal interface material
segment 70c from the second and third under-fill protrusions 42a and 46a when the
thermal interface material layer 70, the second under-fill layer 42, and the third
under-fill layer 46 thermally expand during fabrication and testing of semiconductor
packages. Thus, the semiconductor package 101 may have improved reliability. Other
configurations may be identical or substantially similar to those discussed with reference
to FIGS. 1 to 5.
[0038] FIGS. 9 and 10 illustrate plan views showing semiconductor packages according to
some example embodiments of the present inventive concepts. FIG. 11 illustrates a
cross-sectional view taken along line XI-XI' of FIGS. 9 or 10.
[0039] Referring to FIGS. 9 and 11, a semiconductor package 102 may be configured such that
the first semiconductor chip 50 may be mounted on a central portion of the second
substrate 30 and second semiconductor chips 60a and 60b may be mounted on the second
substrate 30 and on opposite sides of the first semiconductor chip 50. The second
semiconductor chips 60a and 60b may include a first second-semiconductor-chip 60a
and a second second-semiconductor-chip 60b. The third thermal interface material segment
70c may be disposed between the first second-semiconductor-chip 60a and the first
semiconductor chip 50 and between the second-semiconductor-chip 60b and the first
semiconductor chip 50. The first second-semiconductor-chip 60a and the second second-semiconductor-chip
60b may have the same function or different functions from each other. Other configurations
may be identical or substantially similar to those discussed with reference to FIGS.
1 to 5.
[0040] Referring to FIGS. 10 and 11, a semiconductor package 103 may be configured such
that the first semiconductor chip 50 may be mounted on a central portion of the second
substrate 30, and second semiconductor chips 60a, 60b, 60c, and 60d may be mounted
on the second substrate 30 and at opposite sides of the first semiconductor chip 50.
The second semiconductor chips 60a, 60b, 60c, and 60d may include a first second-semiconductor-chip
60a, a second second-semiconductor-chip 60b, a third second-semiconductor-chip 60c,
and a fourth second-semiconductor-chip 60d. The first and third second-semiconductor-chips
60a and 60c may be disposed adjacent to one side of the first semiconductor chip 50.
The second and fourth second-semiconductor-chips 60b and 60d may be disposed adjacent
to another side of the first semiconductor chip 50, which is opposite to the one side
of the first semiconductor chip 50. The second semiconductor chips (alternatively,
the first to fourth second-semiconductor-chips) 60a, 60b, 60c, and 60d may be spaced
apart from each other. The second semiconductor chips 60a, 60b, 60c, and 60d may have
the same function or different functions from each other. Other configurations may
be identical or substantially similar to those discussed with reference to FIGS. 1
to 5.
[0041] FIG. 12 illustrates a cross-sectional view showing a semiconductor package according
to an example embodiment of the present inventive concepts. FIGS. 13 and 14 illustrate
enlarged views showing section XIII of FIG. 12.
[0042] Referring to FIGS. 12 and 13, a semiconductor package 104 may be configured such
that the first distance D1 may be different from the second distance D2. For example,
the first distance D1 may be less than the second distance D2. In such cases, the
top end of the gap region AR1 may be limited by the height of the top surface 50u
of the first semiconductor chip 50. The fourth thermal interface material segment
70d may cover an upper portion of the second chip left-side wall 60sl of the second
semiconductor chip 60.
[0043] If the second distance D2 is less than the first distance D1, the top end of the
gap region AR1 may be limited by the height of the top surface 60u of the second semiconductor
chip 60. The fourth thermal interface material segment 70d may cover an upper portion
of the first chip right-side wall 50sr of the first semiconductor chip 50. Other configurations
may be identical or substantially similar to those discussed with reference to FIGS.
1 to 5.
[0044] Referring to FIG. 14, a cross-section of the third thermal interface material segment
70c may have an inflection point PA. For another example, the third thermal interface
material segment 70c may have a bottom surface with a groove. Because the first and
second distances D1 and D2 are different from each other, a resin solution for forming
the thermal interface material layer 70 may be non-uniformly pressed under the heat
sink 80 covering the resin solution. Thus, the inflection point PA or the groove may
be formed on a lower surface of the thermal interface material layer 70. When the
first distance D1 is less than the second distance D2, the inflection point PA may
be nearer to the first semiconductor chip 50 than to the second semiconductor chip
60. When the first distance D1 is greater than the second distance D2, the inflection
point PA may be nearer to the second semiconductor chip 60 than to the first semiconductor
chip 50. Other configurations may be identical or substantially similar to those discussed
with reference to FIGS. 12 and 13.
[0045] FIGS. 15 to 17 illustrate cross-sectional views showing semiconductor packages according
to some example embodiments of the present inventive concepts.
[0046] Referring to FIG. 15, a semiconductor package 105 may be configured such that a second
sub-semiconductor package 160 may be mounted on the second substrate 30 with the third
internal connection terminals 44 interposed therebetween. The second sub-semiconductor
package 160 may be spaced apart from the first semiconductor chip 50. The second sub-semiconductor
package 160 may include a second sub-package substrate 162 and a plurality of second
semiconductor chips 164 that are sequentially stacked on the second sub-package substrate
162. The second semiconductor chips 164 may include through electrodes 166 therein.
The second semiconductor chips 164 may be stacked in a flip-chip bonding manner. A
second sub-mold layer 165 may cover sidewalls of the second semiconductor chips 164
and a top surface of the second sub-package substrate 162. An uppermost one of the
second semiconductor chips 164 may have a top surface coplanar with that of the second
sub-mold layer 165. The second thermal interface material segment 70b of the thermal
interface material layer 70 may directly contact the uppermost second sub-semiconductor
chip 164. In such cases, heat generated from the uppermost second semiconductor chips
164 may be discharged outwardly through the thermal interface material layer 70. Other
configurations may be identical or substantially similar to those discussed with reference
to FIGS. 1 to 5.
[0047] Referring to FIG. 16, a semiconductor package 106 may be configured such that a first
sub-semiconductor package 150 may be mounted on the second substrate 30 with the second
internal connection terminals 40 interposed therebetween. The first sub-semiconductor
package 150 may be spaced apart from the second sub-semiconductor package 160. The
first sub-semiconductor package 150 may include a first sub-package substrate 151,
a first semiconductor chip 153 wire-bonded to the first sub-package substrate 151,
and a first sub-mold layer 154 covering the first semiconductor chip 153. Other configurations
may be identical or substantially similar to those discussed above with reference
to FIG. 15.
[0048] Referring to FIG. 17, a semiconductor package 107 is not provided with the second
substrate 30 as illustrated in FIGS. 15 and 16, and may be configured such that the
first semiconductor chip 50 is directly mounted on the first substrate 10 with the
second internal connection terminals 40 interposed therebetween. Further, the second
semiconductor chip 60 may be directly mounted on the first substrate 10 with the third
internal connection terminals 44 interposed therebetween. Other configurations may
be identical or substantially similar to those discussed with reference to FIGS. 1
to 5.
[0049] The first semiconductor chip 50 of FIG. 2 and the first sub-semiconductor package
150 of FIG. 16 may each be referred to as a first semiconductor structure. The second
semiconductor chip 60 of FIG. 2 and the second sub-semiconductor package 160 of FIG.
16 may each be referred to as a second semiconductor structure.
[0050] According to the present inventive concepts, a semiconductor package may include
an under-fill layer and a thermal interface material layer that are spaced apart from
each other to mitigate or prevent defects (e.g., crack) resulting from a difference
in physical properties between the under-fill layer and the thermal interface material
layer, thereby improving reliability.
[0051] Furthermore, a method of fabricating the semiconductor package may mitigate or prevent
defects (e.g., crack) and may increase in manufacturing yield.
[0052] Although the present inventive concepts have been described in connection with some
example embodiments of the present inventive concepts illustrated in the accompanying
drawings, it will be understood to those skilled in the art that various changes and
modifications may be made without departing from the technical spirit and essential
feature of the present inventive concepts. It will be apparent to those skilled in
the art that various substitution, modifications, and changes may be thereto without
departing from the scope and spirit of the inventive concepts.
1. A semiconductor package, comprising:
a first substrate;
a first semiconductor structure mounted on the first substrate, the first semiconductor
structure including a first sidewall and a second sidewall opposite to the first sidewall;
a second semiconductor structure mounted on the first substrate and spaced apart from
the first semiconductor structure, the second semiconductor structure being adjacent
to the first sidewall of the first semiconductor structure;
a heat sink covering at least portions of the first semiconductor structure, the second
semiconductor structure, and the first substrate; and
a thermal interface material layer between the first semiconductor structure and the
heat sink and between the second semiconductor structure and the heat sink, the thermal
interface material layer including a first thermal interface material segment between
the first and second semiconductor structures and a second thermal interface material
segment that protrudes beyond the second sidewall, a first distance from a top surface
of the first substrate to a lowest point of a bottom surface of the first thermal
interface material segment being less than a second distance from the top surface
of the first substrate to a lowest point of a bottom surface of the second thermal
interface material segment.
2. The semiconductor package of claim 1, further comprising:
a first under-fill layer between the first substrate and the first semiconductor structure,
wherein the first under-fill layer includes a first under-fill protrusion that protrudes
beyond the first sidewall, and
wherein the first thermal interface material segment is spaced apart from the first
under-fill protrusion.
3. The semiconductor package of claim 2, wherein a third distance from the top surface
of the first substrate to a highest point of an upper surface of the first under-fill
protrusion is equal to or less than about 50% of a fourth distance from the top surface
of the first substrate to a top surface of the first semiconductor structure.
4. The semiconductor package of claim 2, wherein
the second semiconductor structure includes,
a third sidewall adjacent to the first semiconductor structure, and
a fourth sidewall opposite to the third sidewall,
the thermal interface material layer further includes a third thermal interface material
segment that protrudes beyond the fourth sidewall, and
a fifth distance from the top surface of the first substrate to a lowest point of
a bottom surface of the third thermal interface material segment is greater than the
first distance.
5. The semiconductor package of claim 4, further comprising:
a second under-fill layer between the first substrate and the second semiconductor
structure,
wherein the second under-fill layer includes a second under-fill protrusion that protrudes
beyond the third sidewall, and
wherein the first thermal interface material segment is spaced apart from the second
under-fill protrusion.
6. The semiconductor package of claim 5, wherein the second under-fill protrusion is
in contact with the first under-fill protrusion.
7. The semiconductor package of claim 5, wherein a sixth distance from the top surface
of the first substrate to a highest point of an upper surface of the second under-fill
protrusion is equal to or less than about 50% of a seventh distance from the top surface
of the first substrate to a top surface of the second semiconductor structure.
8. The semiconductor package of claim 5, wherein
the first and second semiconductor structures defines a gap region therebetween,
an upper end of the gap region corresponds to a lower one from among heights of top
surfaces of the first and second semiconductor structures,
a lower end of the gap region corresponds to the top surface of the first substrate,
a first side of the gap region corresponds to the first sidewall,
a second side of the gap region, which is opposite to the first side of the gap region,
corresponds to the third sidewall, and
a sum of volumes of the first thermal interface material segment, the first under-fill
protrusion, and the second under-fill protrusion that are positioned in the gap region
is equal to or less than about 90% of a total volume of the gap region.
9. The semiconductor package of claim 8, wherein
the gap region includes an empty space that is not occupied by the first thermal interface
material segment, the first under-fill protrusion, and the second under-fill protrusion,
and
a volume of the empty space is equal to or greater than about 10% of the total volume
of the gap region.
10. The semiconductor package of claim 1, further comprising:
a second substrate under the first substrate,
wherein the heat sink is attached to the second substrate.
11. The semiconductor package of claim 10, further comprising:
an adhesive layer between the heat sink and the second substrate,
wherein the adhesive layer includes a same material as the thermal interface material
layer.
12. The semiconductor package of claim 1, wherein each of the first and second semiconductor
structures is one of a semiconductor chip or a sub-semiconductor package.
13. The semiconductor package of claim 1, wherein a cross-section of the first thermal
interface material segment has a profile having an inflection point at a lower surface
thereof.
14. The semiconductor package of claim 13, wherein:
a top surface of the first semiconductor structure is lower than a top surface of
the second semiconductor structure, and
the inflection point is nearer to the first semiconductor structure than to the second
semiconductor structure.
15. The semiconductor package of claim 1, wherein one of the first semiconductor structure
or the second semiconductor structure includes a sub-package substrate and at least
one semiconductor chip mounted on the sub-package substrate,
wherein the thermal interface material layer is in contact with a top surface of the
semiconductor chip.