LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR AND DISPLAY DEVICE

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the field of display technology, and in particular, relates to an array substrate and a method of fabricating the same, and a display device.

BACKGROUND OF THE INVENTION

[0002] Amorphous silicon (α-Si) technology and low-temperature polysilicon (LTPS) technology are widely used in the field of display technology. With the development of display technology, the LTPS technology is increasingly widely used due to the advantages of high efficient and high definition.

[0003] A magnitude of leakage current is an important parameter for the LTPS structure. The high magnitude of leakage current may cause a driving voltage to be unable to maintain at a certain level and may result in undesirable display performance. A dual-gate or multi-gate structure is currently used as a method for reducing the leakage current of the LTPS structure, for example, the dual-gate structure including two gates 7 shown in Fig. 1 is used. Although an electric field distribution in a channel may be effectively reduced by using the plurality of gates so that hot carrier effect is reduced and the leakage current is restrained, the gate 7 is generally made of metal material with good electrical conductivity, e.g., molybdenum or molybdenum aluminum alloy, and the material (i.e., the gate 7 in Fig. 1) itself is opaque and will block the light. Therefore, the technical solution of utilizing the structure of dual-gate or multi-gate in the prior art goes against improvement of display aperture ratio. US 2007/159565 discloses the features of the preamble of claim 1.

SUMMARY OF THE INVENTION

[0004] The embodiments of the present invention provide a low-temperature polysilicon thin film transistor array substrate according to claims 1-10 and a method of fabricating the same according to claims 11-14, and a display device according to claim 15, which reduces the leakage current and improves the aperture ratio of panel.

[0005] In the array substrate according to the embodiment of the present invention, the multi-gate structure is provided directly below the source, so that the aperture ratio of panel is improved and the leakage current is reduced. In addition, the resin layer with low dielectric constant is provided between the gate and the source and drain, so that the coupling capacitance generated by the gate and the source overlapped with each other is avoided, thereby reducing the leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] 

Fig. 1 is a plan view of an array substrate of dual-gate structure in prior art.

Fig. 2A is a plan view of an array substrate in a first embodiment of the present invention.

Fig. 2B is a cross-sectional view taken along a line A-B in Fig. 2A.

Fig. 3A is a plan view of structures formed in a first patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 3B is a cross-sectional view taken along a line A-B in Fig. 3A.

Fig. 4A is a plan view of structures formed in a second patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 4B is a cross-sectional view taken along a line A-B in Fig. 4A.

Fig. 5A is a plan view of structures formed in a third patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 5B is a cross-sectional view taken along a line A-B in Fig. 5A.

Fig. 6A is a plan view of structures formed in a fourth patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 6B is a cross-sectional view taken along a line A-B in Fig. 6A.

Fig. 7A is a plan view of structures formed in a fifth patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 7B is a cross-sectional view taken along a line A-B in Fig. 7A.

Fig. 8A is a plan view of structures formed in a sixth patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 8B is a cross-sectional view taken along a line A-B in Fig. 8A.

Fig. 9A is a plan view of structures formed in a seventh patterning process in a method of fabricating an array substrate in a second embodiment of the present invention.

Fig. 9B is a cross-sectional view taken along a line A-B in Fig. 9A.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0007] To make those skilled in the art better understand the technical solutions of the present invention, an array substrate and a method of fabricating the same, and a display device according to examples will be described in detail below in conjunction with the accompanying drawings.

[First Embodiment]

[0008] The first embodiment provides a low-temperature polysilicon thin film transistor array substrate. Referring to Figs. 2A and 2B, Fig. 2A is a plan view of the array substrate of the first embodiment, and Fig. 2B is a cross-sectional view taken along a line A-B in Fig. 2A. The array substrate of the first embodiment comprises: a substrate 1; a polysilicon active layer 2 provided on the substrate 1; a first insulation layer 3 provided on the active layer 2; a plurality of gates 7 and a gate line 70 provided on the first insulation layer 3; a second insulation layer 4 provided on the gate 7; a source 5, a drain 6, a data line 11 and a pixel electrode 8 electrically connected with the drain 6, which are provided on the second insulation layer 4, the source 5 covering the gates 7.

[0009] As shown in Fig. 2B, the number of the plurality of gates is three. Referring to Figs. 2A and 2B, the multi-gate structure is provided directly below the source 5, and the plurality of gates 7 are covered by the source 5 in the plan view of the array substrate. Compared with the array substrate in the prior art in which the plurality of gates not covered by the source in the plan view additionally block the light, in the array substrate of the embodiment, light blocking by the metal is reduced by providing the plurality of gates directly below the source, so that the aperture ratio of panel is improved.

[0010] Referring to Fig. 2B, the array substrate of the embodiment further comprises a third insulation layer 9 provided on the pixel electrode 8 and a slit-shaped common electrode 10 provided on the third insulation layer 9.

[0011] The pixel electrode 8 and the common electrode 10 are both made of at least one of indium gallium zinc oxide, indium zinc oxide (IZO), indium tin oxide (ITO) and indium gallium tin oxide.

[0012] The first insulation layer 3, the second insulation layer 4 and the third insulation layer 9 may be made of at least one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide. The gate 7, the source 5 and the drain 6 may be made of at least one of molybdenum, molybdenum niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper. The active layer 2 may be made of low-temperature polysilicon material.

[0013] Alternatively, in the array substrate of the embodiment, the number of the plurality of gates 7 may be two. Of course, the person skilled in the art may utilize four or five gates according to the requirement.

[0014] In the low-temperature polysilicon thin film transistor array substrate according to the embodiment, a buffer layer may further be provided below the active layer 2.

[0015] Alternatively, in the array substrate of the embodiment, the common electrode and the pixel electrode may be provided in the same layer, so as to form a structure of in-plane switching (IPS). In addition, the common electrode may also be provided in the same layer as the gate.

[0016] Alternatively, in the array substrate of the embodiment, the second insulation layer 4 may comprise resin material. The resin material may include polymethyl methacrylate and photosensitive agent. A thickness of the second insulation layer 4 ranges from 1.5µm to 2.0µm.

[Second Embodiment]

[0017] The second embodiment provides a method of fabricating a low-temperature polysilicon thin film transistor array substrate. Before description of the fabricating method, it should be understood that the patterning process in the present invention may comprise only a photolithography process, or comprise a photolithography process and etching process, and may further comprise other process for forming predetermined patterns, e.g., printing, ink jetting, etc. The photolithography process refers to a process for forming patterns, which comprises processing procedures such as film coating, exposure and development and utilizes photoresists, mask plates, an exposure machine and so on. The patterning process may be selected according to the corresponding structure to be formed in the present invention.

[0018] The method of fabricating the low-temperature polysilicon thin film transistor array substrate according to the second embodiment comprises steps S1 through S8 as follows.

[0019] In step S1, an amorphous silicon thin film is deposited on a substrate, then the amorphous silicon is converted into low-temperature polysilicon, and a pattern comprising an active layer 2 is formed by a patterning process.

[0020] In this step, as shown in Figs. 3A and 3B, the amorphous silicon layer is deposited on the substrate 1 by chemical vapor deposition (CVD) process. For example, the amorphous silicon is crystallized into the low-temperature polysilicon by use of excimer laser annealing (ELA) process. The steps of photolithography and etching are then performed to form the desired patterned low-temperature polysilicon layer.

[0021] In step S2, a pattern of first insulation layer 3 is formed on the substrate subjected to step S1.

[0022] In this step, as shown in Figs. 4A and 4B, the first insulation layer 3 is formed on the substrate 1 subjected to step S1 by use of chemical vapor deposition (CVD) process, a thickness of the first insulation layer 3 ranges from 1000Å to 6000Å. The first insulation layer 3 is generally formed by using transparent material (silicon oxide, silicon nitride, hafnium oxide or aluminum oxide).

[0023] In step S3, a gate metal thin film is deposited on the substrate subjected to step S2, and a pattern comprising gates 7 and a gate line is formed by a patterning process.

[0024] In this step, as shown in Figs. 4A and 4B, the gate metal thin film is formed on the substrate 1 subjected to step S2, the gate metal thin film may be formed by using at least one of molybdenum, molybdenum niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper, and then the pattern comprising the gates 7 and the gate line is formed by a patterning process, the gates 7 are connected with the gate line. Doping is performed on the active layer by using gates 7 as mask layer. The gates are formed as a three-gate pattern or multi-gate pattern and has a comb-shaped distribution, the multi-gate structure is provided directly below the source.

[0025] The gate metal thin film may be formed by using deposition process, sputtering process or thermal evaporation process, a thickness of the gate metal thin film ranges from 1000Å to 7000Å. In the patterning process, a layer of photoresist is first coated on the gate metal thin film, and then exposure, development, etching and stripping are performed on the photoresist by using a mask plate, so as to form the pattern comprising the gates 7 and the gate line.

[0026] The multi-gate structure is provided directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved.

[0027] In step S4, a layer of resin layer with a thickness about 3 µm is spin-coated on the substrate subjected to step S3, so as to form a second insulation layer 4. Via holes are formed in the first insulation layer 3 and the second insulation layer 4 by a patterning process.

[0028] In this step, as shown in Figs. 5A and 5B, a layer of resin layer is coated on the substrate 1 subjected to step S3 by a spin coating process, so as to form the second insulation layer 4. The via holes are formed in the first insulation layer 3 and the second insulation layer 4 by a patterning process.

[0029] The resin layer with low dielectric constant is provided between the gate 7 and the source and drain, so as to avoid that a coupling capacitance is formed by the gate and the source overlapped with each other.

[0030] In step S5, a source and drain metal thin film is deposited on the substrate subjected to step S4, and a pattern comprising a source 5 and a drain 6 is formed by a patterning process.

[0031] In this step, as shown in Figs. 6A and 6B, the source and drain metal thin film is formed on the substrate 1 subjected to step S4, and the pattern comprising the source 5, the drain 6 and a data line is formed by a patterning process. The source 5 and the drain 6 are provided above and at both sides of the second insulation layer 4 and are connected with a doped region of the active layer 2 through the via holes provided in the second insulation layer 4 and the first insulation layer 3, respectively.

[0032] The source and drain metal thin film may be formed by using deposition process, sputtering process or thermal evaporation process. In the patterning process, a layer of photoresist is first coated on the source and drain metal thin film, and then exposure, development, etching and stripping are performed on the photoresist by using a mask plate, so as to form the pattern comprising the source 5, the drain 6 and the data line. The source and drain metal thin film may be formed by using at least one of molybdenum, molybdenum niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper.

[0033] In step S6, a transparent conductive thin film is deposited on the substrate subjected to step S5, and a pattern comprising a pixel electrode 8 is formed by a patterning process, the pixel electrode 8 is electrically connected with the drain 6.

[0034] In this step, as shown in Figs. 7A and 7B, the pixel electrode film is formed on the substrate subjected to step S5, and the pattern comprising the pixel electrode 8 is formed by a patterning process. The pixel electrode 8 is provided above the drain 6 and the second insulation layer 4, and the pixel electrode 8 is electrically connected with the drain 6.

[0035] The pixel electrode thin film may be formed by using deposition process, sputtering process or thermal evaporation process, a thickness of the pixel electrode thin film ranges from 100Å to 1000Å. In the patterning process, a layer of photoresist is first coated on the pixel electrode thin film, and exposure, development, etching and stripping are performed on the photoresist by using a mask plate, so as to form the pattern comprising the pixel electrode 8.

[0036] In step S7, a third insulation layer 9 is deposited on the substrate subjected to step S6, and via holes are formed by a patterning process.

[0037] In this step, as shown in Figs. 8A and 8B, a passivation layer thin film is formed on the substrate 1 subjected to step S6, and the pattern of the third insulation layer 9 (PVX) is formed by a patterning process, the pattern of the third insulation layer 9 covers the source 5, the drain 6 and the pixel electrode 8.

[0038] The passivation layer thin film may be formed by using deposition process, sputtering process or thermal evaporation process, a thickness of the passivation layer thin film ranges from 1000Å to 6000Å. In the patterning process, a layer of photoresist is first coated on the passivation layer thin film, and exposure, development, etching and stripping are performed on the photoresist by using a mask plate, so as to form the pattern comprising the third insulation layer 9 and the via hole. Similar to the first insulation layer 3, the third insulation layer 9 is generally formed by using transparent material (silicon oxide, silicon nitride, hafnium oxide or aluminum oxide).

[0039] Here, the third insulation layer 9 is formed above the data line, the source 5 and the drain 6 and extends to a peripheral lead wire region of the array substrate. A data line driving signal introducing electrode is provided at the peripheral lead wire region of the array substrate. The via hole is provided at the position of the third insulation layer 9 corresponding to the data line driving signal introducing electrode, and the data line is electrically connected with the data line driving signal introducing electrode through the via hole.

[0040] In step S8, a transparent conductive thin film is deposited on the substrate subjected to step S7, and a pattern comprising a common electrode 10 is formed by a patterning process.

[0041] In this step, as shown in Figs. 9A and 9B, the common electrode thin film is formed on the substrate 1 subjected to step S7, and the pattern comprising the common electrode 10 is formed on the third insulation layer 9 by a patterning process.

[0042] The common electrode thin film may be formed by using deposition process, sputtering process or thermal evaporation process. In the patterning process, a layer of photoresist is first coated on the common electrode thin film, and exposure, development, etching and stripping are performed on the photoresist by using a mask plate, so as to form the pattern comprising the common electrode 10. The common electrode 10 is a slit electrode having a comb-shaped distribution.

[0043] In the above method of fabricating the array substrate, the number of the patterning processes may be reduced by using half tone or gray tone mask plate, and the embodiment is not limited thereto.

[0044] In the method of fabricating the array substrate in the embodiment, the plurality of gates are formed directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved. In addition, the resin layer with low dielectric constant is formed between the gate and the source and drain, so that the coupling capacitance to be generated by the gate and the source overlapped with each other is avoided.

[0045] The examples further provide a display device that comprises any one of the above array substrates. The display device may be applied to any product or component with display function, such as LCD panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital picture frame, navigation, etc.

Claims

1. A low-temperature polysilicon thin film transistor array substrate, comprising:

a substrate (1);

a polysilicon active layer (2) provided on the substrate (1);

a first insulation layer (3) provided on the active layer (2);

a plurality of gates (7) and a gate line (70) provided on the first insulation layer (3);

a second insulation layer (4) provided on the plurality of gates (7);

a source (5), a drain (6), a data line (11) and a pixel electrode (8) electrically connected with the drain (6), which are provided on the second insulation layer (4),

characterized in that the plurality of gates (7) are formed to have a comb-shaped distribution; and the data line (11) fully cover the plurality of gates (7) having the comb-shaped distribution along an extending direction of the data line (11).

2. The array substrate of claim 1, further comprising a buffer layer provided below the active layer (2).

3. The array substrate of claim 1 or 2, wherein the number of the plurality of gates (7) is two to five.

4. The array substrate of claim 1, further comprising a common electrode (10) provided in the same layer as the pixel electrode (8).

5. The array substrate of claim 1, further comprising:

a third insulation layer (9) provided on the pixel electrode (8); and

a slit-shaped common electrode (10) provided on the third insulation layer (9).

6. The array substrate of claim 1, further comprising a common electrode (10) provided in the same layer as the gate (7).

7. The array substrate of claim 1, wherein the second insulation layer (4) comprises resin material.

8. The array substrate of claim 7, wherein the resin material includes polymethyl methacrylate and photosensitive agent.

9. The array substrate of claim 7, wherein a thickness of the second insulation layer (4) ranges from 1 .5µm to 2.0µm.

10. The array substrate of claim 1, wherein the extending direction of the data line (11) is perpendicular to an extending direction of the gate line (70), and the plurality of gates (7) having the comb-shaped distribution are arranged along the extending direction of the data line (11).

11. A method of fabricating a low-temperature polysilicon thin film transistor array substrate according to claims 1-9, comprising steps of:

sequentially forming an active layer (2), a first insulation layer (3) and a plurality of gates (7) and a gate line (70) on a base substrate (1);

forming a second insulation layer (4) comprising a first via and a second via on the substrate (1) on which the active layer (2), the first insulation layer (3) and the plurality of gates (7) are formed, wherein the plurality of gates are formed to have a comb-shaped distribution;

forming a pattern comprising a source (5) ,a drain (6) and a data line (11) on the substrate (1) on which the second insulation layer (4) is formed, the data line (11) fully covering the plurality of gates (7) having the comb-shaped distribution along an extending direction of the data line (11); and

forming a pattern comprising a pixel electrode (8) on the substrate (1) on which the pattern comprising the source (5) and the drain (6) is formed, the pixel electrode (8) being connected with the drain (6).

12. The method of claim 10, wherein the step of sequentially forming an active layer (2), a first insulation layer (3) and a plurality of gates (7) on a base substrate (1) comprises:

depositing a buffer layer and an amorphous silicon thin film on the substrate (1), converting the amorphous silicon into low-temperature polysilicon, and forming a pattern comprising the active layer (2) by a patterning process;

forming a pattern of the first insulation layer (3) on the substrate (1) on which the active layer (2) is formed; and

depositing a gate metal thin film on the substrate (1) on which the first insulation layer (3) is formed, and forming a pattern comprising the plurality of gates (7) by a patterning process.

13. The method of claim 10, further comprising steps of:

forming a third insulation layer (9) on the substrate (1) on which the pattern of the pixel electrode (8) is formed; and

depositing a transparent conductive thin film on the substrate (1) on which the third insulation layer (9) is formed, and forming a pattern comprising a common electrode (10) by a patterning process.

14. The method of claim 11, further comprising a step of:
forming a pattern of a common electrode (10) while forming the pattern comprising the plurality of gates (7).

15. A display device, comprising the array substrate of any one of claims 1 to 9.

Ansprüche

1. Niedrigtemperatur-Polysilicium-Dünnfilmtransistorarraysubstrat, aufweisend:

ein Substrat (1);

eine aktive Polysiliciumschicht (2), die auf dem Substrat (1) vorgesehen ist;

eine erste Isolierschicht (3), die auf der aktiven Schicht (2) vorgesehen ist;

mehrere Gates (7) und eine Gate-Leitung (70), die auf der ersten Isolierschicht (3) vorgesehen sind;

eine zweite Isolierschicht (4), die auf den mehreren Gates (7) vorgesehen ist;

eine Source (5), ein Drain (6), eine Datenleitung (11) und eine Pixelelektrode (8), die elektrisch mit dem Drain (6) verbunden sind, die auf der zweiten Isolierschicht (4) vorgesehen sind,

dadurch gekennzeichnet, dass die mehreren Gatter (7) so gebildet sind, dass sie eine kammförmige Verteilung haben; und

die Datenleitung (11) die mehreren Gates (7) mit der kammförmigen Verteilung entlang einer Erstreckungsrichtung der Datenleitung (11) vollständig abdeckt.

2. Arraysubstrat nach Anspruch 1, das ferner eine Pufferschicht aufweist, die unterhalb der aktiven Schicht (2) vorgesehen ist.

3. Arraysubstrat nach Anspruch 1 oder 2, wobei die Anzahl der mehreren Gates (7) zwei bis fünf beträgt.

4. Arraysubstrat nach Anspruch 1, das ferner eine gemeinsame Elektrode (10) aufweist, die in derselben Schicht wie die Pixelelektrode (8) vorgesehen ist.

5. Arraysubstrat nach Anspruch 1, das ferner aufweist:

eine dritte Isolierschicht (9), die auf der Pixelelektrode (8) vorgesehen ist; und

eine schlitzförmige gemeinsame Elektrode (10), die auf der dritten Isolierschicht (9) vorgesehen ist.

6. Arraysubstrat nach Anspruch 1, das ferner eine gemeinsame Elektrode (10) aufweist, die in derselben Schicht wie das Gate (7) vorgesehen ist.

7. Arraysubstrat nach Anspruch 1, wobei die zweite Isolierschicht (4) Harzmaterial aufweist.

8. Arraysubstrat nach Anspruch 7, wobei das Harzmaterial Polymethylmethacrylat und ein lichtempfindliches Agens enthält.

9. Arraysubstrat nach Anspruch 7, wobei die Dicke der zweiten Isolierschicht (4) im Bereich von 1,5 µm bis 2,0 µm liegt.

10. Arraysubstrat nach Anspruch 1, wobei die Erstreckungsrichtung der Datenleitung (11) senkrecht zu einer Erstreckungsrichtung der Gate-Leitung (70) ist und die mehreren Gates (7) mit der kammförmigen Verteilung entlang der Erstreckungsrichtung der Datenleitung (11) angeordnet sind.

11. Verfahren zur Herstellung eines Niedrigtemperatur-Polysilicium-Dünnfilmtransistorarraysubstrats nach den Ansprüchen 1-9, folgende Schritte umfassend:

sequentielles Bilden einer aktiven Schicht (2), einer ersten Isolierschicht (3) und mehrerer Gates (7) und einer Gate-Leitung (70) auf einem Basissubstrat (1);

Bilden einer zweiten Isolierschicht (4), die eine erste Durchkontaktierung und eine zweite Durchkontaktierung auf dem Substrat (1) aufweist, auf dem die aktive Schicht (2), die erste Isolierschicht (3) und die mehreren Gates (7) gebildet werden, wobei die mehreren Gates so gebildet werden, dass sie eine kammförmige Verteilung aufweisen;

Bilden einer Struktur, die eine Source (5), ein Drain (6) und eine Datenleitung (11) auf dem Substrat (1) aufweist, auf dem die zweite Isolierschicht (4) gebildet wird, wobei die Datenleitung (11) die mehreren Gates (7) mit der kammförmigen Verteilung entlang einer Erstreckungsrichtung der Datenleitung (11) vollständig abdeckt; und

Bilden einer Struktur, die eine Pixelelektrode (8) aufweist, auf dem Substrat (1), auf dem die Struktur, die die Source (5) und das Drain (6) aufweist, gebildet wird, wobei die Pixelelektrode (8) mit dem Drain (6) verbunden ist.

12. Verfahren nach Anspruch 10, wobei der Schritt des sequentiellen Bildens einer aktiven Schicht (2), einer ersten Isolierschicht (3) und mehrerer Gates (7) auf einem Basissubstrat (1) Folgendes umfasst:

Abscheiden einer Pufferschicht und eines Dünnfilms aus amorphem Silicium auf dem Substrat (1), Umwandeln des amorphen Siliciums in Niedrigtemperatur-Polysilicium und Bilden einer Struktur, die die aktive Schicht (2) aufweist, durch einen Strukturierungsvorgang;

Bilden einer Struktur der ersten Isolierschicht (3) auf dem Substrat (1), auf dem die aktive Schicht (2) gebildet wird; und

Abscheiden eines Gate-Metall-Dünnfilms auf dem Substrat (1), auf dem die erste Isolierschicht (3) gebildet wird, und Bilden einer Struktur, die die mehreren Gates (7) aufweist, durch einen Strukturierungsvorgang.

13. Verfahren nach Anspruch 10, das ferner die folgenden Schritte aufweist:

Bilden einer dritten Isolierschicht (9) auf dem Substrat (1), auf dem die Struktur der Pixelelektrode (8) gebildet wird; und

Abscheiden eines transparenten, leitenden Dünnfilms auf dem Substrat (1), auf dem die dritte Isolierschicht (9) gebildet wird, und Bilden einer Struktur, die eine gemeinsame Elektrode (10) aufweist, durch einen Strukturierungsvorgang.

14. Verfahren nach Anspruch 11, das ferner folgenden Schritt umfasst:
Bilden einer Struktur einer gemeinsamen Elektrode (10) während des Bildens der Struktur, die die mehreren Gates (7) aufweist.

15. Anzeigevorrichtung, die das Arraysubstrat nach einem der Ansprüche 1 bis 9 aufweist.

Revendications

1. Substrat de matrice de transistors à couche mince de polysilicium à basse température, comprenant
un substrat (1);
une couche active de polysilicium (2) prévue sur le substrat (1) ;
une première couche isolante (3) prévue sur la couche active (2) ;
une pluralité de grilles (7) et une ligne de grille (70) prévues sur la première couche isolante (3) ;
une seconde couche isolante (4) prévue sur la pluralité de grilles (7) ;
une source (5), un drain (6), une ligne de données (11) et une électrode de pixel (8) connectés électriquement au drain (6), qui sont prévus sur la deuxième couche isolante (4),
caractérisé en ce que la pluralité de grilles (7) est formée pour avoir une distribution en forme de peigne ; et
la ligne de données (11) couvre entièrement la pluralité de grilles (7) ayant la distribution en forme de peigne le long d'une direction d'extension de la ligne de données (11).

2. Substrat de matrice selon la revendication 1, comprenant en outre une couche tampon prévue en dessous de la couche active (2).

3. Substrat de matrice selon la revendication 1 ou 2, dans lequel le nombre de grilles de la pluralité de grilles (7) est de deux à cinq.

4. Substrat de matrice selon la revendication 1, comprenant en outre une électrode commune (10) prévue dans la même couche que l'électrode de pixel (8).

5. Substrat de matrice selon la revendication 1, comprenant en outre :

une troisième couche isolante (9) prévue sur l'électrode de pixel (8) ; et

une électrode commune en forme de fente (10) prévue sur la troisième couche isolante (9).

6. Substrat de matrice selon la revendication 1, comprenant en outre une électrode commune (10) prévue dans la même couche que la grille (7).

7. Substrat de matrice selon la revendication 1, dans lequel la seconde couche isolante (4) comprend un matériau en résine.

8. Substrat de matrice selon la revendication 7, dans lequel le matériau de résine comprend du polyméthacrylate de méthyle et un agent photosensible.

9. Substrat de matrice selon la revendication 7, dans lequel l'épaisseur de la deuxième couche isolante (4) est comprise entre 1,5 µm et 2,0 µm.

10. Substrat de matrice selon la revendication 1, dans lequel la direction d'extension de la ligne de données (11) est perpendiculaire à une direction d'extension de la ligne de grille (70),
et la pluralité de grilles (7) ayant la distribution en forme de peigne sont disposées le long de la direction d'extension de la ligne de données (11).

11. Procédé de fabrication d'un substrat de matrice de transistors à couche mince de polysilicium à basse température selon les revendications 1 à 9, comprenant des étapes consistant à :

former séquentiellement une couche active (2), une première couche isolante (3) et une pluralité de grilles (7) et une ligne de grille (70) sur un substrat de base (1) ;

former une seconde couche isolante (4) comprenant un premier via et un second via sur le substrat (1) sur lequel sont formées la couche active (2), la première couche isolante (3) et la pluralité de grilles (7), dans lequel la pluralité de grilles est formée pour avoir une distribution en forme de peigne ;

former un motif comprenant une source (5), un drain (6) et une ligne de données (11) sur le substrat (1) sur lequel la deuxième couche isolante (a) est formée, la ligne de données (11) couvrant entièrement la pluralité de grilles (7) ayant la distribution en forme de peigne le long d'une direction d'extension de la ligne de données (11) ; et

former un motif comprenant une électrode de pixel (8) sur le substrat (1) sur lequel le motif comprenant la source (5) et le drain (6) est formé, l'électrode de pixel (8) étant connectée au drain (6).

12. Procédé selon la revendication 10, dans lequel l'étape de formation séquentielle d'une couche active (2), d'une première couche isolante (3) et d'une pluralité de grilles (7) sur un substrat de base (1) comprend les étapes consistant à :

déposer une couche tampon et un film mince de silicium amorphe sur le substrat (1), convertir le silicium amorphe en polysilicium à basse température et former un motif comprenant la couche active (2) par un processus de formation de motifs ;

former un motif de la première couche isolante (3) sur le substrat (1) sur lequel la couche active (2) est formée ; et

déposer un film mince métallique de grille sur le substrat (1) sur lequel la première couche isolante (3) est formée, et former un motif comprenant la pluralité de grilles (7) par un processus de motif.

13. Procédé selon la revendication 10, comprenant en outre les étapes consistant à :

former une troisième couche isolante (9) sur le substrat (1) sur laquelle le motif de l'électrode de pixel (8) est formé ; et

déposer un film mince conducteur transparent sur le substrat (1) sur lequel la troisième couche isolante (9) est formée, et former un motif comprenant une électrode commune (10) par un processus de formation de motifs.

14. Procédé selon la revendication 11, comprenant en outre une étape consistant à :
former un motif d'une électrode commune (10) tout en formant le motif comprenant la pluralité de grilles (7).

15. Dispositif d'affichage, comprenant le substrat de matrice selon l'une quelconque des revendications 1 à 9.

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