A MULTI-CHANNEL INVERTER FOR A PHOTOVOLTAIC APPARATUS

Abstract

 An inverter for a photovoltaic apparatus, which comprises a DC section, a DC/AC conversion section, an AC section and a control section.
Said DC section includes a plurality of DC input channels each comprising a DC/DC converter electrically connected between input terminals and said output terminals of said DC input channels.
The inverter comprises a measuring circuit arrangement adapted to measure an isolation resistance of the photovoltaic strings electrically connected with said DC input channels, when said inverter operates in predefined test conditions.

Description

[0001] The present invention relates to a multi-channel inverter for a photovoltaic apparatus. Multi-channel inverters are widely used in photovoltaic apparatuses including multiple photovoltaic strings.

[0002] A multi-channel inverter generally comprises a DC section including a plurality of DC input channels receiving DC electric power from corresponding photovoltaic strings, an DC/AC conversion section providing a DC/AC conversion of DC electric power provided by the photovoltaic strings and an AC section providing AC electric power to an electric power distribution grid, for example the mains.

[0003] When the inverter is capable of carrying out MPPT (Maximum Power Point Tracking) functionalities, each DC input channel typically includes a DC/DC converter adapted to receive an input DC voltage from a corresponding photovoltaic string and provide an output DC voltage having a controllable voltage value to the DC/AC conversion section.

[0004] As is known, many types of multi-channel inverters are not provided with electric isolation arrangements (e.g. an electric transformer) adapted to galvanically isolate the DC section and the AC section.

[0005] In these cases, current international regulations lay down that the resistive impedance towards ground (normally referred to as "isolation resistance") of the photovoltaic strings has to be cyclically measured under suitable test conditions of the inverter.

[0006] In most of the cases, the isolation resistance is measured by providing a suitable detection circuit between the input terminals of the DC/AC conversion section and the ground.

[0007] In inverters providing MPPT functionalities, the above-mentioned technical solution is applicable only when the DC input channels have their positive or negative electric lines substantially equipotential.

[0008] However, such a technical solution cannot be adopted when DC/DC converters having a double-level configuration are arranged at the DC input channels to provide relatively high output voltages (i.e. higher than 1 kV) to the DC/AC conversion section. In this case, in fact, diodes are present on both the electric lines of each DC input channel and, consequently, the DC input channels cannot have their positive or second electric lines equipotential.

[0009] In order to solve this problem, various measuring circuit arrangements have been proposed in the state of the art, some examples of which are described in CN106603007B.

[0010] Unfortunately, the experience has shown that currently available solutions do not yet ensure accurate and reliable measurements of the isolation resistance of the photovoltaic strings. Additionally, it is not possible to preventively check whether active components (switches) in the designed measuring arrangements are correctly operating when the isolation resistance measurements are required.

[0011] Of course, the above-mentioned drawbacks may lead to unacceptable and potentially dangerous errors in measuring the isolation resistance of the photovoltaic strings.

[0012] The main aim of the present invention is to provide a multi-channel inverter for a photovoltaic apparatus, which enables the disadvantages described above to be overcome. Within this aim, another object of the present invention is to provide a multi-channel inverter, in which the isolation resistance can be measured in an accurate and reliable manner even when the inverter is designed to provide MPPT functionalities and the DC input channels of the inverter do not have any equipotential electric lines.

[0013] Another object of the present invention is to provide a multi-channel inverter, which has a compact structure with a relatively small size.

[0014] Yet another object of the present invention is to provide a multi-channel inverter, which is easy and inexpensive to produce at industrial level.

[0015] This aim and these objects, together with other objects that will be more apparent from the subsequent description and from the accompanying drawings, are achieved, according to the invention, by an inverter, according to claim 1 and the related dependent claims.

[0016] Characteristics and advantages of the present invention will be more apparent with reference to the description given below and to the accompanying figures, provided purely for explanatory and non-limiting purposes, wherein:

• Fig. 1 schematically illustrates a photovoltaic apparatus including an inverter, according to the present invention;
• Fig. 2 schematically illustrates a partial view of a two-channel inverter, according to the present invention;
• Fig. 2A schematically illustrates a partial view of a multi-channel inverter, according to the present invention;
• Figs. 3-6 schematically illustrate some aspects of the inverter, according to the present invention.

[0017] With reference to the aforesaid figures, the present invention relates to an inverter 1 for a low voltage photovoltaic apparatus 100.

[0018] For the sake of clarity, it is specified that the term "low voltage" refers to operating voltages lower than 1 kV AC and 2 kV DC.

[0019] Referring to figure 1, a photovoltaic apparatus 100 including the inverter 1 is shown. The photovoltaic apparatus 100 comprises one or more photovoltaic strings 200, each of which may comprise one or more photovoltaic panels.

[0020] The photovoltaic strings 200 are electrically connected with the inverter 1 that in turns is electrically connected with an electric power distribution grid 300 (e.g. the mains or a load circuit).

[0021] In general, the inverter 1 is adapted to receive DC electric power from the photovoltaic strings, to convert said DC electric power into AC electric power and to provide said Ac electric power to the electric power distribution grid.

[0022] The inverter 1 comprises a DC section 1A, an DC/AC conversion section 1B and an AC section 1C.

[0023] The DC section 1A includes a DC bus electrically connected with the photovoltaic strings 200 to receive DC electric power from these latter.

[0024] According to the invention, the inverter 1 is of the multi-channel type.

[0025] The DC section 1A thus comprises a DC bus formed by a plurality of DC input channels CH₁, CH₂, CH_N, each of which has an input port adapted to be electrically connected with a corresponding photovoltaic string 200 and an output port electrically connected with the DC/AC conversion section 1B.

[0026] The DC/AC conversion section 1B is electrically connected between the DC section 1A and the AC section 1C.

[0027] Conveniently, the DC/AC conversion section 1B comprises an input port (also referred to as "DC-link") electrically connected in parallel with all the output ports of the DC input channels CH₁, CH₂, CH_N of the DC section 1A and an output port electrically connected with the AC section 1C

[0028] Preferably, the DC/AC conversion section 1B comprises one or more DC/AC converters adapted to provide a DC/AC conversion of DC electric power provided by the photovoltaic strings 200 into AC electric power.

[0029] The AC section 1C of the inverter 1 is electrically connected with the DC/AC conversion section 1B and the electric power distribution grid 300.

[0030] Preferably, the AC section 1C comprises an input port electrically connected with the output port of the DC/AC conversion section 1B and a suitable AC bus adapted to deliver the AC electric power provided by the DC/AC conversion section 1B to the electric power distribution grid 300.

[0031] In general, the DC/AC conversion section 1B and the AC section 1C of the inverter 1 may be of known type and will not be further described in further details for the sake of brevity.

[0032] In figure 2, an embodiment of the inverter 1 having two DC input channels CH₁, CH₂ is shown while, in figure 2A, an embodiment of the inverter 1 having a generic number of N (N > 2) DC input channels CH₁, CH₂, CH_N is shown.

[0033] Each DC input channel CH₁, CH₂, CH_N comprises an input port formed by a first input terminal IT+ (e.g. having a positive voltage polarity) and a second input terminal IT- (e.g. having a negative voltage polarity) electrically coupleable with output terminals of a corresponding photovoltaic string 200.

[0034] Each DC input channel CH₁, CH₂, CH_N comprises an output port formed by a first output terminal OT+ (e.g. having a positive voltage polarity) and a second output terminal OT- (e.g. having a negative voltage polarity).

[0035] The output terminals OT+ and OT- of each DC input channel CH₁, CH₂, CH_N are electrically coupled respectively with third and fourth input terminals T+ and T- (e.g. having a positive and negative voltage polarity, respectively) of the DC/AC conversion section 1B, which form the input port of this latter section of the inverter 1. In this way, the output ports of the DC input channels CH₁, CH₂, CH_N are electrically connected in parallel with the input port of the DC/AC conversion section 1B.

[0036] Each DC input channel CH₁, CH₂, CH_N comprises a first electric line L+ (e.g. having a positive voltage polarity) between and including the first input and output terminals IT+ and OT+ and a second electric line L- (e.g. having a negative voltage polarity) between and including the second input and output terminals IT- and OT-.

[0037] According to the invention, the DC section 1A comprises a DC/DC converter CV₁, CV₂, CV_N for each DC input channel CH₁, CH₂, CH_N.

[0038] Each DC/DC converter CV₁, CV₂, CV_N is electrically connected between the input terminals IT+, IT- and the output terminals OT+, OT- of the corresponding DC input channel CH₁, CH₂, CH_N.

[0039] Each DC/DC converter CV₁, CV₂, CV_N comprises one or more first components electrically connected in series with the first input and output terminals IT+, OT+ of the corresponding DC input channel CH₁, CH₂, CH_N and are part of the first electric line L+ of said DC input channel.

[0040] Each DC/DC converter CV₁, CV₂, CV_N comprises one or more second components electrically connected in series with the second input and output terminals IT-, OT- of the corresponding DC input channel CH₁, CH₂, CH_N and are part of the second electric line L- of said DC input channel.

[0041] According to some embodiments of the invention, said first components may include at least a diode arranged in such a way to allow the circulation of a current along the first electric line L+ with a flow direction going from the first input terminal IT+ to the first output terminal OT+ and/or said second components may include at least a diode arranged in such a way to allow the circulation of a current along the second electric line L- with a flow direction going from the second output terminal OT- to the second input terminal IT-.

[0042] Preferably, as shown in figures 2 and 2A, each DC/DC converter CV₁, CV₂, CV_N has a so-called "two-level boost configuration".

[0043] In the embodiments of figures 2 and 2A, each DC/DC converter CV₁, CV₂, CV_N comprises a first inductance L1 and a first diode D1 arranged along the first electric line L+ of the corresponding DC input channel CH₁, CH₂, CH_N.

[0044] The first inductance L1 is electrically connected between the first input terminal IT+ and a first intermediate node N1 of the first electric line L+ whereas the first diode D1 has its anode electrically connected with the first intermediate node N1 and its cathode electrically connected with the first output terminal OT+.

[0045] In the embodiments of figures 2 and 2A, each DC/DC converter CV₁, CV₂, CV_N comprises a second inductance L2 and a second diode D2 arranged along the second electric line L- of the corresponding DC input channel CH₁, CH₂, CH_N.

[0046] The second inductance L2 is electrically connected between the second input terminal IT- and a second intermediate node N2 of the second electric line L- whereas the second diode D2 has its cathode electrically connected between the second intermediate node N2 and its anode electrically connected with the second output terminal OT-.

[0047] In the embodiments of figures 2 and 2A, each DC/DC converter CV₁, CV₂, CV_N further comprises an input capacitance C0 electrically connected in parallel with the input terminals IT+, IT- of the corresponding DC input channel CH₁, CH₂, CH_N, a first switch S1 electrically connected between the first intermediate node N1 and a third intermediate node N3, a first output capacitance C1 electrically connected between the first output terminal OT+ and the third intermediate node N3, a second switch S2 electrically connected between the second intermediate node N2 and the third intermediate node N3 and a second output capacitance C2 electrically connected between the second output terminal OT- and the third intermediate node N3.

[0048] The first and second switches S1 and S2 (e.g. MOSFETs) of each DC/DC converter CV₁, CV₂, CV_N generally operate in response to first control signals (not shown) received in input. In the embodiments of figures 2 and 2A, the third intermediate nodes N3 of the DC/DC converters CV₁, CV₂, CV_N of all the DC input channels CH₁, CH₂, CH_N are electrically connected one with another in such a way to be equipotential.

[0049] As it may be noticed, in the embodiments of figures 2 and 2A, the first diode D1 and the first inductance L1 therefore constitute the above-mentioned first components of the DC/DC converter CV₁, CV₂, CV_N, which are electrically connected in series with the first input and output terminals IT+, OT+ of the corresponding DC input channel CH₁, CH₂, CH_N along the first electric line L+ of said DC input channel.

[0050] On the other hand, the second diode D2 and the second inductance L2 constitute the above-mentioned second components of the DC/DC converter CV₁, CV₂, CV_N, which are electrically connected in series with the second input and output terminals IT-, OT- of the corresponding DC input channel CH₁, CH₂, CH_N along the second electric line L- of said DC input channel.

[0051] According to the invention, the DC section 1A of the inverter 1 comprises a measuring circuit arrangement for measuring the isolation resistance R_ISO of the photovoltaic strings 200, when said inverter operates at predefined test conditions.

[0052] For the sake of clarity, it is specified that the term "isolation resistance" identifies the overall resistive impedance R_ISO towards ground of the photovoltaic strings 200, which is substantially given by the parallel of the single resistive components R₁, R₂ R_N of the impedances towards ground of the single photovoltaic strings 200.

[0053] For the sake of clarity, it is specified that, when it operates under said predefined test conditions, the inverter 1 carries out no power conversion functionalities.

[0054] Thus, when the inverter 1 operates under said predefined test conditions:

• each DC/DC converter CV₁, CV₂, CV_N of the DC section 1A is deactivated and has its active elements (switches S1 and S2) in an interdiction state;
• the DC/AC converters of the DC/AC conversion section 1B are deactivated and have their active elements (switches) in an interdiction state;
• a DC current, which is fed by the corresponding photovoltaic string 200, may flow along the first and second electric lines L+ and L- of each DC input channel CH₁, CH₂, CH_N.

[0055] As it may be noticed, in the embodiments of figures 2 and 2A, when inverter 1 operates under said test conditions, a DC current may flow along the electric line L+ and L- of the corresponding DC input channel CH₁, CH₂, CH_N only.

[0056] The switches S1 and S2 of each DC/DC converter CV₁, CV₂, CV_N are in an interdiction state and are equivalent to open circuits.

[0057] The first intermediate node N1 of the first electric line L+ is substantially equipotential (namely short-circuited, apart the presence of possible parasitic resistances) with the first input terminal IT+ whereas the second intermediate node N2 of the second electric line L- is substantially equipotential (namely short-circuited, apart the presence of possible parasitic resistances) with the second input terminal IT-. The first and second inductances L1, L2 are substantially equivalent to short-circuits as their impedance is virtually null for very low or null operating frequencies.

[0058] No DC currents flow along the input capacitance C0 and the output capacitances C1 and C2. These latter which are substantially equivalent to open circuits as their impedance is virtually infinite for very low or null operating frequencies.

[0059] According to the invention, the above-mentioned measuring circuit arrangement comprises a switch circuit SW₁, SW₂, SW_N for each DC input channel CH₁, CH₂, CH_N.

[0060] Each switch circuit SW₁, SW₂, SW_N is electrically connected with a common electric node N0 that conveniently operates a different voltage potentials with respect to the third input terminal T+ of the DC/AC conversion section 1B, when the inverter 1 operates in the above-mentioned predefined test conditions and at least one of said switch circuits is in an interdiction state.

[0061] In practice, each switch circuit SW₁, SW₂, SW_N is electrically connected with a common node N0 that is not electrically connected in a direct matter with the third input terminal T+ of the DC/AC conversion section 1B so as to be equipotential with said third input terminal and at least one of said switch circuits is in an interdiction state.

[0062] This solution is quite advantageous as it allows substantially improving the accuracy of the isolation resistance measurements, which may otherwise be affected by relevant errors, if the common node was always equipotential with the third input terminal T+ of the DC/AC conversion section 1B, as it occurs in some known solutions of the state of the art.

[0063] According to some embodiments of the invention, each switch circuit SW₁, SW₂, SW_N is electrically connected with the first input terminal IT+ of the corresponding DC input channel CH₁, CH₂, CH_N or with an electric node (e.g. the first intermediate electric node N1) of the first electric line L+ of the corresponding DC input channel CH₁, CH₂, CH_N. Said electric node N1 is short-circuited (apart the presence of possible parasitic resistances) with the first input terminal IT+, when the inverter 1 operates at the above-mentioned test conditions. According to alternative embodiments of the invention, each switch circuit SW₁, SW₂, SW_N is electrically connected with the second input terminal IT- of the corresponding DC input channel CH₁, CH₂, CH_N or with an electric node (e.g. the second intermediate electric node N2) of the second electric line L- of the corresponding DC input channel CH₁, CH₂, CH_N. Said electric node N2 is short-circuited (apart the presence of possible parasitic resistances) with the first input terminal IT-, when the inverter 1 operates at the above-mentioned test conditions.

[0064] Preferably, each switch circuit SW₁, SW₂, SW_N comprises a first resistive element R_S and a third switch S_SW (e.g. a MOSFET) electrically connected in series between the first input terminal IT+ and the common electric node N0 (figure 3).

[0065] Preferably, each switch circuit SW₁, SW₂, SW_N comprises a first driving circuit DV_SW to suitably drive the third switch Ssw in response to second control signals Csw received in input. According to the invention, the above-mentioned measuring circuit arrangement comprises a first detection circuit 10.

[0066] The first detection circuit 10 is adapted to provide first detection signals D1 indicative of a first voltage V_ISO between the third input terminal T+ of the DC/AC conversion section 1B and the ground, when the inverter 1 operates at the above-mentioned test conditions (figures 2, 2A, 4).

[0067] As it may be easily understood, the first voltage V_ISO is indicative of the voltage difference between the operative voltage of the third input terminal T+ and the ground voltage, when the inverter 1 operates at the above-mentioned test conditions.

[0068] Preferably, the first detection circuit 10 comprises a first resistive element R₁₀ and a fourth switch S₁₀ (e.g. a MOSFET) electrically connected in series between the third input terminal T+ and the ground.

[0069] Preferably, the first detection circuit 10 comprises a second driving circuit DV₁₀ to suitably drive the fourth switch S₁₀ in response to third control signals C₁₀ received in input. Preferably, the first detection circuit 10 further comprises a first detection output M₁₀, at which it makes available the first detection signals D1.

[0070] As it will better emerge from the following, the arrangement of the first detection circuit 10 is essential to measure the isolation resistance R_ISO of the photovoltaic strings 200.

[0071] Preferably, the above-mentioned measuring circuit arrangement comprises a second detection circuit 20 adapted to provide second detection signals D2 indicative a second voltage V_TEST between the common electric node N0 and the fourth input terminal T- of the DC/AC conversion section 1B, when the inverter 1 operates at the above-mentioned test conditions (figures 2, 2A, 6).

[0072] As it may be easily understood, the second voltage V_TEST is indicative of the voltage difference between the operating voltage of the common electric node N0 and the operating voltage of the fourth input terminal T-, when the inverter 1 operates in the above-mentioned test conditions.

[0073] Preferably, the second detection circuit 20 comprises a second resistive element R₂₀ electrically connected in series between the common electric node N0 and the fourth input terminal T- and an operational circuit OP electrically connected in parallel with the second resistive element R₂₀ (figure 6).

[0074] Preferably, the operational circuit OP comprises an operational amplifier and a suitable polarization circuit CP electrically connected with the fourth input terminal T- to suitably drive said operational amplifier.

[0075] Preferably, the second detection circuit 20 comprises a second detection output M₂₀, at which it makes available the second detection signals D2.

[0076] Preferably, the above-mentioned measuring circuit arrangement comprises a third detection circuit 30 for each DC input channel CH₁, CH₂, CH_N.

[0077] Each third detection circuit 30 is adapted to provide third detection signals D3 indicative of a third voltage V_IN between the first and second input terminals IT+, IT- of the corresponding DC input channel CH₁, CH₂, CH_N, when the inverter 1 operates in the above-mentioned test conditions.

[0078] As it may be easily understood, the third voltage V_IN is indicative of the voltage difference between the operating voltages of the first and second input terminals IT+, IT- of the corresponding DC input channel CH₁, CH₂, CH_N, when the inverter 1 operates in the above-mentioned test conditions.

[0079] Preferably, each third detection circuit 30 is comprises a resistive shunt R₃₀ electrically connected in parallel with the first and second input terminals IT+, IT- of the corresponding DC input channel CH₁, CH₂, CH_N (figure 5).

[0080] Preferably, each third detection circuit 30 comprises a third detection output M₃₀, at which it makes available the third detection signals D3.

[0081] As it will better emerge from the following, the arrangement of the second and third detection circuits 20, 30 is quite important to check the operating status of each switching circuit SW1, SW2, SWN, preferably before carrying out a measurement of the isolation resistance R_ISO of the photovoltaic strings 200.

[0082] According to the invention, the inverter 1 comprises a control section 1D operatively associated with the DC section 1A, the DC/AC conversion section 1B and the AC section 1C to control the operation of these latter.

[0083] The control section 1D may include one or more control boards or units, each of which may include one or more digital processing devices (e.g. microcontrollers, DSPs, and the like) and suitable electronic circuits of digital or analog type.

[0084] Conveniently, the control section 1D comprises suitable data processing means to carry out its functionalities, some of which (the first, second and third processing means 51, 52, 53) will be better described in the following.

[0085] If implemented in a digital manner, said data processing means may comprise suitably arranged software instructions stored in a medium and executable by one or more digital processing devices of the control section 1D to perform said functionalities.

[0086] If implemented in analog manner, said data processing means may comprise electronic circuits suitably arranged to perform said functionalities.

[0087] Additional variant solutions to implement said data processing means are available to the skilled person.

[0088] Preferably, the control section 1D is operatively coupled with the first and second switches S1, S2 of each DC/DC converter CV₁, CV₂, CV_N and it is capable to provide first control signals (not shown) to control the operation of these latter switches.

[0089] Conveniently, the control section 1D is operatively coupled with each switch circuit SW₁, SW₂, SW_N and it is capable to provide second control signals Csw to control the operation of the third switch S_SW of each switch circuit SW₁, SW₂, SW_N.

[0090] Conveniently, the control section 1D is operatively coupled with the above-mentioned first detection circuit 10 (namely with the first detection output M₁₀ and second driving circuit DV₁₀ thereof) to receive the first detection signals D1 and to provide third control signals C₁₀ to control the operation of the fourth switch S₁₀.

[0091] Preferably, the control section 1D is operatively coupled with the above-mentioned second detection circuit 20 (namely with the second detection output M₂₀ thereof) to receive the second detection signals D1.

[0092] Preferably, the control section 1D is operatively coupled with the above-mentioned third detection circuit 30 (namely with the third detection output M₃₀ thereof) to receive the third detection signals D3.

[0093] Preferably, the control section 1D comprises first data processing means 51 adapted to carry out MPPT (Maximum Power Point Tracking) functionalities by suitably controlling the DC/DC converters CV₁, CV₂, CV_N of the input channels CH₁, CH₂, CH_N and the DC/AC converters of the DC/AC conversion section 1B.

[0094] In order to carry out said MPPT functionalities, the first data processing means 51 may implement algorithms or procedures of known type that will be not described in the following for the sake of brevity.

[0095] Preferably, the control section 1D comprises second data processing means 52 configured to carry out a test procedure P_T adapted to test the operating conditions of a switch circuit SW₁, SW₂, SW_N operatively associated with a given DC input channel CH₁, CH₂, CH_N of the DC section 1A.

[0096] The test procedure P_T will now be described in details in accordance to a preferred embodiment of the invention.

[0097] The test procedure P_T comprises a step of commanding the inverter 1 to take or maintain the above-mentioned predefined test conditions.

[0098] In order to implement this step, the second data processing means conveniently provides suitable control signals to the switches S1, S2 of each DC/DC converter CV₁, CV₂, CV_N and suitable control signals to the DC/AC converters of the DC/AC conversion section 1B to maintain said switches i an interdiction state.

[0099] The test procedure P_T then comprises the step of selecting an input channel (for example the input channel CH₁ - figures 2, 2A).

[0100] The test procedure P_T then comprises the step of commanding the switching circuit SW₁ operatively associated with the selected input channel CH₁ to switch in a conduction state and the step of commanding the switching circuits SW₂, SW_N operatively associated with the input channels CH₂, CH_N different from the selected input channel CH₁ to switch in an interdiction state.

[0101] In order to implement this step, the second data processing means conveniently provides suitable control signals Csw to the driving circuits DV_SW of the switching circuits SW₁, SW₂, SW_N in such a way that the corresponding switches S_SW are operated in an interdiction state or in a conduction state.

[0102] Following the above-mentioned steps, the common node N0 becomes substantially equipotential with the first input terminal IT+ of the selected DC input channel CH₁ and its decoupled from the first input terminals IT+ of the remaining DC input channels CH₂, CH_N. The test procedure P_T then comprises the step of receiving the second detection signals D2 from said the detection circuit 20 and the step of receiving the third detection signals D3 from said third detection circuit 30.

[0103] The second detection signals D2 include one or more first voltage values V_A indicative of the detected second voltage V_TEST whereas the third detection signals D3 include one or more second voltage values V_B indicative of the detected third voltage V_IN.

[0104] The test procedure P_T then comprises the step of comparing the above-mentioned first and second voltage values V_A, V_B.

[0105] As the common node N0 is substantially equipotential with the first input terminal IT+ of the selected DC input channel CH₁, the second and third voltages V_TEST and V_IN should have similar first and second voltage values V_A, V_B, if the switching circuit SW₁ operatively associated with the selected input channel CH₁ works properly. Otherwise, a substantial voltage difference between the first and second voltages V_A, V_B will be certainly present.

[0106] The test procedure P_T then comprises the step of determining a fault condition of the switching circuit SW₁ operatively associated with the selected input channel CH₁, if a voltage difference value between the second and third second voltages V_TEST, V_IN exceeds a given voltage threshold value V_TH.

[0107] In practice, a fault condition of the switching circuit SW₁ operatively associated with the selected input channel CH₁ is determined if the following condition occurs:

where V_A is a first voltage value of the detected second voltage V_TEST, V_B is a second voltage value of the detected third voltage V_IN and V_TH is the above-mentioned threshold value. Preferably, the second data processing means 52 are configured to carry out the above-described test procedure P_TEST for each DC input channel CH₁, CH₂, CH_N.

[0108] At each execution cycle of the test procedure P_T, the second processing means 52 will conveniently select a different DC input channel CH₁, CH₂, CH_N to check the actual operative status of the corresponding switching circuit SW₁, SW₂, SW_N.

[0109] It is evidenced that at each execution cycle of the test procedure P_T, the common electric node N0 always operates a different voltage potentials with respect to the third input terminal T+ of the DC/AC conversion section 1B, as N-1 switch circuits among the switching circuits switching circuit SW₁, SW₂, SW_N are in an interdiction state.

[0110] The above-mentioned test procedure P_T allows testing the actual operating status of the switching circuits SW₁, SW₂, SW_N operatively associated with the DC input channels CH₁, CH₂, CH_N.

[0111] Conveniently, the actual operating status of the switching circuits SW₁, SW₂, SW_N may be checked by carrying above-mentioned test procedure P_T before measuring the isolation resistance R_ISO of the photovoltaic strings 200

[0112] In this way, relevant measurement errors of the isolation resistance R_ISO of the photovoltaic strings 200 may be preventively avoided with relevant advantages in terms of reliability and accuracy.

[0113] Preferably, the control section 1D comprises third data processing means 53 configured to carry out a measuring procedure P_M adapted to measure the isolation resistance R_ISO of the photovoltaic strings 200.

[0114] The measuring procedure P_M will now be described in details in accordance to a preferred embodiment of the invention.

[0115] The measuring procedure P_M comprises a step of commanding the inverter 1 to take or maintain the above-mentioned predefined test conditions.

[0116] In order to implement this step, the second data processing means conveniently provides suitable control signals to the switches S1, S2 of each DC/DC converter CV₁, CV₂, CV_N and suitable control signals to the DC/AC converters of the DC/AC conversion section 1B to maintain said switches in an interdiction state.

[0117] The measuring procedure P_M comprises a step of commanding the first switch S₁₀ of the first detection circuit 10 to switch in an interdiction state.

[0118] In order to implement this step, the third data processing means 53 conveniently provides suitable control signals C₁₀ to the driving circuits DV₁₀ of the switch S₁₀.

[0119] The measuring procedure P_M comprises a step of receiving the first detection signals D1 indicative of the first voltage V_ISO. The first detection signals D1 include one or more third voltage values V_C indicative of the detected first voltage V_ISO.

[0120] The measuring procedure P_M then comprises a step of commanding the first switch S₁₀ of the first detection circuit 10 to switch in a conduction state.

[0121] In order to implement this step, the third data processing means 53 conveniently provides suitable control signals C₁₀ to the driving circuits DV₁₀ of the switch S₁₀.

[0122] The measuring procedure P_M comprises a further step of receiving the first detection signals D1 indicative of the first voltage V_ISO. The first detection signals D1 include one or more fourth voltage values V_D indicative of the detected first voltage V_ISO.

[0123] The measuring procedure P_M then comprises a step of calculating the isolation resistance R_ISO of the photovoltaic strings 200 basing on the third and fourth voltage values V_C, V_D.

[0124] In order to calculate the isolation resistance R_ISO, the third processing means 53 may adopt known algorithms of know type.

[0125] As an example, the isolation resistance R_ISO may be calculated as:

where V_C is a third voltage value of the detected first voltage V_ISO with the switch S₁₀ in interdiction state, V_D is a third voltage value of the detected first voltage V_ISO with the switch S₁₀ in conduction state and R₁₀ is the known resistance value of the first resistive element R₁₀ of the first detection circuit 10.

[0126] The measuring procedure P_M allows measuring the isolation resistance of the photovoltaic strings 200 in a simple manner by carrying out subsequent measurements of a single circuit point (the third input terminal T+ of the DC/AC conversion section 1B) with respect to the ground.

[0127] This constitutes an important advantages with respect to known MPPT inverters the state of the art where the voltages of multiple points of the DC section have to be measured to calculate the isolation resistance of the photovoltaic strings.

[0128] The present invention allows achieving the intended aims and objects.

[0129] The inverter 1 is provided with a measuring circuit arrangement that allows measuring the isolation resistance R_ISO of the photovoltaic strings 200 in an accurate and reliable manner. The measuring circuit arrangement employed in the inverter 1 is particularly adapted for use in an inverters is capable of providing MPPT functionalities and having the DC input channels CH1, CN2, CHN without equipotential lines in common.

[0130] The inverter 1 has a compact structure with a relatively small size. The above-mentioned measuring circuit arrangement may in fact be easily integrated in the DC section 1A and it may employ MOSFETs or equivalent switching devices for its practical implementation.

[0131] The inverter 1 can be easily manufactured at industrial level with highly automated operations at competitive costs with respect to known solutions of the state of the art.

Claims

1. An inverter (1) for a photovoltaic apparatus (100), said inverter comprising a DC section (1A), a DC/AC conversion section (1B), an AC section (1C) and a control section (1D), wherein said DC section includes a plurality of DC input channels (CH₁, CH₂, CH_N), each DC input channel comprising:

- first and second input terminals (IT+, IT-) adapted to be electrically connected with a corresponding photovoltaic string (200);

- first and second output terminals (OT+, OT-) electrically connected with a third input terminal (T+) and a fourth input terminal (T-) of said DC/AC conversion section (1B), respectively;

- a first electric line (L+) including said first input and output terminals (IT+, OT+) and a second electric line (L-) including said second input and output terminals (IT-, OT-);

- a DC/DC converter (CV₁, CV₂, CV_N) electrically connected between said input terminals and said output terminals;

characterised in that said DC section (1A) comprises a measuring circuit arrangement adapted to measure an isolation resistance (R_ISO) of said photovoltaic strings (200), when said inverter operates in predefined test conditions, said measuring arrangement comprising:

- for each DC input channel (CH₁, CH₂, CH_N), a switch circuit (SW₁, SW₂, SW_N) electrically connected with a common electric node (N0) operating at a different voltage potentials with respect to the third input terminal (T+) of said DC/AC conversion section (1B), when said inverter operates in said test conditions and at least one of said switch circuits is in an interdiction state, said switch circuit (SW₁, SW₂, SW_N) being further electrically connected with:

- said first input terminal (IT+) or an electric node (N1) of said first electric line (L+) that is short-circuited with said first input terminal (IT+), when said inverter operates in said test conditions; or

- said second input terminal (IT-) or an electric node (N2) of said second electric line (L-) that is short-circuited with said second input terminal (IT-), when said inverter operates in said test conditions;

- a first detection circuit (10) adapted to provide first detection signals (D₁₀) indicative of a first voltage (V_ISO) between the third input terminal (T+) of said DC/AC conversion section (1B) and the ground, when said inverter operates in said test conditions.

2. Inverter, according to claim 1, characterised in that said first detection circuit (10) comprises a first resistive element (R₁₀) and a switch (S₁₀) electrically connected in series between the third input terminal (T+) of said DC/AC conversion section (1B) and the ground.

3. Inverter, according to one or more of said previous claims, characterised in that said measuring circuit arrangement comprises a second detection circuit (20) adapted to provide second detection signals (D2) indicative a second voltage (V_TEST) between said common electric node (N0) and the fourth input terminal (T-) of said DC/AC conversion section (1B), when said inverter operates in said test conditions.

4. Inverter, according to claim 3, characterised in that said second detection circuit (20) comprises a second resistive element (R₂₀) electrically connected in series between said common electric node (N0) and the fourth input terminal (T-) of said DC/AC conversion section (1B) and an operational circuit (OP) electrically connected in parallel with said second resistive element (R₂₀).

5. Inverter, according to one or more of the previous claims, characterised in that said measuring circuit arrangement comprises, for each DC input channel (CH₁, CH₂, CH_N), a third detection circuit (30) adapted to provide third detection signals (D3) indicative of a third voltage (V_IN) between the first and second input terminals (IT+, IT-) of said DC input channel, when said inverter operates in said test conditions.

6. Inverter, according to claim 5, characterised in that said third detection circuit (30) comprises a resistive shunt (R₃₀) electrically connected in parallel with the first and second input terminals (IT+, IT-) of said DC input channel (CH₁, CH₂, CH_N).

7. Inverter, according to one or more of the previous claims, characterised in that said control section (ID) comprises first data processing means (51) configured to carry out MPPT functionalities.

8. Inverter, according to one or more of the previous claims, characterised in that said control section (ID) comprises second data processing means (52) configured to carry out a test procedure (P_T) adapted to test operating conditions of a switch circuit (SW₁, SW₂, SW_N) operatively associated with a DC input channel (CH₁, CH₂, CH_N), said test procedure including the following steps:

- commanding said inverter (1) to take or maintain said predefined test conditions;

- selecting an input channel (CH₁);

- commanding the switching circuit (SW₁) operatively associated with the selected input channel (CH₁) to switch in a conduction state;

- commanding the switching circuits (SW₁, SW₂, SW_N) operatively associated with the input channels (CH₂, CH_N) different from the selected input channel (CH₁) to switch in an interdiction state;

- receiving said second detection signals (D2) including one or more first voltage values (V_A) indicative of said second voltage (V_TEST);

- receiving said third detection signals (D3) including one or more second voltage values (V_B) indicative of said third voltage (V_IN);

- comparing said second voltage values (V_A) with said third voltage values (V_B);

- determining a fault condition of the switching circuit (SW₁) operatively associated with the selected input channel (CH₁), if a voltage difference value between said second and third second voltage values (V_A, V_B) exceeds a given voltage threshold.

9. Inverter, according to claim 8, characterised in that said second data processing means are configured to carry out said test procedure (P_TEST) for each DC input channel (CH₁, CH₂, CH_N).

10. Inverter, according to one or more of the claims from 2 to 9, characterised in that said control section(1D) comprises third data processing means configured to carry out a measuring procedure (P_M) to measure the isolation resistance (R_ISO) of said photovoltaic strings (200), said detection procedure including the following steps:

- commanding said inverter (1) to take or maintain said predefined test conditions;

- commanding the first switch (S₁₀) of said first detection circuit (10) to switch in an interdiction state;

- receiving said first detection signals (D1) including one or more third voltage values (Vc) indicative of said first voltage (V_ISO);

- commanding the first switch (S₁₀) of said first detection circuit (10) to switch in a conduction state;

- receiving said first detection signals (D1) including one or more fourth voltage values (V_D) indicative of said first voltage (V_ISO);

- calculating said an isolation resistance value (R_ISO) basing on said third and fourth voltage values (V_C, V_D).

11. Inverter, according to one or more of the previous claims, characterised in that said DC/DC converter (CV₁, CV₂, CV_N) has a two-level boost configuration.

12. A photovoltaic apparatus (100) characterised in that it comprises an inverter (1), according to one or more of the previous claims.

Drawing