[0001] This invention relates to a semiconductor circuit arrangement for controlling current
transmitted through a controlled device.
[0002] In the prior art, the current in a controlled device such as a semiconductor light
emitting diode (LED) has been regulated by a control circuit containing an insulated
gate field effect transistor (IGFET) driver switch of relatively very large transconductance
in series with a ballast resistor. The IGFET driver is typically formed in a semiconductive
silicon chip in accordance with standard MOS (metal-oxide-semiconductor) technology.
During operation, if the voltage drop across the IGFET driver in its "on" condition
is relatively small compared with applied voltage, the brightness of the LED in its
"on" condition is somewhat stabilized by the ballast resistor. However, such a control
circuit suffers from poor current regulation, whereby the current in the LED during
operation can fluctuate by as much as a factor of 3 when the voltage of the external
power supply, of typically about 5 or 6 volts, fluctuates by only 20 percent. Although
this fluctuation in current can be reduced by using larger voltages for the power
supply in conjunction with a larger ballast resistor, such an approach to the current
fluctuation problem still suffers from the requirement of a physically relatively
large IGFET driver. This device, which consumes an undesirably large amount of semiconductive
silicon chip area, is required in order to keep the driver resistance, and hence the
driver voltage drop, relatively small (0.5 volt drop) for the desired LED operating
current. Moreover, ordinary processing variations in the manufacture of the IGFET
driver of the prior art circuit cause corresponding variations in the LED operating
current, thereby adversely affecting either the brightness or the lifetime of the
LED on account of, respectively, either too little or too much operating current.
It would therefore be desirable to have a control circuit for stabilizing the operating
current in an LED, which mitagates the shortcomings of the prior art.
[0003] In accordance with the present invention the current in a controlled device such
as an LED is stabilized by a semiconductor circuit arrangement which includes transistor
switch means having feedback means operable on the control input of the input thereof
for controlling the current flowing through the transistor switch means and thus through
the controlled device when connected in series therewith. Preferably the feedback
means is of comparator form for stabilizing a node of the series circuit in dependence
upon a comparison of the node voltage and a reference voltage. By reason of the feedback
means, the transistor switch means can operate with a relatively large source-drain
voltage, typically of about 5 volts; therefore, for a given operating current in the
thereby controlled (LED) device the transistor switch means can now have a relatively
high resistance, thereby reducing the required amount of semiconductor chip area therefor.
[0004] In a specific embodiment of the invention, an LED is connected in series with a ballast
resistor and the high current path (source-drain) of an IGFET driver switch (Q
i). The node between the IGFET driver and the series connection of the LED and Ballast
resistor is connected through a comparator type feedback network back to the low current
control (gate) terminal of the IGFET driver. This control terminal of the IGFET driver
is also connected through the high current path of an auxiliary control IGFET (Q2)
switch to a voltage source, the low current control terminal of this auxiliary IGFET
being connected to an input terminal for application thereto of input signals to turn
the LED "on" and "off".
[0005] This invention together with its features, objects, and advantages will be better
understood from the following exemplary embodiment which is described in conjunction
with the accompanying single figure drawing which is a schematic circuit diagram of
a semiconductor circuit arrangement for regulating the current in a semiconductor
LED in accordance with a specific embodiment of the invention.
[0006] As shown in the drawing, a semiconductor LED 10 has one of its terminals connected
to a voltage source V
GG and another of its terminals connected to a ballast resistor R. As one example, the
circuit parameters will be described in terms of P-MOS technology . Typically, the
source V
GG is approximately -12 volts, and the resistor R is approximately a thousand ohms.
The LED is characterized by an operating "on" current of about 10 milliamperes with
an operating voltage drop of about 2 to 3 volts. The LED and the resistor R are connected
in series with the high current (i.e. source-drain) path of an IGFET driver Q
1 to another voltage source V
SS of about +5 volt. In its "on" state, the driver Q
1 has a resistance advantageously equal to about R/2 or less.
[0007] As further shown in the drawing, the IGFETs Q
3, Q
4, Q
5 and Q
6 are in a comparator feedback network arrangement for stabilizing the voltage at node
11 located between R and Q
l. For this purpose, the node 11 is connected to a low current (i.e. gate) terminal
of Q
6 whose high current path connects VGG to a node 13. The node 13 is connected to V
SS through the high current path of Q
3 whose gate terminal is grounded (V=O). The gate terminal of the driver Q
I is connected to a node 12 which is connected through Q
5 to V
GG and through Q
4 to the node 13. The IGFET Q
5 is in a diode configuration; that is, the drain and gate terminals of Q
5 are shorted together, so that Q
5 behaves as a diode which tends to conduct current only in the direction toward the
source V
GG. On the other hand, the gate terminal of Q
4 is connected to ground serving as a reference potential.
[0008] The node 12 is further connected to V
SS through the high current path of Q
2. The gate of Q
2 is connected to an input signal source 20 which provides signals for turning Q
2 "on" and "off". As more fully explained below, when Q
2 is "on", then Q
1 is "off" and hence the LED 10 is also "off"; and when Q
2 is "off", then Q
1 is "on" and hence the LED 10 is also "on". Thus, the feedback arrangement acts as
a signal inverter as well as a current stabilizer.
[0009] For optimum operation, the transconductance ratios
B21 B31 B
4, B
5 and
B6 of the
IGFETs Q2, Q
3,
Q4, Q
5 and Q
6, respectively, should satisfy the following: B
5 should be much less than B
3; B
3 should be much less than either B
4 and B
6; and B
4 and B
6 should be much less than B
2. By "much less than" is meant less than by preferably a factor of 10, but in any
event at least by a factor of 2 or 5. For example, by way of an illustrative example
only, suitable approximate values for the B's are: B
5 = 2 x 10
-6 mho/V; B
3 =
15 x 10
-6 mho/V; B
4 - B
6 = 100 x 10 mho/V; and B
2 = 250 x 10
-6 mho/V. Moreover, the transistor Q
1 is advantageously characterized by moderately high B
1: for a 10 milliamp LED current, a suitable approximate value is B
1 = 250 x 10
-6 mho/volt. In the absence of the comparator feedback circuit, the required transconductance
of the IGFET driver would be about 1,200 x 10
-6 mho/volt. Operation of the circuit shown in the drawing can be understood from the
following considerations. Starting from a condition in which the LED and the driver
Q
1 are both "off" in the presence of a signal from the source 20 sufficient to maintain
Q
2 in its "on" state, it will first be shown that this condition is stable; and it will
then be shown that a signal applied that is sufficient to switch and maintain Q
2 in its "off" state will also switch and maintain both the driver Q
1 and the LED "on" in a stabilized current condition. In order to explain this operation,
it is to be noted that when at first the input signal maintains Q
2 in its "on" state, then the driver Q
l will thus be in its "off" state and hence the LED will also be in its "off" state.
Under these conditions, the node 12 tends to remain at essentially the potential V
SS by virtue of the connection of this node to the source V
SS through the relatively high B IGFET Q
2. This connection is through the transistor of the highest B in the comparator circuit
(Q,, Q
5 and Q
6 in particular). Thus, the node 12 remains in a stable condition at essentially V
SS (the substrate of all transistors is connected to V
SS as is ordinarily true in P-MOS integrated circuits). Accordingly, the voltage on
the node 12 maintains the IGFET Q
1 in its "off" state, thereby maintaining the LED 10 in its "off" state also. Meanwhile,
since the node 11 is essentially at potential at V
GG due to the path through R and the LED to the source V
GG, the transistor Q6 is in its "on" state; so that the node 13 is essentially at potential
V
GG (except for a threshold of Q
6 which, with the backgate bias effect, is about -5 or -6 volts). This is true even
though Q
3 is also "on" because of the high B
6 of Q
6 as compared with the low B
3 of Q
3. On the other hand, since node 13 is at essentially V
GG while the node 12 is at V
SS, Q
4 is "on"; but this "on" condition of Q
4 combined with the "on" conditions of Q
5 and Q
6 is not sufficient to pull the node 12 away from V
SS, since Q
2 has the highest transconductance B of all. Thus, the node 12 remains stably at V
SS, thereby keeping Q
1 in its "off" state and hence the LED stably remains in its "off" state also.
[0010] When the input signal applied by the source 20 to the gate of Q
2 is then switched to a value sufficient to turn Q
2 "off", the potential of the node 12 tends toward V
GG but without reaching it because the driver Q
1 turns "on" before this node 12 reaches ground. As soon as the driver Q
1 turns "on", however, the LED turns "on" also and the node 11, between Q
1 and R, goes from the potential V
GG toward the potential V
SS, since the "on" resistance of the driver is advantageously made sufficiently small
compared with R, typically about R/2. As the node 11 goes toward V
SS, the transistor Q
6 allows the node 13 to go toward V
SS by virtue of the "on" state of Q
3. But when this node 13 reaches ground plus the threshold of Q
4, then Q
4 turns "on", in the opposite direction with node 13 as its source and node 12 as its
drain, thereby preventing the node 12 from going any further toward V
GG. In this way, the node 12 is kept at a potential suitable for maintaining the driver
Q
1 and the LED in their "on" states. In effect, the transistor arrangement of Q,, Q
4, Q
5 and Q
6 acts as a feedback comparator for stabilizing, against fluctuations of either polarity,
the voltage at node 11 essentially at the voltage applied to the gate of Q
4, whenever the signal input turns Q2 "off". Thus, the LED remains "on" until the input
signal is thereafter switched to a value sufficient to turn the transistor Q
2 back to its "on" state.
[0011] Although the invention has been described in detail in terms of a specific embodiment,
various modifications can be made without departing from the scope thereof. For example,
N-MOS technology can be used instead of P-MOS; that is, all the transistors Q
1-Q
6 can be integrated in a P-type semiconductor chip with N+ type source and drain regions,
with suitable modifications in V
SS and VGG. Moreover, other types of transistors than IGFETs can be used, such as J-FETs
or bipolar transistors. Also, a unidirectional current inhibiting diode element of
conductance B
5 in the forward direction can be used instead of the transistor Q
5. Moreover, the voltages applied to gate electrode of Q
4 and of Q
3 can both be other than ground, in order to stabilize the voltage at node 11 during
operation at a corresponding voltage other than essentially ground potential. In any
event, however, it is preferred that the voltage difference (V
SS - V
GG) be at least three or more times the voltage drop across the LED in its "on" state,
and that the voltage at node 11 be stabilized to a value that is sufficiently different
from V
SS to enable the use of a relatively small sized driver Q
1 of relatively high resistance, thereby to conserve semiconductor chip area.
1. Semiconductor circuit arrangement comprising transistor switch means for controlling
a controlled device when connected in series therewith, in response to an input signal
applied to a control input of said switch means, characterised by feedback means (Q;, Q4, Q5, Q6,) operable on the control input of the transistor switch means (Q1) for controlling the current flowing through the transistor switch means.
2. Circuit arrangement as claimed in claim 1, in which the feedback means is of comparator
form and is operable on the control input of the transistor means in dependence upon
a comparison of a voltage afforded by said transistor means (at node 11) and a reference
voltage (ground).
3. Circuit arrangement as claimed in claim 1 or claim 2, including a controlled device
(10) in series with a ballast resistor (R) and a first transistor driver switch (Qq),
the driver switch controlling the controlled device in response to an input signal
such that both the driver switch and the controlled device turn "off" in response
to one input signal and turn "on" in response to another input signal and a comparator
feedback control network including first (12) and second (11) feedback terminals,
the first feedback terminal (12) connected to a low current carrying control input
terminal of the first transistor driver switch (Q1) and the second feedback terminal (11) connected to a high current carrying terminal
of the first transistor driver switch.
4. Circuit arrangement as claimed in claim 3, comprising a second transistor (Q2) having a low current carrying terminal for connection thereto of the input signal
and having a pair of high current carrying terminals, one of the said high current
carrying terminals of the second transistor being connected to the said low current
carrying terminal of the first transistor (Q1), third (Q3), fourth (Q4), and sixth (Q6) transistors each having a low current carrying terminal and a pair of high current
carrying terminals, means for connecting mutually together one of the high current
carrying terminals of each of the third, fourth, and sixth transistors, a fifth (Q5) unidirectional current inhibiting device connected between the other high current
carrying terminals of the fourth and sixth transistors, and means for connecting the
said other high current carrying terminal of the fourth transistor to said one of
the high current carrying terminals of the second transistor.
5. Circuit arrangement as claimed in claim 4, in which the low current carrying terminals
of the third and fourth transistors are connected to terminals for the application
thereto of reference potentials, and in which the other high current carrying terminals
of the second and third transistors are connected to terminals for connection thereto
of a first voltage source, and the other high current carrying terminal of the sixth
transistor is connected to a terminal for connection thereto of a second, different
voltage source.
6. Circuit arrangement as claimed in claim 5, in which the first, second, third, fourth
and sixth transistors are insulated gate field effect transistors and in which the
fifth current inhibiting device is a field effect transistor whose gate terminal is
shorted to its drain terminal.
7. Circuit arrangement as claimed in claim 6, in which the controlled device is a
light emitting diode.
8. Circuit arrangement as claimed in any of claims 4 to 7, in which the first, second,
third, fourth, fifth and sixth transistors are formed on a semiconductive silicon
chip.
9. Circuit arrangement as claimed in any of claims 4 to 8, in which the second, third,
fourth, fifth and sixth transistors respectively have transconductances B2, B3, B4, B5, and B6, respectively which satisfy the following conditions: B5 is less than B3; B3 is less than either B4 or B6; B4 and B6 are each less than B2.
10. Circuit arrangement as claimed in claim 9, in which B5 is less than B3 by a factor of at least 5; B4 and B6 are each less than B2 by a factor of at least 2.