Ink drop compensation in ink jet printers

Abstract

 The flight path of drops from an ink jet printer nozzle are corrected to reduce print position error on the print media. Compensation values are stored and retrieved for use by the printer to correct the flight of a drop to the print media. The compensation values are based on the pattern of print data representing the drops in the ink stream with the drop being compensated. To reduce the number of variables that must be dealt with, one or more portions of the print data can be grouped into one or more blocks and each block treated as having a single effect on the drop being compensated. However, basing the compensation value on one predetermined treatment of print drops as having individual effects or as having individual effects in combination with one or more group effects on the drop being compensated does not produce the optimum print appearance for all combinations of print data. Accordingly, one of a plurality of modes (Mode 1, Mode 2, Mode 3) of treating the data in the print data register 70 is selected based upon the pattern of print data representing drops in the ink stream. Depending on the number of drops in the flight path with the drop being compensated, the drops may be treated as each having an individual effect, an individual effect by some drops and a single group effect by the remaining drops or an individual effect by some drops and group effects by multiple groups of the remaining drops. The compensation values are stored in store 75 and more storage space is allotted for compensation values based on the combinations treated as multiple groups because these combinations produce the most visible print error.

Description

[0001] This invention relates to correcting the flight paths of ink drops in an ink jet printer to compensate for the effects of charge repulsion between ink drops, induced charges on the ink drops and aerodynamic drag on the ink drops.

[0002] The three effects that can change the flight path of an ink drop in an ink jet printer are charge repulsion between drops, charge induction between drops and aerodynamic drag. The ink drop is charged as it breaks off from the ink stream. This is typically accomplished by grounding the ink, which is conductive, and surrounding the ink stream at the drop breakoff point with a charge ring connected to some predetermined voltage. The voltage between the ink stream and the charge ring creates electrical charges in the ink stream which are trapped in the drop as the drop breaks off from the stream. The magnitude of this charge trapped on the drop is used to control the flight path of the drop by placing an electric field in the flight path to deflect the charged drop. Thus, a change in the voltage potential applied to the charge ring can change the charge in the drop and the flight path of the drop.

[0003] Charge induction errors in the flight path are caused by previously charged drops in the vicinity of the drop breakoff point inducing a charge on the drop currently breaking off. The charge placed on a drop is predominantly controlled by the charge ring but an error charge can be placed on the drop due to a previously charged drop near the drop breakoff point. The error in charging the drop then causes an error in the flight path of the drop to the print media.

[0004] The charge repulsion error effect is created by drops of the same charge repelling each other as they fly towards the print media. The repelling forces between the drops change their flight paths and thus change the point at which the drops strike the media creating an error in printing.

[0005] The aerodynamic drag on a drop can change the flight time of a drop to the print media. The faster the print media is moving relative to the drop stream, then the greater will be the errors in print position due to changes in flight time of a given drop. The amount of drag experienced by a drop depends upon the pattern of drops flying in front of the print drop or reference drop.

[0006] Each of the above three effects can create errors in precision ink jet printing. Which effect is dominant largely depends on the distance from the drop breakoff point to the print media and the relative velocity between the ink drops and the print media. If the velocity of the print media is slow relative to the ink drop velocity the predominant errors in printing are due to charge induction and charge repulsion. As the flight time of ink droplets increase and as the velocity of the print media relative to the droplets increase, aerodynamic drag becomes the more predominant source of error in printing. This is especially true in a binary ink jet system using uncharged drops as the print drops and charged drops as the gutter drops. Since the uncharged drops are the print drops the error effects due to induced charges and charge repulsion are small compared to the errors due to the aerodynamic drag on the drops.

[0007] In addition, the error effect of induced charges or charge repulsion is limited to substantially the three or four drops immediately in the vicinity of the reference drop. It is known for example that the charge induction effect falls off nonlinearly with distance from the reference drop (drop breaking off). The fourth drop away from the reference drop is the last drop that usually needs to be considered (for example, see U.S. Patent Specification No. 4,032,924). Similarly, the charge repulsion effect between drops decreases as an inverse function of the squared distance between the drops. Thus, the charge repulsion effect on print error need be considered only for drops immediately in the vicinity of the reference drop.

[0008] On the other hand, the aerodynamic error effect, when it is predominant has been found to be a long term effect. In some situations drops in excess of 30 drop positions in front of the reference drop can have an effect on the aerodynamic drag on the reference drop.

[0009] One problem in trying to correct for relatively long term aerodynamic drag effects is the number of patterns to be corrected for. If drops as far as 30 drop positions away from the reference drop have an effect, then the number of possibilities requiring correction are 230. Clearly storing a charge compensation value for each and every possibility is not practical.

[0010] A basic solution to the above problem is to compensate the reference drop for each and every drop in the immediate proximity to the reference drop and to summarize the effect of groups of drops more remote from the reference drop. However, further improvement of print quality can be achieved with the same limited memory space if tradeoffs are made between print data patterns taking into account the print error distribution produced by the pattern combinations.

[0011] Accordingly, the invention provides an ink jet printer having a charge electrode and a deflection electrode to control the flight of each ink drop in accordance with print data for that drop, and flight compensation apparatus for modifying the potential applied to the deflection electrode to compensate the flight path of the ink drop to reduce print position error, the flight compensation apparatus comprising: print data buffering means for storing the print data pattern relating to an ink drop stream containing a reference drop R the flight of which is to be compensated; memory means for storing compensation values each of which can be addressed for application to the printer to modify the flight path of an ink drop; and the compensation apparatus being characterised by logic means responsive to the print data in the buffering means to form an address for the memory means; and mode selection means responsive to a predetermined portion of the print data in the buffering means to select one of a plurality of different modes of operation of the logic means.

[0012] The print data pattern is monitored and the one of a plurality of print data blocking or grouping techniques is dynamically selected to determine the compensation effect to be used to correct the flight path of the ink drop. In one mode, the correction is based only on individual drops in close proximity to the reference drop. This mode is used when a high percentage of the drops close to the reference drop will be flying in the same path as the reference drop to the print paper. In another selectable mode, the effect of drops in close proximity to the reference drop are individually corrected for and the more remote drops are corrected for as a single large block. In yet another selectable mode, the more remote drops instead of being corrected for as a large group are divided into sub-blocks and the effects of the drops in the sub-blocks are corrected for. Where the more remote drops are grouped as sub-blocks, the correction is based upon the pattern of print data that acts as a link or a bridge between the remote drops and the drops in close proximity to the reference drop.

[0013] The advantage in dynamically selecting print data blocks for correction effects is that storage space consumed to store correction values for patterns producing little or no error can now be reallocated to store correction values for patterns producing a large error. In other- words, in a situation where many of the drops in close proximity to the reference drop are flying in the same flight path they will tend to isolate the reference drop from the effects of more remote drops. Accordingly, there are fewer combinations of print patterns producing a sizable error that need to be taken into consideration and stored as correction values. The storage locations, which are saved, can be used to store compensation values for patterns where the more remote drops have a stronger effect on the flight path of the reference drop. As a result for the same stored quantity of correction values, a higher print quality appearance can be achieved by dynamically selecting the correction modes based on print data.

[0014] In the accompanying drawings, FIGURES 1 and 3 represent systems which do not employ dynamic selection of the grouping of print data. These two systems serve as background to assist in understanding the invention. In the drawings:-

FIGURE 1 is a diagram of a system in which the print data for the drops more remote from the reference print drop are grouped into three blocks of increasing size to reduce the number of print data patterns compensated for;

FIGURE 2 is a diagram of one example of logic that can be used to implement the block B logic in FIGURE 1;

FIGURE 3 is a diagram of a simpler system in which only one block of remote print data is combined to reduce the print data patterns used to retrieve the compensation signal to be applied to the charge electrode;

FIGURE 4 is a graph of print error distributions for different size data pattern samples;

FIGURE 5 is a diagram of a first embodiment of the present invention wherein the grouping of print data is dynamically changed depending upon the print data patterns;

FIGURE 6 is a more detailed diagram of the embodiment of FIGURE 5;

FIGURE 7 is a diagram of a second embodiment of the present invention, which uses a computer to implement the grouping or blocking of print data patterns for compensation effect;

FIGURE 8 is a timing diagram with examples of waveforms appearing in the embodiment of FIGURE 7; and

FIGURES 9 and 10 show program flow diagrams indicating program control for the computer in FIGURE 7 to implement the dynamic grouping or blocking of print data patterns of FIGURE 5.

[0015] In FIGURE 1, ink jet head 10 is printing on a media mounted on drum 12. As drum 12 rotates ink jet head 10 is indexed parallel to the axis of the drum so as to print the entire page mounted on the surface of the drum 12. Ink in the head 10 is under pressure and thus issues from the nozzle 14 as an ink stream. In addition, a transducer in the head 10 provides a vibration in the ink cavity inside head 10. This vibration or pressure variation in the ink causes the stream 16 to break-up into droplets.

[0016] The transducer in head 10 is driven by drop generator driver 17. The clock signal applied to driver 17 controls the frequency of the drops and the drop period--distance between drops. To synchronize the system, the clock signal is also applied to the shift register 30 and to the drum motor driver 19. Shift register 30 is shifted by the leading edge of the clock signal. The speed of drum 12 and motor 21 is held steady to the clock by feedback from tachometer 23 through phase locked loop circuit 25 to motor driver 19.

[0017] Charge ring 18 surrounds the ink stream 16 at the point where the ink stream breaks into droplets. Nozzle 14 and ink 16 are electrically conductive. With nozzle 14 grounded and a voltage on charge ring 18, electrical charges will be trapped on the ink droplet as it breaks off from stream 16.

[0018] As the droplets fly forward they pass through an electrical field provided by deflection electrodes 20. If the drops carry a charge they are deflected by the electrical field between electrodes 20. Highly charged drops are deflected into a gutter 22, while drops with little or no charge fly past the gutter to print a dot on the media carried by drum 12. Ink caught by gutter 22 may be recirculated to the ink system supplying ink to head 10.

[0019] In FIGURE 1 the print drops have no charge placed on them due to data. If there were no error effects, the print drops would be uncharged. However, because of the error effects, compensation charge is applied to the print drops. This compensation charge varies from print drop to print drop depending upon the correction required to obtain the proper flight path to the media on the drum 12.

[0020] The charge voltage applied to charge ring 18 is either a gutter (no-print) voltage or a compensation voltage. Switching circuit 24 receives the gutter print voltage from gutter voltage generator 26 and the compensation voltage from digital to analog converter 28. A zero bit in the reference drop R position of shift register 30 indicates the reference drop D R should be guttered. Accordingly, a binary zero from the reference drop stage of shift register 30, causes switch 24 to connect the gutter voltage generator 26 to the charge electrode amplifier 34. On the other hand, if the reference drop is to be printed, the R stage in shift register 30 will have a binary one stored therein. A binary one applied to switch 24 causes the switch to connect the compensation signal from the digital-to-analog converter 28 to the charge electrode amplifier 34.

[0021] Digital-to-analog converter 28 receives a digital compensation signal from the read only memory 32. The size of the digital word from memory 32 depends upon the capacity of the memory. Typically a 9 bit word representative of a compensation signal with 512 possible levels might be used.

[0022] The 9 bit word is converted into an analog signal by the converter 28 and applied to the switch 24. The signal from switch 24 is amplified by the charge electrode amplifier 34 and applied to the charge ring 18.

[0023] To generate the compensation signal, read only memory 32 contains 2¹¹ memory addresses with each address containing a compensation voltage for a particular print data pattern of drops. In the embodiment of FIGURE 1, one drop is monitored behind the reference drop and 30 drops are monitored in front of the reference drop. The shift register 30 thus has 32 stages to temporarily store the print data for the reference drop and the additional 31 drops being monitored. Drop D₀ is the trailing drop. Drops D to D₃₀ are the drops immediately preceding the reference drop D_R. Since FIGURE 1 is a schematic representation and not to scale, the distance shown from the reference drop D_R to the print drum 12 is not 30 drops. In actual operation the distance would be in excess of 30 drop periods (a drop period in distance equals the velocity of the drops multiplied by the period of the drop generation frequency).

[0024] Leading drops D₁ to D₇ and trailing drop D₀ are applied individually to the address register 33 for read only memory 32 at clock + At time. The time, clock + Δt, occurs a short time after the shift register 30 has shifted but before the reference drop DR breaks off during the clock cycle. Each of these drops is close enough to the reference drop D _R so that each variation in their print data pattern has a significant individual error effect on the flight time of the reference drop. The quantity of leading drops for which an individual correction is made is a design trade-off between the size of the memory 32 and the effect that the next most remote drop has on the reference drop.

[0025] One guideline that may be used to determine when to start grouping the leading drops is as follows. If the last drop which is individually corrected for has an error effect on the reference drop that requires a compensation signal of z volts, then the next n number of drops, which together are responsible for a correction of z volts can be grouped together into a single compensation bit decision. This is only one of many ways in which to select the grouping of drops for making a block compensation signal. Other alternatives will be discussed hereinafter.

[0026] In FIGURE 1, the remaining leading drops are grouped as follows. Block or group A includes leading drops D₁₆ through D₃₀. Block B includes drops D₁₁ through D₁₅. Block C includes drops D₈, D₉ and D₁₀. Each of these blocks is responsible for generating one bit of the address used by address register 33 in read only memory 32. In FIGURE 1 the criteria for designating a block as a one or zero address bit based on the print data in the block is indicated at the output of each block logic. For block C logic 36, if any of the drops D₈ to D₁₀ are a print drop then the Block C logic will have a one output. In other words, n is greater than 0 where n is the number of binary ones in block C. The block C logic 36 could simply be an OR circuit to generate an output binary one in the event any of the stages D₈, D₉, or D₁₀ of register 30 contains a binary one.

[0027] The block B logic 38 monitors stages D₁₁ through D₁₅ of shift register 30 for a total number of binary ones in excess of one. If two or more of the drops D₁₁ through D₁₅ are print drops, block B logic 38 will have a binary one output. Similarly, block A logic 40 monitors stages D₁₆ through D₃₀ of the shift register 30 for a total of binary one's greater than 4. Thus, if 5 or more of the drops D₁₆ through D₃₀ are print drops, block A logic 40 will have a binary one output.

[0028] An example of the logic to implement block B logic 38 is shown in FIGURE 2. AND gate 42 in combination with OR circuit 44 looks for a print condition for drop D₁₅ in combination with a print condition for any of the drops D₁₁ through D₁₄. AND gate 46 in combination with OR circuit 48 looks for a print condition for drop D₁₄ in combination with a print condition for any of the drops D₁₁ through D₁₃. Similarly, AND gate 50 in combination with OR circuit 52 looks for a print condition on drop D₁₃ in combination with a print condition on drop D₁₁ or D₁₂. Finally, AND gate 54 looks for the combination of drops D₁₁ and D₁₂ being printed. All of these possibilities are logically collected by OR circuit 56 to generate the n greater than 1 indication as the output from block B logic 38. Of course, any number of logic designs might be used to determine if 2 or more of the droplets D₁₁ through D₁₅ are print drops.

[0029] A variety of techniques may be used to determine the number of ones in a block or group which are necessary before assigning a single bit code to the output of a group. The criteria, n greater than 0 for block C, n greater than 1 for block B, and n greater than 4 for block A, were all determined empirically. The test procedure involved monitoring the compensation voltage necessary to bring a print drop to the correct position for particular patterns. The patterns chosen for each block were consecutive print drops from 0 up to the maximum size of the block with the consecutive drops being centred in the block. All drops, other than the reference drop, outside the block of drops being observed were gutter drops. A correction voltage for each pattern in each block was taken. The maximum and minimum correction voltages were averaged. Patterns requiring a correction voltage less than the average value were then designated as a one bit for the group. Patterns requiring a correction greater than the average value were then designated as a zero bit for the group. For example, in the Block A Logic if the number of drops was 4 or less, the correction voltage was greater than half of the average correction voltage for the block. If the number of drops was 5 or greater than the correction voltage was less than half of the average for the block.

[0030] The operation of the apparatus in FIGURE 3 is substantially the same as the operation in FIGURE 1. The print data for drops in the ink stream are buffered in shift register 60. Trailing drop DO and preceding drops D through D₁₀ are applied directly to the address register 62 of read only memory 64. Drops D₁₁ through D₁₇ are analyzed by logic 67. Logic 67 generates a binary one if three or more of the drops D₁₁ through D₁₇ are print drops, i.e., binary one stored in at least three of the shift register positions ^D₁₁ through ^D₁₇.

[0031] As in FIGURE 1, the shift register is shifted at the beginning of each drop clock cycle. Shortly thereafter (clock plus Δt) the values from the shift register 60 and the logic 67 output are loaded into the address register 62. Thus the address register 62 is loaded with a new pattern address prior to the breakoff time. The compensation value retrieved by the address in the address register is a 9-bit value which is passed to the digital-to-analog converter 66. The nine bits can then be converted by converter 66 to one of 512 analog values. These analog compensation values are amplified by the charge electrode amplifier and applied to the charge electrode (FIGURE 1). If the reference drop bit is a binary zero (a gutter drop), the gutter voltage is generated by converter 66. The binary zero from the reference drop bit signals converter 66 to generate its maximum output voltage irrespective of the value from ROM 64. The drop is charged with the maximum voltage and deflected to the gutter as shown in FIGURE 1. If the reference drop bit is a binary one (a print drop), converter 66 will generate the charge electrode voltage based on the compensation value received from memory 64.

[0032] An analysis of print error distribution, as a function of the total number, sample size N , of droplets preceding the reference drops that are individually monitored and as a function of print density, leads to the present invention which further improves the print quality. FIGURE 4 is a graph of print error values versus the number of print combinations producing the error value for various sample sizes N . Each curve or function represents a different N_T. As will be described hereinafter, this analysis shows that further improvement in print quality can be achieved by dynamically adjusting the blocking depending upon the pattern of print data for drops preceding the reference drop.

[0033] The curves in FIGURE 4 are representative and not precise. The N_T=11 curve indicates the distribution of the print error when 11 drops preceding the reference drop are individually monitored. The N -8 curve indicates the distribution of the print error when 8 drops preceding the reference drop are monitored. Generally, as fewer drops are monitored, the distribution curve becomes flatter and wider and the centre point or highest number of combinations is at a point further out on the print error axis in the graph.

[0034] From the standpoint of print quality, it is the right-hand portion of the distribution curves that represents the most objectionable errors on the printed page.

[0035] Print errors in the left-hand portion of the error distribution curve tend to not be visible to the eye while those in the right-hand portion stand out on the printed page. The curves show that if a very large memory were available so that more drops could be monitored individually, the print error distribution could be squeezed down to a spike and moved left on the graph to or near zero print error. Of course, such a system is not practical because of the large size memory required. Within the limitation of a 4K memory, only 12 drops can be monitored. As previously discussed, fewer drops immediately preceding the reference drop could be monitored individually and more remote drops monitored as groups.

[0036] In FIGURE 4, choosing to monitor 8 drops individually instead of 11 drops moves the print error distribution to the right. However, the print error distribution for NT=8 can be divided into regions based upon print density, the number of print drops in the eight bit sample. The cross-hatched region in the right-hand portion of the curve represents all combinations where the number of print drops is equal to or less than 3 (n<3) a low print density. The left-hand cross-hatched portion in NT 8 represents all print drop combinations where five or more of the eight drops are print drops (n>5) a high print density. The n>5 portion of the distribution confirms the expectation that if a large number of the drops adjacent the reference drop are print drops, they provide an aerodynamic shield for the reference drop as it travels to the print media. Conversely, if three or less of the drops out of the eight drops are print drops, there is much less shielding for the reference drop as it flies to the print media, and the print error increases.

[0037] If storage locations in memory for the patterns where n>5 could be borrowed and given to the patterns where n<3, it would be possible to lower the worst case print error. Stated another way, the drops more remote than 8 drops from the reference drop have a stronger effect when three or less of the drops in the eight drops preceding the reference drop are print drops. Therefore, for all cases where five or more of the drops in the first eight are print drops, only pattern changes in the eight drops will be monitored to address the read only memory for charge correction values. The memory saved by not using bits 9, 10 and 11 may then be used to store more correction values when three or fewer of the first eight drops are print drops.

[0038] Referring again to FIGURE 4, the dashed curve for N_T= 8(3:5) shows a print error distribution for the above memory exchange method. In effect, the NT=8 waveform is squeezed to form the N_T= 8(3:5) waveform. As a result, there is an improvement in worst case error as compared against NT 11 waveform, but there is also a degradation in the smaller print errors. Since the larger print errors are the most visible to the eye, this is an attractive tradeoff for improving overall print quality.

[0039] In effect, the memory space exchanging divides the N_T =8 waveform into three portions requiring different optimum print error pattern monitoring for optimum use of the memory for storing compensation values. A first mode for addressing the memory would be where five or more of the drops in the first eight drops preceding the reference drop are print drops. A second mode would be where four of the drops of the first eight preceding the reference drop are print drops. Finally, the third mode would be where three or less of the drops of the first eight drops are print drops. In other words, depending upon the number of print drops in the first eight drops, the pattern monitored in the print data and the blocking or grouping of print data to address the memory may be dynamically changed.

[0040] Apparatus embodying the present invention, using dynamic grouping of the print data, is shown in FIGURE 5. This apparatus divides the N _T =8 curve into the three portions shown in FIGURE 4. To do this the eight drops immediately preceding the reference drop have their print data monitored by a mode selection logic 72. Print data register 70 contains the print data for the reference drop R, one trailing drop D and 17 drops D1-D17 preceding the reference drop.

[0041] Mode controlled gating 73 responds to the mode signals from logic 72 to form the addresses used by the compensation storage device 75. In the embodiment of my invention in FIGURE 5, storage device 75 is addressed by 12 bits. The 12 bits are formed by the mode control gating 73 from the print data bits in the print data register 70.

[0042] The mode control gating circuits receive data bits D₀ and D₁ through D₁₇ from the print data register. In mode 1, where the number of binary one's in D₁ through D₈ is equal to or greater than five as signalled by the mode selection logic 72, the gating circuits use D₀ and D₁ through D₈ as the address for the storage device 75. The last three bits in the address are set to zero. Setting these three bits to zero saves memory space which can be subsequently used during mode 3.

[0043] In mode 2, where the number of binary one's in D₁ through D₈ is equal to 4, the mode controlled gating circuits group the print data bits from _D11 through D₁₇. These data bits are formed into a single data bit B for the entire group or block. Accordingly, in mode 2 the gating circuit 73 form the address for storage 75 as D₀, D₁ through D₁₀ and bit B.

[0044] In mode 3, where the number of binary one's in D₁ through D₈ is less than or equal to three, the gating circuits 73 make use of the memory locations saved during mode 1. Further, mode 3 operates in two phases or two levels of addressing of the storage device 75. In the first phase of addressing, the gating circuit 73 simply uses data bits D₀ and D₁ through D₁₁ to address the storage device 75. The compensation value addressed is loaded into V_CE storage device 77. The gating circuits then proceed to the second phase of addressing if two conditions exist in the print data--D₉, D₁₀, and D₁₁ are not all binary one's and D₁₂ through D₁₇ are not all binary zeros. If either D₉, D₁₀ and D₁₁ are all binary ones or D₁₂ through D₁₇ are all binary zeros, then mode 3 addressing stops at phase 1. Under these conditions looking for fluctuations in data patterns at more remote drop positions is not necessary.

[0045] Phase 2 or second level addressing during mode 3 proceeds if D₉ ,D₁₀ and D₁₁ are not all binary one's and if there are any binary one's in D₁₂ through D₁₇. The address in phase 2 is generated by inverting data bits D₁ through D₈ and pairing data bits D₁₂ through D₁₇ into three block bits; B₁, B₂ and B₃. The trailing bit data bit D₀ is also used at the first bit position in the address. The fact that B₁, B and B bits will have one or more binary ones and the fact that D₁ through D₈ data bits have been inverted means the second level or second phase address will be identical to the addresses saved during mode 1 on a one-to-one basis.

[0046] To use the compensation values accessed by the addresses generated by gating circuits 73, storage devices 77 and 79, bridging logic 81 and adder 83 are used. In all situations except mode 3, phase 2, the final compensation value is stored in the V_CE storage device 77. From there V _CE is passed through adder 83 to be applied eventually to the charge electrode. In mode 3, phase 2, adder 83 adds a Δ V_CE increment to the V_CE voltage. This is accomplished by loading compensation values from storage device 75 into the Δ V _CE storage device 79 during phase 2 of mode 3.

[0047] Each mode-3 phase-2 address accesses in storage device 75 three incremental compensation values A V_CE one of which may be added to the compensation value in storage device 77. Which one of the three A V_CE voltages is to be added to the V _CE voltage is controlled by bridging logic 81. Bridge logic 81 is so named to reflect the fact that the binary pattern in data bits D₉, D₁₀ , and D₁₁ has a bridging effect between the data bits D₁ through D₈ and data bits D₁₂ through D₁₇. In other words, the strength of the effect of the pattern of drops D₁₂ through D₁₇ on the reference drop will depend upon the bridging effect of drops D , D₁₀, and D₁₁. Logic 81 selects one of the Δ V_CE increments from storage device 79 to be added to the charge electrode voltage V_CE based upon whether the number of binary one's in D₉, D₁₀, and D₁₁ is zero, one or two.

[0048] Thus, the apparatus in FIGURE 5 has dynamically selected various print data bit groupings depending upon the print data pattern. Further, those print data combinations producing small errors have had their memory storage space reallocated to those print data patterns which contribute large errors. In this way, the exchange of storage space between mode 1 and mode 3 produces an overall reduction in the worst case print error.

[0049] In FIGURE 6, a more detailed drawing of the FIGURE 5 embodiment of the invention is shown. Shift register 70 and mode selection logic 72 in FIGURE 6 correspond to the print data register 70 and mode selection logic 72 in FIGURE 5.

[0050] The mode selection logic 72 monitors drops D ₁ through D₈ to detect the three conditions--n greater than or equal to 5, n equals 4 and n less than or equal to 3 where n is the number of binary one's in the print data for drops D₁ through D₈. Mode 1 where n>5 utilizes only the variations in print patterns in the first eight drops, D₁ through D₈, to change the address in the read only memory 74. Mode 2 where n=4, treats the trailing drop and the ten drops immediately preceding the reference drop individually and treats drops D₁₁ through D₁₇ as a group, i.e., mode 2 operates exactly as the apparatus shown in FIGURE 3. Mode 3 where n<3 makes use of the addresses saved during mode 1 and changes the data blocking or data grouping of drops D₉ through D₁₇ based upon the pattern of drops in D₉ through ^D₁₇.

[0051] In mode 1 and all other modes, the print data for the trailing drop D₀ is passed directly to the zero order position in address register 76. Also, the print data from drops D₁ through D₈ is passed to the address register 76 via the invert switch 78. The invert switch 78 is active to invert the print data for drops D₁ through D₈ only during mode 3 as will be discussed hereinafter. Normally the invert switch 78 passes the print data for drops D₁ through D directly from the shift register 70 to the address register 76.

[0052] In addition, in mode 1, the signal line representing the condition n>5 is used to enable gate 80. Gate 80 passes binary zeroes to OR circuits 82, 84 and 86 which in turn pass the binary zeros to the ninth, tenth and eleventh order positions of the address register 76. Thus, in mode 1, the three highest address register positions are forced to zero and this space saved during mode 1 will be subsequently used during mode 3 as hereinafter described.

[0053] In mode 2, the print data in the shift register 70 is monitored in the same manner as the print data was monitored in FIGURE 3. The mode 2 signal or n=4 condition signal is used to activate or enable gate 88. Gate 88 passes the print data bit from D₉ to OR circuit 82, from D₁₀ to OR circuit 84 and a bit generated by logic 90 to OR circuit 86. The last address bit is generated from the group analysis of data positions D₁₁ through D₁₇ by the n>3 logic 90.

[0054] The address positions for the ninth, tenth and eleventh order bits in the address register are then passed by OR's 82, 84 and 86 to the address register 76 of the read only memory 74. The first address position in the address register 76 is from the trailing drop position D₀ in the shift register 70. The next eight positions in the address register are from drop data positions D₁ through D₈ in shift register 70. In other words in mode 2, the trailing drop and the ten drops immediately preceding the reference drop are monitored individually while drops D₁₁ through D₁₇ are grouped into a single data bit for addressing the read only memory 74. This operation is identical to that previously described for FIGURE 3.

[0055] In mode 3, the read only memory 74 is addressed in two phases or two levels. The blocking or grouping of the data in this two- phase addressing for drops D₉ through D₁₇ depends upon the pattern of print data in D₉ through D₁₇. If D₉, D₁₀, and D₁₁ all contain binary one's, then only one phase of addressing is used during mode 3. Also if drops D₁₂ through D₁₇ are all binary zeros, only one phase of addressing is used in mode 3. If neither of these conditions are satisfied, then two phases of addressing are used during mode 3.

[0056] In phase 1 of mode 3, gate 92 is enabled to pass the print data from stages D₉ through D₁₁ to address register 76. Simultaneously binary bits for stages D₀ and D₁ through D₈ are also passed to the address register 76. Thus, the first phase or first level addressing of memory 74 uses the individual data bits for D₀ and D₁ through D11. At clock phase 1 time plus Δt. (Clk _Ph 1 + Δt₁) AND gate 94 is enabled and provides a set signal for register 96. Register 96 then stores the binary bits for _D9, D₁₀ and D11 passed by gate 92. The Clk Ph 1 + Δt₁ signal is used so that transients in the logic die out before setting register 96 with the contents of D₉, D₁₀ and D₁₁ from shift register 70. Shift register 70 is shifted by the leading edge of the clock phase 1 (Clk Ph 1) signal. The Δt₁ interval occurs early during the duration of the clock phase 1 signal.

[0057] At clock phase 1 plus Δt₂ (Clk Ph 1 + Δt₂), the compensation value addressed in memory 74 during phase 1 is loaded into a register 98. The Δt₂ interval occurs during clock phase 1 duration shortly after the Δt₁ interval pulse occurs during clock phase 1.

[0058] Note that address register 76 is set by Clk Ph 1 + Δt₁ via OR ₁₀0. As a result, the address register is set at Δt₁ during phase 1 and the compensation value read out from memory 74 is loaded into register 98 at Δt₂ during phase 1.

[0059] In summary, in phase 1 mode 3, at time Δt₁ print data for D₀ through D₁₁ are loaded into the address register 76. At phase 1 Δt₂ time, the compensation value for this first level addressing of memory 74 is stored in register 98. Also register 96 is set at Δt₂ time to store the contents of _D9, _D10 and D₁₁. These binary values will be used as described hereinafter during phase 2 of mode 3.

[0060] A mode 3 phase 2 condition is signalled by AND gate 102. The inputs to AND gate 102 are the mode 3 signal from logic 72, the clock phase 2 (Clk Ph 2) signal and the output of NOR 104. NOR 104 has an output only if D₉, D₁₀, D₁₁ are not all binary one's and only if D₁₂ through D₁₇ are not all binary zeros.

[0061] D₁₂ through D₁₇ are paired to form three blocks or groupings of two by OR circuits 110, 112 and 114. OR 110 will have an output if either D₁₂ or D₁₃ contains a binary one. OR circuit 112 will have an output if either D₁₄ or D₁₅ contain a binary one. OR circuit 114 will have an output if either D₁₆ or D₁₇ contains a binary one.

[0062] NOR 108 monitors the output of the paired blocks and has an output itself if OR circuits 110, 112 and 114 all have zero outputs. AND gate 106 monitors D₉, D₁₀ and D₁₁ and has an output only if D₉ through D₁₁ are all binary one's. NOR 104 then collects the output from AND 106 and NOR 108 and has an output only if there is zero output from both AND 106 and NOR 108. Thus a one output from NOR 104 means that D₉ through D₁₁ are not all l's and D₁₂ through _D17 are not all 0's. This is the phase 2 mode 3 condition which has an output at Clk Ph 2 time AND 102. This mode 3 phase 2 signal is used to enable gate 116, to switch invert switch 78 and to enable AND gates 118 and 120.

[0063] Enabling invert switch 78 means that the inverted data bit pattern from D₁ through D₈ in shift register 70 is applied to bit positions 1 through 8 in the address register 76. Enabling AND gate ₁18 means that at Clk Ph 2 time plus Δt₁ (Clk Ph 2 + Δt₁) address register 76 will be set to the value on the input lines to the address register. Δt₁ is a timing pulse occurring some time during the duration of Clk Ph 2. Enabling AND gate 120 means that at Clk Ph 2 + At₂ time (shortly after Clk Ph 2 + Δt₁) ΔV_CE register 122 will be loaded with the compensation value addressed at Clk Ph 2 + Δt₁ time. Enabling gate 116 means that the paired grouping output from D₁₂ through D₁₇ is passed by gate 116 through OR's 82, ₈₄ and 86 to the address register 76. These bits are the address inputs for bits 9, 10 and 11 in the address register 76 during the phase 2 or second level addressing.

[0064] In summary, the second level address for the read only memory 74 is the trailing bit D₀, the inverted data pattern for D₁ through _D8 and the paired groupings from D₁₂ through D₁₇. At Clk _Ph 2 + Δt₂ time, AND gate 120 will have an output since it has been enabled by AND gate 102. This output from AND gate 120 sets ΔV_CE register to load the nine bits of compensation stored at the address accessed during the second level addressing. Thus, in mode 3 at the end of clock phase 2, the V CE register 98 contains a compensation value and the ΔV_CE register 122 also contains values for compensating the charged drop.

[0065] The values in the ΔV_CE register are divided into three portions. Memory 74 has a nine-bit output so these nine bits may be divided into three groups of three bits and stored in ΔV_CE register 122. One of the three bit values in register 122 will be added to the V_CE nine bit value in register 98 by the digital adder 124. Which one of the three bit values in register 122 is added depends upon the contents of register 96.

[0066] Register 96 is analyzed by the ΔV_CE logic 126. Depending upon whether the number of one's in print data bits D ₉ D₁₀ and D₁₁ is 0, 1 or 2, gate 128 will gate one of the three bit values in register 122 to the digital adder 124. The selected ΔV_CE compensation value is added to the V_CE compensation value and passed to the digital-to-analog converter 130. The output of the converter 130 goes to the switch 24 which performs the same function as described in FIGURE 1.

[0067] To summarize mode 3, if the number of binary one's in bits D₁ through D₈ is less than or equal to 3 and bits D₉, D₁₀ and D₁₁ are all one's or bits D₁₂ through D₁₇ are all zeros, the pattern is sufficiently isolated that the memory 74 is addressed by the trailing bit and bits D₁ through D₁₁. However, if the bits D₉ through D₁₁ are not all one's and the bits D₁₂ through D₁₇ are not all zeros, various patterns of compensation will occur. The strength of the bridging of compensation effects from D₁ - D₈ to D₁₂ - D₁₇ will depend upon the number of o^ne's in D₉, D₁₀, and D₁₁. Accordingly, a ΔV_CE compensation is added to a V_CE compensation by two-level addressing of memory ₇₄. The values for the V _CE in the first level depend upon the data pattern from D₁ through D₁₁ while the values in the second level for the ΔV_CE increments depend upon the data pattern in D₁₂ through D₁₇ grouped in pairs and the strength of the bridging as represented by the number of binary one's in D₉, D₁₀ and D₁₁.

[0068] In the first level of addressing, a 9-bit word read from the memory ₇₄ defines the value for V_CE. In the second level of addressing, the 9-bit word read from memory is partitioned into three ₃-bit words--one three bit word for each ΔV_CE increment. Thus, the second level 9-bit word is partitioned so that there is a three-bit incremental compensation word for each of the three possible bridging effects (^D₉, ^D₁₀ and D₁₁ contain 0, 1 or 2 binary ones).

[0069] Note that the ΔV_CE register 122 is reset at Clk Ph 1 + At₂ time. Accordingly, register 122 is reset to zeros near the end of each _Clk Ph 1 time. Therefore, register 122 will have values in it only if there is a mode 3 phase 2 condition as indicated by AND ₁₀₂. Under all other conditions the compensation value applied to the converter 130 is represented only by the digital value in· V_CE register 98.

[0070] In the above described manner, FIGURE 6 implements the waveform N_{T 8}(_3:5) shown in FIGURE 4. As described earlier, this print error distribution produces an improvement in the worst case condition and, thus, an improvement to the eye of an observer of the printed document.

[0071] The embodiment of FIGURES 5 and 6 may be implemented by use of a computer. A computer controlled system to retrieve the compensation values to be applied to the charged electrode amplifier is shown in FIGURE 7. Waveforms occurring in FIGURE 7 and illustrative of the timing of the system are shown in FIGURE 8.

[0072] In FIGURE 7, timing for the system is provided by the timing oscillator 132. Oscillator 132 generates a cycle clock signal (waveform A of FIGURE 8) which is used to control the cycles of the computer 134. The cycle clock signal is divided by a frequency divider 136 to generate a drop clock signal (waveform _B FIGURE ₈). The division factor M for the frequency divider circuit 1₃₆ is selected to provide the desired drop frequency and also to allow the computer sufficient time during a drop cycle to find the compensation value to be used during the next drop cycle.

[0073] Sync logic 138 is controlled by computer 134 to generate a sync pulse (waveform C of FIGURE 8) to synchronize the system with the time of occurrence of drop breakoff of the ink drop from the ink stream. Waveform D in FIGURE 8 is an example of the charge electrode voltage building up during each cycle between sync pulses. Sync logic 138 under control of computer 134 generates the sync pulse at a time sufficiently ahead of the drop breakoff time to allow the charge electrode voltage to build to a stable level. Typically, the sync pulse will be generated such that it occurs during the first one-fourth of the drop cycle while the drop breakoff point occurs approximately three-fourths of the period through the drop cycle.

[0074] The sync pulse is used as a clocking pulse for the data source 140 and shift register 142. Serial data from the data source is shifted into the shift register 142 by the leading edge (LE) of the sync pulse. The trailing edge (TE) of the sync pulse enables gate ¹⁴⁴ to pass print data bits DO and D₁ through ^D₁₇ to computer 134 for analysis. Thus, the leading edge of the sync pulse is used to shift data into the shift register 142 and the trailing edge is used to gate that data in parallel to the computer.

[0075] The computer 134 analyzes the print data pattern to retrieve the compensation value from the read only memory 146 before the leading edge of the next sync pulse transfers the compensation value into the V CE register 148.

[0076] Computer 134 contains a processor and a memory. The computer is program controlled to implement the group blocking of the print data into a pattern which can be used to address the read only memory 146. Gating logic 150 is controlled by the computer to pass the addresses generated by the computer to address the read only memory. Gating logic 150 is also controlled by the computer to access the compensation value stored in the read only memory as addressed and to operate on that compensation value as dictated by the program. The final compensation value is then gated under computer control to the register 148.

[0077] The register 148 is set to the digital value for the charge electrode voltage by the leading edge of the sync pulse. Since computation time is predetermined to be less than the time between sync pulses, the charge electrode voltage is computed during one cycle between sync pulses and used during the next cycle between the sync pulses.

[0078] The computer 134 can also be used to store a digital value for the gutter voltage. Thus, in the event that the reference bit R is a no print or zero bit, the computer 134 gates the digital value of the gutter voltage through the gating logic 150 to the register 148. At the leading edge of the next sync pulse, the gutter voltage value is loaded into register 148. The digital-to-analog converter 151 then applies the gutter voltage value to the charge electrode amplifier. If the reference drop R is a print drop, the compensation value will be loaded into register 148, converted by converter 151 to an analog signal and applied to the charge electrode amplifier.

[0079] The advantage of the apparatus in FIGURE 7 is that computer 134 can be programmed to implement a number of print data grouping or print data blocking techniques to address the memory 146 for compensation values. One example of program control of the computer 134 to implement the embodiment previously described with reference to FIGURES 5 and 6 is illustrated by the program flowcharts in FIGURES 9 and 10. When programmed in accordance with these flowcharts, the computer 134 will dynamically change the group blocking of the print data in accordance with the three modes previously discussed with reference to FIGURES 4 and 5. Various computing systems could be used so long as they are fast enough to complete the addressing within the period of one drop cycle (about 10 usec.).

[0080] Referring now to FIGURE 9, the program starts by checking the reference drop R to determine whether it is a print drop or a gutter drop. If the reference drop is a binary zero, decision block 152 passes control to block 154. Operation block 154 controls the computer to provide a digital value V CE equal to the count 511. The count 511 corresponds to the nine bit digital value of the gutter voltage. Accordingly, when the V_CE register 148 (FIGURE 7) is next loaded by the sync pulse, the 511 count would be passed into the register.

[0081] If the reference drop is a binary one, program control passes to decision block 156. Decision block 156 is the mode 1 decision block. If the number of binary one's for print data bits D through D₈ is greater than or equal to 5, program control branches to mode 1 implemented by operation block 158. If the number of binary one's in D₁ through D₈ is less than 5, program control passes to decision block 160 to make the decision between mode 2 and mode 3.

[0082] In mode 1, operation block 158 sets the 4K address for the read only memory to the binary values for DO through D ₈ and forces the three highest address bit positions to zero. Program control passes then to operation block 162 where the mode 1 address is used to access the charge electrode voltage from the read only memory. At the next sync pulse this charge electrode value would be loaded into register 148 in FIGURE 7.

[0083] Mode 2 operation occurs if the decision block 160 indicates the number of binary one's in D1 through D₈ is equal to 4. The program control then passes to decision block 164. Decision block ₁₆₄ represents the group analysis of print data bits D₁₁ through D₁₇. If the number of binary one's in D₁₁ through D₁₇ is equal to or greater than 3, the program passes to operation block 166. If the number of one's in D₁₁ through D₁₇ is less than 3, the program passes to operation block 168. In operation 166, the address bits are set to the values for data bits D₀ through D₁₀, and the elev- _ent_h bit position is set to binary 1 representing data bits D₁₁ through _D17 as a group. Operation 168 sets the address to the data bits for D₀ through D₁₀ and the eleventh bit is set to a binary 0 representing the group of data bits D₁₁ through D₁₇. The mode 2 address from either block 166 or 168 is used by operation block 162 to access the read only memory to obtain the charge electrode voltage. This mode 2 charge electrode voltage is then loaded into the register 148 (FIGURE 7) during the next sync pulse.

[0084] Mode 3 operation is indicated by a negative decision by decision block 160 in FIGURE 9. If the decision blocks 156 and ₁₆₀ both produce negative results, then the number of binary one's in D₁ through D₈ must be less than or equal to 3 which is the mode 3 condition. The mode 3 operation 170 in FIGURE 9 is diagrammed in detail in FIGURE 10.

[0085] In FIGURE 10, the mode 3 operation starts by blocking or grouping the data bits pairs D₁₂ with D_13' ^D₁₄ with D15, and ^D₁₆ with D₁₇. If ^D₁₂ or D₁₃ or both contain a binary one, then decision block 170 sets a block bit B₁ to 1. If both D₁₂ and D₁₃ contain binary zeros, then decision block 170 sets the block bit B₁ to zero. Decision blocks 172 and 174 perform the same function for data bits _D14 with D₁₅ and D₁₆ with D₁₇, respectively. Block bit B₂ is set to one if D₁₄ or D₁₅ contains a binary one; otherwise, block B₂ equals zero. Similarly, block bit B is set to one if D₁₆ or D₁₇ contain a binary one; otherwise, block bit B is set to zero.

[0086] Next program flow moves to decision block 176 to determine if the number of binary one's in B₁ through B₃ is equal to zero. If it is, program flow branches to operation block 178. If it is not, program flow branches to decision block 180 to determine if the number of binary one's in data bits D₉ through D₁₁ is equal to 3. If it is, the program flow branches to operation block 178. If it is not, program flow branches to mode 3 double phase.

[0087] In mode 3 single phase, operation block 178 sets the address bits to the data bit pattern for data bits D₀ through D₁₁. Computer 134 then controls the gating logic via operation block 182. Operation block 182 causes the computer to address the read only memory with the address bits set by operation 178. The charge electrode voltage obtained from the read only memory is then gated to the register 148 during the next sync pulse.

[0088] In mode 3 double phase, program flow branches from decision block 180 to operation block 184..In the first phase of the double phase operation, block 184 sets the address bits to the value of the data bits D₀ through D₁₁. This address is then used by operation 186 to access the read only memory and get charge electrode voltage V¹_CE for phase 1.

[0089] Program control passes on to operation block 188 to commence the second phase of the double-phase operation. In operation block ₁₈₈, the computer inverts the data bits for D ₁ through D₈ and proceeds to operation block 190. In operation block 190, the computer sets the address bits to the bit D₀, the inverted data bits for D through D₈, and the block bits B₁, B₂ and B₃ for positions 9, 10 and 11 of the address. This second phase address is then used during operation 192 to access the read only memory.

[0090] In operation 192, the 9 bits of compensation value read from the read only memory are partitioned into three sections, Δ₁, Δ₂ and Δ₃, of three bits each. Each of these three-bit values may then be added to the V¹_CE charge electrode voltage determined during phase 1. The addition operation depends upon the number of binary one's in the data bit positions D , D₁₀ and D₁₁. The program control flows from operation block 190 to decision block 194.

[0091] If the number of binary one's in D₉, D₁₀ and D₁₁ is equal to zero, then decision block 194 branches the program to operation block 196. Operation 196 adds Δ₁ to the charge electrode voltage V¹_CE determined during the first phase. If the number of binary one's in D₉ through D₁₁ is not equal to 0, program control branches to decision block 198 to determine whether the number of binary one's is equal to 1 or greater than 1. If the number of binary one's in D₉ through D₁₁ is equal to 1, then the charge electrode voltage is formed by operation block 200. Computer 134 in operation block 200 adds the first phase charge electrode voltage V¹_CE to Δ₂ to obtain the final charge electrode voltage V¹_CE. If the CE number of binary one's in D₉, D₁₀ and D₁₁ is not equal to zero and not equal to one, the program will branch to operation block 202. In operation block 202, the computer 134 adds the first phase charge electrode voltage V¹_CE to Δ3 to form the final charge electrode voltage V_CE. As discussed earlier, these A charge electrode increments are different due to the different bridging effect, caused by the number of binary one's in positions D₉, D₁₀ and D₁₁, on the block pairs represented by binary bits B , B₂ and B₃. Once the final charge electrode voltage is determined in the double-phase operation by one of the operation blocks 196, 200 or 202, that charge electrode voltage is loaded into the register 148 (FIGURE 7) during the next sync pulse.

[0092] By changing the size of the shift register and the read only memory and be changing the group data bit analysis performed by the programmed computer, any number of blocking or grouping patterns might be used to address the read only memory.

[0093] Further, more or less than three modes of selection to different dynamic blocking or grouping routines could be used. For example, if the data bit pattern being monitored to make the mode selection contained an odd number of data bits, the invention might be implemented by using two modes rather than three modes. In other words, if the first seven data bits preceding the referenced drop were being monitored to make the mode selection, the memory exchange could be made based on a greater-than-or-equal-to four and a less-than-or-equal-to three mode selection. There would be no middle condition between the exchange and, thus, there would only be two modes selected.

[0094] Furthermore, if more data bits were being monitored, the computer might be programmed to dynamically group more data bits as a function of the bridging effect of the data bit pattern in one group on the data pattern in the next group.

Claims

1. An ink jet printer having a charge electrode and a deflection electrode to control the flight of each ink drop in accordance with print data for that drop, and flight compensation apparatus for modifying the potential applied to the deflection electrode to compensate the flight path of the ink drop to reduce print position error, the flight compensation apparatus comprising: print data buffering means for storing the print data pattern relating to an ink drop stream containing a reference drop R the flight of which is to be compensated; memory means for storing compensation values each of which can be addressed for application to the printer to modify the flight path of an ink drop; and the compensation apparatus being characterised by logic means 73 responsive to the print data in the buffering means to form an address for the memory means 75; and mode selection means 72 responsive to a predetermined portion of the print data in the buffering means 70 to select one of a plurality of different modes of operation of the logic means.

2. An ink jet printer as claimed in claim 1, in which the mode selection means is operable to select a mode of operation of the logic means in dependence upon the number of drops in the ink stream which are in close proximity to the reference drop and which will remain in the flight path to the print media.

3. An ink jet printer as claimed in claim 2, in which the mode selection means comprises: first means for monitoring print data for the drops in close proximity to and immediately preceding the reference drop and generating a first mode signal when the print data indicates more than half of the close-in drops will fly to the print media; second means for monitoring print data for the drops in close proximity to and immediately preceding the reference drop and generating a second mode signal when the print data indicates approximately half of the close-in drops will fly to the print media; third means for monitoring print data for the drops in close proximity to and immediately preceding the reference drop and generating a third mode signal when the print data indicates less than half of the close-in drops will fly to the print media.

₄. An ink jet printer as claimed in claim 3, in which the logic means comprises: first gating means responsive to the first mode signal to gate only the portion of the print data pattern representing drops close to the reference drop as a portion of the address for the memory means and to save other available addresses by forcing the remaining portion of the address to a fixed value; second gating means responsive to the second mode signal to gate the portion of the print data pattern representing drops close to the reference drop as a portion of the address for the memory means and to gate a single grouped representation for the remote drops as the remaining portion of the address; and third gating means responsive to the third mode signal to generate a first address based only on data obtained directly from the print data buffering means and to generate a second address using addresses saved by said first gating means based in part on inverted print data from said buffering means and in part on multiple grouped representations for the remote drops.

5. An ink jet printer as claimed in claim 2, in which the mode selection means is operable when the ink drops in the ink stream remote from the reference drop have a negligible effect on the flight path of the reference drop to select a first mode of operation of the logic means in which it forms the address for the memory means merely by directly gating a first predetermined portion of the print data pattern.

6. An ink jet printer as claimed in claim 5, in which the mode selection means is operable when the ink drops in the ink stream remote from the reference drop have a significant effect on the flight path of the reference drop to select a mode of operation of the logic means in which it forms part of the address for the memory means by analysing a portion of the print data pattern representing remote drops and forms the remainder of the address by gating the remaining portion of the print data pattern.

7. An ink jet printer as claimed in claim 6, in which the mode selection means is operable when the ink drops in the ink stream remote from the reference drop have such an effect on the flight of the reference drop that they can be treated as a single group of drops to select a second mode of operation of the logic means in which it forms part of the address by analysing the print data pattern of that single group of drops and forms the remainder of the address by directly gating the remaining portion of the print data pattern.

8. An ink jet printer as claimed in claim 5, in which the mode selection means is operable when the ink drops in the ink stream remote from the reference drop have so significant effect on the flight of the reference drop that they cannot be treated as a single group of drops to select a third mode of operation of the logic means in which it forms part of the address for the memory means from individual address bits formed by analysing respective blocks of a plurality of blocks of the print data pattern and forms the remainder of the address by gating the remaining portion of the print data pattern.

9. An ink jet printer as claimed in claim 8, in which: the memory means has locations each containing a set of incremental compensation values stored at one address; the logic means is operable to provide a phase-one address based on the print data pattern so that the memory means retrieves a first compensation value; the logic means is operable to provide a phase-two address based on said individual address bits and on the remaining portion of the print data pattern so that said memory means retrieves a set of incremental compensation values; the logic means is operable to select one of the incremental compensation values depending upon the strength of the bridging effect between drops closest to the reference drop and drops most remote from the reference drop by drops intermediate these two groups of drops; and the compensation apparatus includes means for adding the selected incremental compensation value to said first compensation value and passing the summed value to control the potential applied to the deflection electrode of the printer.

Drawing