The invention relates to a digital multichannel speech synthesizer operating according to the linear-predictive-coding method, comprising:

• - a speech generator including a digital noise generator, an adjustable digital pitch generator, and a controllable change-over switch for selectively connecting one of said generators to an output;
• - an adjustable digital filter adapted to produce in combination with said speech generator digital speech signals for each of a number of speech signals;
• - means for adjusting said speech generator and for controlling said switch by control signals; and
• - means for generating interpolated parameters.

A multichannel synthesizer of the kind described above is known from Icassp 79, Proceedings Of An IEEE International Conference On Acoustics, Speech and Signal Processing (April 2-4, 1979, Washington), L. Nebbia et al.: "Eight-channel digital speech synthesizer based on LPC techniques, pages 884-886.

The prior art as disclosed in the article mentioned above describes multichannel synthesizers suitable for applications in which good quality audio responses over a number of time-division channels are required. Although with such prior art multichannel synthesizers a satisfactory performance is achievable, the transmission capacity of the multichannel transmission path between a sending side and a receiving side of a communication section is not exploited to its full extent, while the quality of the synthesized speech is invariable. More in particular this prior art has the deficiency that with decreased traffic load on said transmission path, the amount of idle transmission time, i.e. time segments during which useful information is not transferred, increases and consequently the transmission efficiency declines.

It is an object of the present invention to improve the overall performance of a multi- channel synthesizer of the aforementioned kind in that an improved transmission efficiency and an improved quality of synthesized speech are achievable. In other words it is an object of the present invention to effect an advantageous trade-off between quality and quantity, thereby more efficiently exploiting the transmission time available on the multichannel transmission path.

A digital multichannel speech synthesizer is according to the invention characterized in that said speech generator in combination with control means are adapted to selectively vary the number of bits involved in the computation of each parameter and/or the number of parameters effective for generating synthesized speech, in dependence on the multichannel load; said control means comprising:

• - a pre-processing unit having included therein means to separate control signals from a multichannel speech input, means to derive from said control signals data representing the number of interpolations to be carried out between successively received frames on said input, and means to carry out said number of interpolations; and
• - a store to temporarily store the coded speech signals for the control of said adjustable filter.

A multichannel synthesizer structured in accordance with the principles of the present invention inherently has the options to selectively control a) the number of interpolations between successively received samples of speech (set of parameters), and b) the number and/or "width dimension" (number of bits) of the parameters (filter coefficients) included in the respective speech samples. Therefore the quality of the synthesized speech can be improved when the traffic load is lowered.

An embodiment of a digital multichannel speech synthesizer is according to the present invention characterized thereby that said pre-processing unit further comprises

• - a function decoder adapted to decode control signals from said input;
• - registers, a converter, a fraction table and a counter, which in combination are effective to determine the number of interpolations to be carried out on the basis of data in said control signals;
• - a microprocessor, which in response to data derived from said fraction table and data from a speech data input controls the computation of the number of interpolations; and
• - an adder-multiplier for carrying out the interpolations under control of said microprocessor and to transfer the interpolated parameters to a computing unit included in said control means via lines.

The above embodiment is illustrative of a specific structure for the implementation of interpolation processes wherein on the basis of knowledge about the time available between successively received samples of speech, a correspondingly varied number of interpolations is carried out.

A further embodiment of a digital multichannel speech synthesizer is according to the present invention characterized thereby that said means for adjusting said speech generator in combination with said control means include

• - a series-to-parallel converter, which under control of a central processing unit selectively varies the number of bits included within the parameters provided at its input, in dependence on the multichannel load; and
• - an auxiliary control unit, which under control of said central processing unit is effective to cause a computing unit to compute a number of parameters depending on the multichannel load.

The further embodiment described above is illustrative of a specific structure by which on the basis of knowledge about the traffic load of the multichannel transmission path, (and therefore on the basis of available transmission time) the number of coefficients and/or the number of bits per coefficient can be correspondingly varied.

The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawing, in which:

• Fig. 1 is a general block diagram of a speech synthesizer;
• Fig. 2 is a block diagram of the speech synthesizer according to the invention;
• Fig. 3 illustrates a preferred embodiment of the pre-processing unit of the device according to the invention;
• Fig. 4 illustrates a preferred embodiment of the computing unit of the device according to the invention;
• Fig. 5 is the flow-chart of the pre-processing unit (9) of the device of Fig. 2 and
• Fig. 6 is the flow-chart of the central processing unit (11) of the device of Fig. 2.

Fig. 1 is a general block diagram of a speech synthesizer. The adjusting parameters for the device are designated by the letters a, b, c and d. The circuit comprises a digital noise source 1, which generates white noise for unvoiced speech components, and a digital pitch generator 2, which generates the fundamental frequency for voiced speech components and is adjusted according to parameter a. The choice between generators 1 and 2 is made by switch 3 as controlled by parameter b. Then the digital signal is applied successively to an adjustable digital ladder filter 4, controlled by parameter c, and a digital volume regulator 5, controlled by parameter d. A digital-to-analog converter 6 converts the digital signal into an analog signal. Fig. 2 is a block diagram of the device according to the invention. A digital input signal incorporating the parameters a, b, c and d is applied to input 7 of the speech synthesizer and led to a buffer 8. The parameters a, b, c and d have been determined by the "linear predictive coding" method and can come from a storage medium, in the case of a message that has to be repeated regularly or from a transmission line. A preprocessing unit 9 ensures the reading of the parameters and their storage in portion 10.1 of store 10, the interpolation of two successive groups of parameters, the transfer of the interpolation results to other parts of the circuit and the passing of control data to the central processing unit 11.

The data stored in store portion 10.1 can be transferred to a second store portion 10.2, when the preceding data stored in 10.2 have been processed. Processing takes place in a computing unit 12, which employs the interpolated data for adjusting the ladder filter (Fig. 1; 4) incorporated in the computing unit. In the meantime store portion 10.1 is filled again. The computing unit 12 of this embodiment can compute the digital speech signals for 16 speech channels simultaneously. These digital speech signals are stored in "first-in-first-out" buffers 13.1... 13.16 (one signal per channel) and then led to digital-to-analog converters 6.1... 6.16, respectively. The computing unit 12 is controlled in conformity with fixed rules by a control unit 14, which receives its instructions from the central processing unit 11.

Fig. 3 illustrates a preferred embodiment of the pre-processing unit 9 according to the invention, and store portion 10.1. The data coming from the buffer (Fig. 2; 8) are led to a series-to-parallel converter 15. The discriminator 16 infers from the first few bits of a 24-bit frame whether this frame contains speech data or control information, in which cases a data buffer 17 or a control buffer 18 is opened, respectively. The speech data are led from the data buffer 17 via a data bus 19 to a microprocessor 20, which is connected to the central processing unit (Fig. 2; 11) via a control bus 21 and an address bus 22. Store 23 (RAM) and decoding store 24 (ROM) are also connected to this data bus. Further, the circuit comprises an adder-multiplier 25 for carrying out parts of interpolation calculations.

The group of parameters comprises, as has already been observed, the following four:

• a. the pitch, for which the data are led via output 27 to the computing unit (Fig. 2; 12);
• b. the voiced/unvoiced decision, for which the data are also led to said computing unit via output 26;
• c. the reflection coefficients K↑" to K_M", 1st and Mth reflection coefficient, respectively, of the nth group of parameters read, the data of which are led to store portion 10.1, while the data transferred to store portion 10.2 are being handled;
• d. the volume of output signal C", the data of which are also led to store portion 10.1.

The data for parameters a and b have no effect upon the ladder filter (Fig. 1; 4), so that they can be handled in a different manner and need not pass the store 10, as will be described hereinafter.

The function of the speech data portion of the circuit of Fig. 3 is described as separating the parameters a, b, c and d and interpolating the parameters c and d. Interpolation is necessary, because the speech information arrives in bursts and because annoying clicks could occur without interpolation. Every time a group of data n is written in register 23, the interpolation with the preceding group of data, n-1, is carried out by the microprocessor 20 with the aid of the adder-multiplier 25 and store 24 in accordance with the formulain which i=0... L-1, L being the number of interpolations desired. indicates the number of a group interpolated between the groups n-1 (1=0) and n (I=L). The coefficientsandare generated by the microprocessor 20.

The reflection coefficients interpolated on the basis of rule (1) and the interpolated volume are led to store 10.1.

According to the invention, the pre-processing unit comprises means for adjusting the quality of the speech reproduced according to the degree of occupation of the transmission medium. Therefore, at the transmitting end, relevant data are sent along with the control signals. These data are interpreted in the function decoder 28. Further, the circuit comprises a register 29, for recording the number of interpolations to be carried out by the microprocessor 20 on the unvoiced part of the speech, and a register 30, which has an analogous function with regard to the voiced part of the speech. Registers 29 and 30 are connected to ROM store 31, which converts the number of interpolations to be carried out into a signal for positioning counter 32, stepping in synchronism with a counter incorporated in microprocessor 20. The position of counter 32 is passed to a fraction table 33 (ROM), connected via a selector 34 to control bus 21 and address bus 22. Under the control of the central processing unit (Fig. 2; 11), the number of interpolations to be carried out by the microprocessor 20 can be fixed. The circuit of Fig. 3 also contains registers 35 and 36 for recording adjusting data for the adjustable filter incorporated in the computing unit (Fig. 2; 12). The adjusting data for unvoiced speech are stored in register 35, those for voiced speech in register 36. A ROM 37, converts the adjusting data into positioning data for counter 38. Via selector 39 the counter position is passed to buses 21 and 22, after which the number of calculations to be carried out by the control unit (Fig. 2: 14) is fixed under the control of the central processing unit (Fig. 2; 11).

Furthermore, the circuit may contain a register 40 for recording a signal indicating that the next one or two frames contain no speech. The relevant data can be passed via selector 41 and buses 21 and 22 to the central processing unit (Fig. 2; 11), so that the computing unit (Fig. 2; 12) can spend the time thus saved in dealing with other channels. The circuit may comprise a register 42 and a selector 43 for recording the signal indicating that one or two new frames contain the same information as the preceding frame, so that the new frames need not be transmitted. Because the preceding frame is in the buffer (Fig. 2; 8) for interpolation purposes, repetition will suffice, so that transmission capacity is saved. In an analogous way information concerning the degree of compression and expansion of the speech signal can be received and handled.

Fig. 4 illustrates a preferred elaboration of store 10.2, computing unit 12, buffers 13 and control unit 14. The data stored in 10.1 (Fig. 2) are transferred to store 10.2 under the control of the central processing unit 11. The data stored in 10.2, containing the information for computing the digital signal to be supplied to the buffers 13, are led to multipliers 44 and 45 working in parallel, adder-subtractor 46, AND-circuit 47 and D-flip-flop 48. Selector 49 determines the number of bits to be calculated per PCM-word and a round-off factor. D-flip-flop 50 ensures in a well-known manner the adaptation to bus traffic. The results of a first calculation are written, for sixteen separate channels, in buffers 51, from which they can be output via D-flip-flops 52. The voiced/ unvoiced and pitch data are sent via output 26 to electronic switch 3 and via output 27 to generator 2, respectively, and combined by means of D-flip-flop 53 with the digital signal to be calculated. The whole algorithm can be represented by the following formulae:andin whichand

Multipliers 44 and 45 ensure the multiplications and adder-subtractor 46 carries out the adding and subtracting operations. The intermediate results of the operations are put away, every time, in the 51-buffer associated with the channel dealt with. Every time one sample has been calculated, its value is multiplied by the volume factor C_n. The various operations carried out on the data from store 10.2 are controlled by a programmable store (PROM) 54, which, under the control of a counter 55, makes a step every time after the calculation of one PCM-sample for each of the 16 channels. The stepping of counter 55 is timed by clock 56. Store 54 supplies the data required for carrying out the various operations via a control bus 57 and the address data for store 10 via address bus 58. The last instruction in store 54 relates to writing the calculated final results in buffers 13 and signalling to the central processing unit 11 (Fig. 2) that the programme has finished. Then, under the control of central processing unit 11 (Fig. 2), a fresh set of data is transferred from store 10.1 to store 10.2, clock 56 being started in order to carry out again the programme contained in store 54. The data produced by the programme will only be stored when the central processing unit 11 (Fig. 2) has found that the buffers 13 are not full. After the data have been stored in buffers 13, the programme is started again under the control of the central processing unit 11. Thus the invention provides a relatively simple device for generating, from an input signal produced by the LPC-method referred to hereinabove, an analog signal for a large number of channels. The pre-processing unit 9 and the central processing unit 11 comprise microcomputers, for which the flow-charts are given in Figs. 5 and 6, respectively. The arrangement is not relevant for a good understanding of the invention, so that the flow-chart need not be described in detail. After a start command the micro- programme stored in the control unit 14 (Fig. 4) is carried out.

As soon as counter 55 (Fig. 4) has reached its final position, the last instruction contained in store 54 passes the signal "End of programme" to the central processing unit 11, which checks whether buffers 13 are full. In the affirmative case the programme is stopped. If there is space left in ,buffers 13, the next PCM-word is calculated.