(57) Byte shifting apparatus for high speed bus architecture data processing systems comprises
a plurality of byte shifters (14, 15, 16, 17), one for each byte, each with a corresponding
number of input ports (e.g. 18, 19, 20, 22) and an output port (18). Data are read
from the bus (13) into each byte shifter through one of its input ports selected by
shift control means (37) and are returned to the bus through its output port. Fill
logic (56) is provided for filling bytes with ones or zeros as required before returning
them to the bus. Checking means, not shown in Figure 1, are provided within each byte
shifter for checking bit parity, shift error, shift select error, and loading of the
buffer register within the shifter with the shifted byte.
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