Solid-state imaging device

Description

[0001] The present invention relates to a solid state imaging device comprising a photosensing unit having a plurality of picture elements arranged in a matrix form, each of said picture elements including a photo-electric conversion element and a switching insulated gate field effect transistor for reading an optical signal from said photo-electric conversion element; vertical gate lines each connected to the gates of the switching insulated gate field effect transistors for the picture elements on the same row; a vertical shift register for producing vertical scan pulses; and a simultaneous two-line selection circuit for simultaneously selecting two of said vertical gate lines to simultaneously read the two lines. Such an imaging device is described in GB-A-2 001 504 representative of the prior art.

[0002] Fig. 1 shows a schematic diagram of a conventional solid-state area image sensor. It comprises a number of photodiodes 1 as photo-electric conversion elements arranged in a matrix form, vertical switching insulated gate field effect transistors (MOSTs) 2 and horizontal switching MOSTs 3 for reading out desired signals stored in the photodiodes 1, and vertical and horizontal shift registers 4 and 5 for sequentially switching the switches 2 and 3. A part including the photodiode 1 and the vertical switching MOST 2 for each picture element forms a photosensing part. Numeral 6 denotes vertical gate lines, numeral 7 denotes vertical signal output lines, numerals 8, 16, 17, 18 and 19 denote horizontal gate lines, and numerals 9 and 10 denote horizontal signal output lines which are connected to signal output terminals. The vertical and horizontal switching MOSTs 2 and 3 have their gate voltages controlled by the shift registers 4 and 5 to carry out the switching operations.

[0003] In orderto improve a vertical resolution in such an imaging device, a signal readout scheme called an interlace mode operation has been used. By way of example, when the vertical gate lines 6 are designated by A, B, ... from the bottom to the top in Fig. 1, signals on the lines A+B, C+D, E+F,... are read in a first field period, and signals on the lines A, B+C, D+E,... are read in a second field period.

[0004] In Fig. 1, numeral 11 denotes an interlace circuit which allocates the output pulses or vertical scan pulses of the vertical shift register 4 to the vertical gate lines of the respective fields F, and F₂. Fig. 2 shows a conventional interlace circuit. In Fig. 2, the pulses are applied to the vertical gate lines in the sequence of A+B, C+D, E+F, ... in the first field (F,) period, to read the signals. In the next field (F₂) period, the pulses are applied in the sequence of A, B+C, D+E, ... to read the signals. In this manner, the signals are read in the interlace mode. A timing of the pulses of the circuit of Fig. 2 is shown in Fig. 3.

[0005] In the signal readout scheme of the solid-state imaging device of Fig. 1 in conjunction with Figs. 2 and 3, a D.C. level of a video signal varies depending on a field so that a flicker appears on a reproduced picture image. A mechanism of the generation of the flicker is explained with reference to Figs. 4 and 5. Fig. 4 shows some picture elements in the photosensing part shown in Fig. 1. Each picture element comprises a photodiode 43 and a vertical switching MOST 44. Numerals 30, 31 and 32 denote vertical gate lines, numerals 41 and 42 denote coupling capacitances, numeral 43 denotes photodiodes, numeral 44 denotes vertical switching MOSTs and numerals 46 and 47 denote vertical signal output lines to which video bias voltages V_v are externally applied. Considering a potential V_sc of the photodiode 43, when a potential of the vertical gate line C (31) is high, V_sc is substantially equal to the video bias V_v so that a reset state is attained, but when the potential of C is low, V_sc falls because of the coupling capacitance which is parasitically present between the vertical gate line and the photodiode. The coupling capacitance varies with the field. Fig. 5 shows a variation thereof and a pulse timing.

[0006] Referring to Fig. 5, in the first field in which the first field switching pulse F, is of high level, the vertical gate lines C (31) and D (32) (Fig. 4) are selected at the same timing, and in the second field in which the second field switching pulse F₂ is of high level, the vertical gate lines B (30) and C (31) are simultaneously selected. Considering V_sc, when the vertical gate line C changes from the high level to the low level (at the timing shown by 53 and 55) in the F, field, only CPC1 (41) acts as the coupling capacitance because the vertical gate line B remains at the low level. As a result, the drop ΔV_s↑ of V_sc is small as shown by 51 in Fig. 5. On the other hand, when the vertical gate line C changes from the high level to the low level (at timing 54) in the F₂ field, the vertical gate line B also changes from the high level to the low level. As a result, both C_PC1 (41) and C_PB2 (42) act as the coupling capacitance so that the drops of V_sc (ΔV_S2 52 in Fig. 5) is larger than that in the F, field.

[0007] Since the drops V_sc are superimposed on drops (56, 57) due to the optical signal, a signal equivalent to ΔV_S2-OV_S1 apparently appears or disappears in each field so that the flicker appears in each field of the reproduced picture image particularly when the signal is low. Accordingly, when the device is used under a low illumination, the reproduced picture image is of low quality because of the flicker and the flicker materially deteriorates the characteristic of the solid-state imaging device.

[0008] It is an object of the present invention to provide a flicker free readout system in a solid-state imaging device operated in an interlace mode by simultaneous selection of two vertical gate lines or picture element rows.

[0009] It is another object of the present invention to provide a high sensitivity solid-state imaging device which can produce a high quality of image even at a low illumination.

[0010] In order to achieve the above objects, the present invention is characterised in that a buffer circuit is inserted between said vertical gate lines and said simultaneous two-line selection circuit for first turning off the vertical gate line for the picture element row which has a coupling capacitance with only one of the two selected vertical gate lines and thereafter turning off the vertical gate line for the picture element row which is encircled by the two selected vertical gate lines and has coupling capacitances therewith.

[0011] The present invention will now be explained in conjunction with the accompanying drawings, in which:

Fig. 1 shows a schematic circuit diagram of a conventional MOS solid-state area imaging device;

Fig. 2 shows a circuit diagram of an interlace circuit shown in Fig. 1 together with a vertical shift 10 register;

Fig. 3 shows a timing chart of pulses in the circuit of Fig. 2;

Figs. 4 and 5 illustrate a mechanism of generation of flicker, Fig. 4 being a circuit diagram of part of the device of Fig. 1 including some picture elements and Fig. 5 showing a pulse timing and a variation of the coupling capacitance;

Fig. 6 shows a schematic circuit diagram of a solid-state imaging device according to an embodiment of the present invention;

Fig. 7 shows a circuit diagram of a buffer circuit shown in Fig. 6 together with an interface circuit and a vertical shift register; and

Fig. 8 shows a timing chart of pulses for explaining the operation of the buffer circuit shown in Fig. 7.

[0012] In Fig. 6 which shows a schematic circuit diagram of a solid-state imaging device according to one embodiment of the present invention, numeral 101 denotes a novel buffer circuit. Fig. 7 shows an example of the buffer circuit together with a vertical shift register and an interlace circuit, and Fig. 8 shows a timing chart for explaining the operation of the buffer circuit of Fig. 7.

[0013] In Fig. 7, numeral 121 denotes a part of the vertical shift register 4. Numerals 122 to 131 denote field switching MOSTs for interlace operation, four field switching MOSTs being provided for each stage of the vertical shift register, numerals 132 and 133 denote first and second field pulse lines for supplying first and second field switching pulses F, and F₂, and these elements forms an interlace circuit 11. Numerals 161 to 166 denote vertical gate lines, numerals 147 and 148 denote first and second drive pulse lines for supplying first and second drive pulses P, and P₂ which are to be applied to the vertical gate lines and are synchronized with the vertical scan pulses V₁ to V₃ from the vertical shift register 121, numerals 141 to 146 denote transfer MOSTs for sequentially selecting P, and P₂, numeral 170 denotes bootstrap capacitances, numerals 167 and 168 denote first and second reset lines for supplying first and second reset pulses P₃ and P₄ to fully turn off the voltages on the vertical gate lines, and numerals 151 to 156 denote reset MOSTs controlled by the reset pulses P₃ and P₄.

[0014] Referring to the timing chart shown in Fig. 8, the operation of the buffer circuit of Fig. 7 is now explained.

[0015] The first and second field pulses F, and F₂ select the corresponding field switching MOSTs (122 to 131). For example, when F₂ is ON (high level), the pairs of MOSTs 124, 125; 128, 129,; ... are selected. This corresponds to the selection of the pairs of vertical gate lines B, C; D, E; .... When F₁ is ON, the pairs of MOSTs 122,123; 126,127; 130, 131 are selected. It corresponds to the selection of the vertical gate lines A, B; C, D; .... In this manner, the interlace operation is carried out by F, and F₂.

[0016] For example, if the pulses P, and P₂ are turned ON (high level) when V₂ is ON (high level) and F₂ is ON, the corresponding gate lines 162 (B) and 163 (C) are turned ON (high level) (attime t₁ in Fig. 8). By the provision of the bootstrap capacitances 170 as shown in Fig. 7, the potentials on the vertical gate lines are raised to the high levels of the pulses P₁ and P₂ independently of the threshold voltages of the transistors (142, 143).

[0017] After the signals of the photodiodes have been read onto the vertical signal output lines, P, is turned OFF (low level) and P₃ is turned ON (high level) so that the vertical gate line 162 (B) is turned OFF (low level) (at time t₂). After the line B has been turned OFF, P₂ is turned OFF (low level) and P₄ is turned ON (high level) so that the line C is turned OFF (low level).

[0018] Thus, by controlling the timing of P, to P₄ as shown in (a) of Fig. 8 by the buffer circuit shown in Fig. 7, the vertical gate line B can be turned OFF prior to the vertical gate line C. This is true for the pairs of D and E, ... which have been selected. In the field in which F, is ON, the pairs A, B; C, D; ... are selected. In this case, by exchanging the timings of P, and P₂, and P₃ and P₄, the gate line A can be turned OFF prior to B, and the gate line C can be turned OFF prior to D.

[0019] Referring to Fig. 4, it is assumed that B and C have been selected and turned ON, and B is to be first turned OFF and then C is to be turned OFF next. When B is turned OFF, the transistor 44 is still conducting. Accordingly, the potential V_SC of the photodiode 43 is not affected by the presence of the coupling capacitance C_PB2 and the potential drops by the presence of the coupling capacitance C_PC1 when the vertical gate line 31 (C) is turned OFF. Accordingly, the variation of the potential of V_sc is equal to that produced when C is turned OFF in the other field (in which F₁ is ON) where C and D are simultaneously selected. Thus, there is no variation among the fields and the flicker does not occur. According to the embodiment shown in Figs. 7 and 8, the solid-state imaging device which is free from the flicker and enables the simultaneous selection of two vertical gate lines or picture element rows is provided. The change of V_SC in the above operation is also shown in (b) of Fig. 8. Fig. 8 further shows a drive pulse timing (a) of the buffer circuit shown in Fig. 7. In Fig. 8, the offset of timing at the transition to OFF is presented by switching the timings of the pulses P_i, P₃, P₂, P₄ for each field.

[0020] It should be understood that the buffer circuit is not limited to the particular circuit shown in Fig. 7. For example, the drive pulse lines for P, and P₂ may be common. In this case, the timing is to be adjusted such that after V,, V₂, ... (vertical register outputs) have been changed from ON to OFF, the reset pulses P₃ and P₄ are turned ON. In this manner, the outputs (A, B, ...) as shown in (b) of Fig. 8 are produced. Conversely, P3 and P₄ may be common. In this case, the common pulses P₃ and P₄ is synchronized with one of P, and P₂ which is later turned OFF.

[0021] An essential feature of the present invention resides in the solid-state imaging device operated in the simultaneous selection mode of two lines in which the gate line for the photodiode which has the coupling capacitance with only one of the two selected vertical gate lines is turned OFF first and the gate line for the photodiode which is encircled by the two selected vertical gate lines and has coupling capacitances therewith is turned OFF next so that the flicker which would otherwise be caused by the unbalance of the coupling capacitances among the fields is prevented and the high sensitivity solid-state imaging device which can produce a high quality of image under a low illumination is provided. The drive circuits and the pulse sequences are not limited to the illustrated examples.

[0022] While the horizontal scan in Fig. 6 is carried out by the horizontal switching MOSTs 3 and the horizontal shift register 5, it should be understood that the present invention is equally applicable to a solid-state imaging device which carries out the horizontal scan and read by a change transfer device (CTD) as shown in U.S. Patent Application Serial No. 206,865 filed on November 14,1980 (or equivalent EPC Application No. 80.304072.4 filed on November 13, 1980).

Claims

1. A solid-state imaging device comprising a photosensing unit having a plurality of picture elements arranged in a matrix form, each of said picture elements including a photo-electric conversion element (1) and a switching insulated gate field effect transistor (2) for reading an optical signal from said photo-electric conversion element; vertical gate lines (6) each connected to the gates of the switching insulated gate field effect transistors for the picture elements on the same row; a vertical shift register (4) for producing vertical scan pulses; and a simultaneous two-line selection circuit (11) for simultaneously selecting two of said vertical gate lines to simultaneously read the two lines; characterised in that a buffer circuit (101) is inserted between said vertical gate lines and said simultaneous two-line selection circuit for first turning off the vertical gate line for the picture element row which has a coupling capacitance with only one of the two selected vertical gate lines and thereafter turning off the vertical gate line for the picture element row which is encircled by the two selected vertical gate lines and has coupling capacitances therewith.

2. A solid-state imaging device according to Claim 1, wherein said buffer circuit includes transfer MOSTs (141 to 146) which are provided for said vertical gate lines (161 to 166), respectively, said transfer MOSTs receiving as gate input pulses the output signals from said simultaneous two-line selection circuit and driven by drive pulses (P₁, P₂) synchronized with the vertical scan pulses (V_i, V₂, V₃) from said vertical shift register (121), and reset MOSTs (151 to 156) which are controlled by reset pulses (P₃, P₄) to reset said vertical gate lines.

3. A solid-state imaging device according to Claim 2, wherein said simultaneous two-line selection circuit is an interlace scanning circuit which rearranges the two vertical gate lines to be selected in each field.

4. A solid-state imaging device according to Claim 3, wherein said interlace circuit includes first to fourth field switching MOSTs connected to each stage of said vertical shift register, first and second field switching pulses (F_t, F₂) being applied to the pair of said first and second field switching MOSTs (123, 122; 127, 126; 131, 130) and the pair of said third and fourth field switching MOSTs (125, 124; 129, 128), respectively, so that said first and second field switching MOSTs are activated in a first field and said third and fourth field switching MOSTs are activated in a second field, by the vertical scan pulses sequentially produced from said vertical shift register and said first and second field switching pulses, to produce said gate input pulses for said transfer MOSTs of said buffer circuit.

5. A solid-state imaging device according to Claim 4, wherein ones of the sources and drains of said first to fourth field switching MOSTs (124 to 127) provided for each stage of said vertical shift register are connected to the output of a selected stage of said vertical shift register, the others of the sources and drains of the first field switching MOST (123) provided for the preceding vertical shift register stage and of the fourth field switching MOST (124) provided for the selected vertical shift register stage, the others of the sources and drains of the third and second field switching MOSTs (125, 126) provided for the selected vertical shift register stage, and the others of the sources and drains of the first field switching MOST (127) provided for the selected vertical shift register stage and of the fourth field switching MOST (128) provided for the next vertical shift register stage are, respectively, connected to the gates of the transfer MOSTs (142, 143, 144) provided for the three successive ones (162,163,164) of said vertical gate lines, and said first field switching pulse (F₁) is applied to the gates of said first and second field switching MOSTs while said second field switching pulse (F₂) is applied to the gates of said third and fourth field switching MOSTs.

6. A solid-state imaging device according to Claim 5, wherein ones of the drains and sources of said transfer MOSTs are coupled to said drive pulses (P₁, P₂) while the others of the drains and sources of said transfer MOSTs are connected to said vertical gate lines.

7. A solid-state imaging device according to Claim 6, wherein the ones of the drains and sources of the transfer MOSTs (142, 144, 146) connected to the odd row vertical gate lines (162, 164, 166) are coupled to a first one (P,) of said drive pulses while the drains (sources) of the transfer MOSTs (141, 143, 145) connected to the even row vertical gate lines are coupled a second one (P₂) of said drive pulses, said first and second drive pulses changing from high levels to low levels at different timings.

8. A solid-state imaging device according to Claim 6, wherein ones of the drains and sources of said reset MOSTs (151 to 156) are connected to said vertical gate lines and the others of the drains and sources of said reset MOSTs are grounded.

9. A solid-state imaging device according to Claim 8, wherein the gates of the reset MOSTs (152, 154, 156) connected to the odd row vertical gate lines (162, 164, 166) are coupled to a first reset pulse (P₃) and the gates of the reset MOSTs connected to the even row vertical gate lines (161, 163,165) are coupled to a second reset pulse (P₄), said first and second reset pulses changing from low levels to high levels at different timings.

Revendications

1. Dispositif de formation d'images à l'état solide comportant une unité de photodétection comprenant une pluralité d'éléments d'image disposés sous la forme d'une matrice et dont chacun d'eux comporte un élément de conversion photoélectrique (1) et un transistor à effet de champ à grille isolée de commutation (2) servant à lire un signal optique délivré par l'élément de conversion photoélectrique, des lignes verticales (6) de liaison de grilles, qui sont raccordées aux différentes grilles des transistors à effet de champ à grilles isolées de commutation pour les éléments d'image situés sur la même ligne, un registre à décalage vertical (4) servant à produire des impulsions de balayage vertical, et un circuit (11) de sélection simultanée de deux lignes, servant à réaliser la sélection simultanée desdites lignes verticales de liaison de grilles pour réaliser la lecture simultanée des deux lignes, caractérisé en ce qu'un circuit tampon (101) est inséré entre lesdites lignes verticales de liaison de grilles et ledit circuit de sélection simultanée de deux lignes, pour réaliser tout d'abord le débranchement de la ligne de liaison de grille pour la ligne d'éléments d'image, qui possède une capacité de couplage avec seulement l'une des deux lignes verticales sélectionnées de grilles et pour réaliser ensuite le débranchement de la ligne verticale de liaison de grilles pour la ligne d'éléments d'image qui est entourée par les deux lignes verticales sélectionnées de liaison de grilles et possède des capacités de couplage avec ces lignes.

2. Dispositif de formation d'images à l'état solide selon la revendication 1, dans lequel ledit circuit tampon comprend des transistors MOST de transfert (141 à 146) qui sont prévus respectivement pour lesdites lignes verticales de liaison de grilles (161 à 166), lesdits transistors MOST de transfert recevant en tant qu'impulsions d'entrée de grille les signaux de sortie délivrés par ledit circuit de sélection simultané de deux lignes et commandé par des impulsions de commande (P_i, P₂) synchronisées avec les impulsions de balayage vertical (V" V₂, V₃) délivrées par ledit registre à décalage vertical (121), et des transistors MOST de remise à l'état initial (151 à 156), qui sont commandés par des impulsions de remise à l'état initial (P₃, P₄) de manière à remettre à l'état initial lesdites lignes verticales de liaison de grilles.

3. Dispositif de formation d'images à l'état solide selon la revendication 2, dans lequel ledit circuit de sélection simultanée de deux lignes est un circuit de balayage entrelacé qui réarrange les deux lignes verticales de liaison de grille, qui doivent être sélectionnées dans chaque trame.

4. Dispositif de formation d'images à l'état solide selon la revendication 3, dans lequel ledit circuit d'entrelacement comprend un premier, un second, un troisième et un quatrième transistors MOST de commutation de trame raccordés à chaque étage dudit registre à décalage vertical, des première et second impulsions de commutation de trame (F_i, F₂) éant appliquées au couple desdits premier et second transistors MOST de commutation de trames (123, 122; 127, 126; 131, 130) et au couple desdits premier et quatrième transistors MOST de commutation de trames (125, 124; 129, 128) respectivement de telle sorte que lesdits premier et second transistors MOST de commutation de trames sont activés pendant une première trame et que lesdits troisième et quatrième transistors MOST de commutation de trames sont activés pendant une seconde trame, par les impulsions de balayage vertical produites d'une manière séquentielle par ledit registre à décalage vertical et par lesdites premières et secondes impulsions de commutation de trames, afin de produire lesdites impulsions d'entrée de grilles pour lesdits transistors MOST de transfert dudit circuit tampon.

5. Dispositif de formation d'images à l'état solide selon la revendication 4, dans lequel certaines des sources et des drains desdits premier, deuxième, troisième et quatrième transistors MOST de commutation de champ (124 à 127) prévus pour chaque étage dudit registre à décalage vertical sont raccordés à la sortie d'un étage sélectionné dudit registre à décalage vertical, les autres des sources et des drains du premier transistor MOST de commutation de trames (123) prévu pour l'étage du registre à décalage vertical précédent, et du quatrième transistor MOST de commutation de trames (124) prévu pour l'étage de registre à décalage vertical sélectionné, les autres des sources et des drains des premier et second transistors MOST de commutation de trames (125, 126) prévus pour l'étage de registre à décalage vertical sélectionné, et les autres des sources et drains du premier transistor MOST de commutation de trames (127) prévus pour l'étage de registre à décalage vertical sélectionné et du quatrième transistor MOST de commutation de trame (128) prévu pour l'étage du registre à décalage vertical suivant sont raccordés respectivement aux grilles des transistors MOST de transfert (52, 53, 54) prévus pour les trois lignes successives (162, 163, 164) faisant partie desdites lignes verticales de liaison de grilles, et ladite première impulsion de commutation de trames (F₁) est appliquée aux grilles desdits premier et second transistors, MOST de commutation de trames, tandis que ladite seconde impulsion de commutation de trames (F₂) est appliquée aux grilles desdits troisième et quatrième transistors MOST de commutation de trames.

6. Dispositif de formation d'images à l'état solide selon la revendication 5, dans lequel certains des drains et des sources desdits transistors MOST de transfert sont accouplés auxdites impulsions, de commande (P_i, P₂) tandis que les autres des drains et des sources desdits transistors MOST de transfert sont raccordés auxdites lignes verticales de liaison de grilles.

7. Dispositif de formation d'images à l'état solide selon la revendication 6, dans lequel certains des drains et des sources des transistors MOST de transfert (142, 144, 146) raccordés aux lignes verticales de liaison de grilles (162, 164, 166) de lignes impaires sont accouplés à une première impulsion (P,) faisant partie desdites impulsions de commande, tandis que les drains (sources) des transistors MOST de transfert (141, 143, 145) raccordés au lignes verticales de liaison de grilles de rangés paires sont accouplés à une second impulsion (P₂) faisant partie desdites impulsions de commande, lesdites première et seconde impulsions de commande passant de niveaux hauts à des niveaux bas selon des cadencements différents.

8. Dispositif de formation d'images à l'état solide selon la revendication 6, dans lequel certains des drains et des sources desdits transistors MOST de remise à l'état initial (151 à 156) sont raccordés auxdites lignes verticales de liaison de grilles et les autres des drains et sources desdits transistors MOST de remise à l'état initial sont mis à la masse.

9. Dispositif de formation d'images à l'état solide selon la revendication 8, dans lequel les grilles des transistors MOST de remise à l'état initial (152, 154, 156) raccordés aux lignes verticales de liaison de grilles (162, 164, 166) de lignes impaires sont accouplées à une première impulsion de remise à l'état initial (P₃) et les grilles des transistors MOST de remise à l'état initial raccordées aux lignes verticales de liaison de grilles (161, 163, 165) de lignes paires sont accouplées à une seconde impulsion de remise à l'état initial (P₄), lesdites première et second impulsions de remise à l'état initial passant de niveaux bas à des niveaux hauts selon des cadencements différents.

Ansprüche

1. Festkörper-Bildaufnahmevorrichtung mit einer Fotosensor-Einheit mit einer Vielzahl von in einer Matrixform angeordneten Bildelementen, wobei jedes der Bildelemente ein fotoelektrisches Wandlerelement (1) und einen schaltenden Feldeffekttransistor mit isolierter Gate-Elektrode (2) für das Lesen eines optischen Signals von dem fotoelektrischen Wandlerelement umfaßt;

vertikalen Gate-Leitungen (6), die jeweils mit den Gate-Anschlüssen der schaltenden Feldeffekttransistoren mit isolierter Gate-Elektrode für die Bildelemente in derselben Zeile verbunden sind;

einem vertikalen Schieberegister(4) für die Erzeugung vertikaler Abtastimpulse; und

einem simultanen Zweileitungs-Auswahlschaltkreis (11) für das simultane Auswählen von zwei der genannten vertikalen Gate-Leitungen, um die zwei Leitungen simultan zu lesen;

dadurch gekennzeichnet, daß zwischen die vertikalen Gate-Leitungen und den simultanen Zweileitungs-Auswahlschaltkreis ein Pufferschaltkreis (101) eingefüht ist, um zuerst die vertikale Gate-Leitung für die Bildelement-Zeile auszuschalten, dit mit nur einer der beiden gewählten vertikalen Gate-Leitungen eine Kopplungskapazität hat, und um danach die vertikale Gate-Leitung für die Bildelement-Zeile auszuschalten, die von den zwei gewählten vertikalen Gate-Leitungen umgeben ist und mit diesen Kopplungskapazitäten hat.

2. Festkörper-Bildaufnahmevorrichtung nach Anspruch 1, wobei der Pufferschaltkreis umfaßt:

Transfer-MOSTs (141 bis 146), die jeweils für die genannten vertikalen Gate-Leitungen (161 bis 166) vorgesehen sind, als Gate-Eingangsimpulse die Ausgangssignale von dem genannten simultanen Zweileitungs-Auswahlschaltkreis empfangen und durch Ansteuer-Impulse (P_i, P₂) angesteuert werden, die mit den vertikalen Abtast-Impulsen (V_i, V₂, V₃) von dem vertikalen Schieberegister (121) synchronisiert sind, und

Rücksetz-MOSTs (151 bis 156), die durch Rücksetz-Impulse (P₃ P₄) gesteuert werden, um die vertikalen Gate-Leitungen zurückzusetzen.

3. Festkörper-Bildaufnahmevorrichtung nach Anspruch 2, wobei der simultane Zweileitungs-Auswahlschaltkreis eine verschränkte Abtastschaltung ist, die die in jedem Feld auszuwählenden zwei vertikalen Gate-Leitungen umordnet.

4. Festkörper-Bildaufnahmevorrichtung nach Anspruch 3, wobei die verschränkte Schaltung erste bis vierte Feld-Schalt-MOSTs umfaßt, die mit jeder Stufe des vertikalen Schieberegisters verbunden sind, wobei erste und zweite Feld-Schalt-Impulse (F" F₂) an das Paar der ersten und zweiten Feld-Schalt-MOSTs (123, 122; 127, 126; 131,130) bzw. an das Paar der dritten und vierten Feld-Schalt-MOSTs (125, 124; 129, 128) angelegt werden, so daß durch die von dem vertikalen Schieberegister sequentiell erzeugten vertikalen Abtast-Impulse und die ersten und zweiten Feld-Schalt-Impulse die ersten und zweiten Feld-Schalt-MOSTs in einem ersten Feld aktiviert werden und die dritten und vierten Feld-Schalt-MOSTs in einem zweiten Feld aktiviert werden, um die Gate-Eingangs-Impulse für die Transfer-MOSTs des Pufferschaltkreises zu erzeugen.

5. Festkörper-Bildaufnahmevorrichtung nach Anspruch 4, wobei die einen der Source- und Drain-Anschlüsse der für jede Stufe des vertikalen Schieberegisters vorgesehenen ersten bis vierten Feld-Schalt-MOSTs (124 bis 127) mit dem Ausgangs einer gewählten Stufe des vertikalen Schieberegisters verbunden sind, die anderen der Source- und Drain-Anschlüsse des für die vorhergehende Stufe des vertikalen Schieberegisters vorgesehenen ersten Feld-Schalt-MOST (123) und des für die gewählte Stufe des vertikalen Schieberegisters vorgesehenen vierten Feld-Schalt-MOST (124), die anderen der Source-und Drain-Anschlüsse der für die gewählte Stufe des vertikalen Schieberegisters vorgesehenen dritten und zweiten Feld-Schalt-MOSTs (125, 126) und die anderen der Source- und Drain-Anschlüsse des für die gewählte Stufe des vertikalen Schieberegisters vorgesehenen ersten Feld-Schalt-MOST (127) bzw. des für die nächste Stufe des vertikalen Schieberegisters vorgesehenen vierten Feld-Schalt-MOST (128) mit den Gate-Anschlüssen der Transfer-MOSTs (142, 143, 144) verbunden sind, die für die drei aufeinanderfolgenden (162, 163, 164) der vertikalen Gate-Leitungen vorgesehen sind, und wobei der erste Feld-Schalt-Impuls (F,) an die Gate-Anschlüsse der ersten und zweiten Feld-Schalt-MOSTs angelegt wird, während der zweite Feld-Schalt-Impuls (F₂) an die Gate-Anschlüsse der dritten und vierten Feld-Schalt-MOSTs angelegt wird.

6. Festkörper-Bildaufnahmevorrichtung nach Anspruch 5, wobei die einen der Drain- und Source-Anschlüsse der Transfer-MOSTs mit den genannten Ansteuer-Impulsen (P₁, P₂) gekoppelt sind, während die anderen der Drain- und Source-Anschlüsse der Transfer-MOSTs mit den vertikalen Gate-Leitungen verbunden sind.

7. Festkörper-Bildaufnahmevorrichtung nach Anspruch 6, wobei die einen der Drain- und Source-Anschlüsse der Transfer-MOSTs (142, 144, 146), die mit den vertikalen Gate-Leitungen (162, 164, 166) einer ungeraden Zeile verbunden sind, mit einem ersten (P₁) der Ansteuer-Impulse gekoppelt sind, während die Drain(Source)-Anschlüsse der Transfer-MOSTs (141, 143, 145), die mit den vertikalen Gate-Leitungen einer geraden Zeile verbunden sind, mit einem zweiten (P₂) der Ansteuer-Impulse gekoppelt sind, wobei sich die ersten und zweiten Ansteuer-Impulse zu verschiedenen Zeitpunkten von hohen Pegeln auf niedrige Pegel verändern.

8. Festkörper-Bildaufnahmevorrichtung nach Anspruch 6, wobei die einen der Drain- und Source-Anschlüsse der Rücksetz-MOSTs (151 bis 156) mit den vertikalen Gate-Leitungen verbunden sind, und die anderen der Drain- und Source-Anschlüsse der Rücksetz-MOSTs geerdet sind.

9. Festkörper-Bildaufnahmevorrichtung nach Anspruch 8, wobei die Gate-Anschlüsse der mit den vertikalen Gate-Leitungen (162, 164, 166) einer ungeraden Zeile verbundenen Rücksetz-MOSTs (152,154,156) mit einem ersten RücksetzImpuls (P₃) gekoppelt sind, und die Gate-Anschlüsse der mit den vertikalen Gate-Leitungen (161, 163, 165) einer geraden Zeile verbundenen Rücksetz-MOSTs mit einem zweiten RücksetzImpuls (P₄) gekoppelt sind, wobei sich die ersten und zweiten Rücksetz-Impulse zu verschiedenen Zeitpunkten von niedrigen Pegeln auf hohe Pegel verändern.

Drawing