(19)
(11) EP 0 078 363 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
18.09.1985 Bulletin 1985/38

(43) Date of publication A2:
11.05.1983 Bulletin 1983/19

(21) Application number: 82106648

(22) Date of filing: 23.07.1982
(84) Designated Contracting States:
DE FR GB

(30) Priority: 29.10.1981 US 316160

(71) Applicant: International Business Machines Corporation
 ()

(72) Inventors:
  • Thomas, David Ross
     ()
  • Tien, Paul Chung
     ()

   


(54) Fet memory with drift reversal


(57) in response to a periodic pulse on a lead (21), an FET (47) connected gate-to-drain is given in a low current circuit, producing a threshold potential on node F. This is connected through switch FET's (61) to the word lines (1) of a memory. This holds the gates of memory access switches (5) at threshold. A higher voltage on the bit line (7) takes off change in memory cells (40) which have drifted from zero charge stored toward the substrate voltage. Absence of the periodic signal activates an FET (59) which grounds node F. High voltage applied to a word line (1) switches off the FET (61) connecting that line to node F.






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