(57) A multiprocessing three level memory hierarchy implementation is described which
uses a "write" flag and a "share" flag per pages of information stored in a level
three main memory. These two flag bits are utilized to communicate from main memory
(4) at level three to private and shared caches (12, 27; 20, 30; 14; 22) at memory
levels one and two how a given page of information is to be used. Essentially, pages
which can be both written and shared are moved from main memory to the shared level
two cache and then to the shared level one cache, with the processors executing from
the shared level one cache. All other pages are moved from main memory to the private
level two and level one caches of the requesting processor. Thus, a processor executes
either from its private or shared level one cache. This allows several processors
to share a level three common main memory without encountering cross interrogation
overhead. If uniform status within a page cannot be guaranteed at the main memory
interface, the shared cache configuration does not interface with main memory but,
in parallel, with the private caches at an appropriate intermediate level.
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