(19)
(11) EP 0 093 954 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
03.10.1984 Bulletin 1984/40

(43) Date of publication A2:
16.11.1983 Bulletin 1983/46

(21) Application number: 83104112

(22) Date of filing: 27.04.1983
(84) Designated Contracting States:
DE GB

(30) Priority: 28.04.1982 JP 7037382

(71) Applicant: HITACHI, LTD.
 ()

(72) Inventors:
  • Ikeda, Tetsuya
     ()
  • Komatsu, Shigeru
     ()
  • Hirahata, Shigeru
     ()
  • Koyama, Tokuo
     ()

   


(54) Image display memory unit


(57) An image display memory unit having a plurality of display memories (6, 7, 8) connected to a plurality of data lines of data bus (3) one for each display memory chip and addressable for each bit of the data bus comprises a display memory chip selection circuit (13) for selecting the display memory chip for each data bit on the same address, and a write control circuit (16, 17, 18) for controlling writing for each display memory. The dot-by-dot coloring is attained only by a software processing of controlling write information for each display memory and selecting the display memory chip.






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