(57) An interface circuit (10) for coupling a parallel data device (12) to a serial data
channel (14,16) over which Manchester-type codes are transmitted. In the interface
circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop
(50), an exclusive-ore gate (52), and at least one delay line (58A or 588) separates
the data and clocking signals. The serial data signals are clocked into a serial register
(30) under control of the external clocking signals from the channel. A carrier detector
(24) enables the serial register only when valid information signals are present.
A parallel data register (40) receives in parallel the data from the serial data register.
To get in phase the external clocking signals with the internal clock source, an internal
clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence
of a synchronizing character that is transmitted over the serial data channel. In
this fashion, the internal operations of the parallel data transfers are in phase,
but isolated from the external clocking signals so that in the event that the external
clocking signals become corrupted due to noise or simultaneous transmissions of information
signals by different devices, the internal parallel transfer operations may continue
freely without disruption.
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