A pulse width modulation circuit and an analog product forming integration circuit using such modulation circuit

Abstract

 A pulse width modulation circuit is capable of cancelling the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits (FF3, L1, L2) to an existing pulse width modulation circuit (10, CP3). Such pulse width modulation circuit is used preferably in an integration circuit forming the product of two analog signals.
The offset of the triangular wave signal (VA) is cancelled by inverting either the triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal, in every predetermined period. To this end, the circuit eliminates the offset of a comparator (CP3) by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

Description

BACKGROUND OF THE INVENTION

[0001] This invention relates to a pulse width modulation circuit using a triangular wave generation circuit and to an integration circuit using the pulse width modulation circuit. More particularly, the present invention relates to an integration circuit which is particularly suitable for generating pulses in such a number as to be proportional to the integration of the product of two signals, and also to a pulse width modulation circuit used in the former.

[0002] Figure 1 illustrates a two-phase electronic type energy meter produced by modifying a three- phase electric energy meter disclosed on page 257 of INT. J. Electronics, 1980, Vol. 48, No. 3.

[0003] A triangular wave generation circuit 10 consists of an integrator INT1 which selectively receives d.c. voltages V_B and -V_B via a switch SWl, a flip-flop FF1 generating a signal SΔ which controls the switch SW1 and first and second comparators CP1 and CP2 which control set and reset of the flip-flop, respectively. The integrator INT1 consists of a resistor Rl, a capacitance Cl and an amplifier Al. The comparators CP1 and CP2 compare the output of the amplifier Al with the reference voltages V_R and -V_R and generate signals for setting and resetting the flip-flop FF1 when they are in agreement, respectively. The switch SW1 changes over the voltage to V_B and -V_B when the signal SΔ is 0 and 1, respectively, and applies the voltage to the integrator INT1. Thus, the output signal VΔ from the circuit 10 becomes a triangular wave having an inclination of V_B/(R₁C₁) in both positive and negative and a peak of ±V_R. This output signal VΔ is applied to the non-inversion input terminal of the comparator CP3, and a first a.c. signal E_V or its inversion signal -E_V is applied as an input voltage V_X to the inversion input terminal of the comparator CP3. The switch SW3 selects the signals -E_V and E_V when the later- appearing signal S_V is 1 and 0, respectively.

[0004] The output V of the comparator CP3 becomes "1" and "0" when the level difference between the triangular wave VΔ and the input voltage V_x is positive and negative, respectively. Thus, the output signal V_g becomes a signal formed by modulating the pulse width of the input signal V_x.

[0005] Here, the degree of pulse modulation D is defined in the following manner:

where a is the time in which V_g is "1" during one cycle of V_g (that is, one cycle of the triangular wave VA), and b is the time in which V is "0".

[0006] On-the other hand, the comparator CP3 generates V₉ = "0" and V_g = "1" when V_X>VΔ and when V_x<VΔ, respectively. Accordingly, the following equations are given with T representing one cycle of the triangular wave:

[0007] Accordingly, the degree of pulse modulation D can be expressed as follows:

[0008] Here, it is assumed that the frequency of the triangular wave is selected to be sufficiently higher than the frequency of the signal S_v and that of the signal E_v.

[0009] The signal V_g modulated in this manner controls the selector switch SW2 for the second a.c. current E₁ proportional to a current applied to an electric system and its inversion signal -E_i so that the switch SW2 selects the signals E_i and -E_i when the signal V_g is 1 and 0, respectively. The mean value V_M of the output V_M of the switch SW2 over one cycle of the triangular wave is given as follows: .

[0010] In other words;

[0011] Thus, the mean value of V_M with respect to time is proportional to the product of the first input V_x and the second input E_i.

[0012] The selection output V_M of the switch SW2 is applied to the integrator INT2 inside the pulse generation circuit 20. The integrator INT2 consists of a resistor R2, a capacitance C2 and an amplifier A2, and produces an integration signal V_P of the input V_M from the output terminal of the amplifier A2. Comparators CP4 and CP5 compare the integration signal V_P with the reference voltages V_R and -V_R, respectively, and set and reset the flip-flop EF2 when they are in agreement, respectively.

[0013] Change-over of the signals E_v and -E_v by S_v prevents the saturation of the integration signal V_p by inverting the polarity of the input V_M to the integrator INT2, and lets V_p change repeatedly between the voltages V_p and -V_p at a frequency proportional to the integration value of the product of E and E.

[0014] The integration value of the product of the voltage E_v and the current E₁, that is, the electric power, can be measured by counting how many times the output S_v of the flip-flop FF2 becomes 1.

[0015] It will be now considered that the amplifier A₁ and the comparators CP1 through CP3 have offset. Figure 2 is a circuit diagram showing the case in which these offset voltages are inserted as the equivalent voltage sources. Here, the voltage sources F_fA, V_f1 - V_f3 are those which equivalently express the offset quantities of the amplifier Al and comparators CP1 through CP3, respectively. Accordingly, the amplifier Al and the comparators CP1 - CP3 in Figure 2 can be regarded as having no offset. The triangular wave VΔ in this case has a waveform expressed by the following relation:'

[0016] As can be understood clearly from above, the mean voltage of this triangular wave VΔ becomes (V - V_f1) and is not zero when the offset V_f1 is not equal to the offset V_f2. Hereinafter, this means voltage will be referred to as the "offset of the triangular wave". In this example, this offset results from the difference of offset between the comparators CP1 and CP2.

[0017] Because the offset voltage V_f3 of the comparator CP3 exists, this triangular wave voltage VΔ appears as if it were shifted to a voltage VA'. The waveform of this voltage VA' has a value which is the sum of V_f3 to the positive and negative turn-back voltages of the waveform of VΔ, respectively. The sum is more clearly illustrated in Figure 3. In the same way as the formulas (1) through (3), the degree of pulse width modulation D of the modulation signal V_g is given by the following formula:

[0018] In the formula (6) above, the denominator of the second item is equivalent to the change of the reference voltage V_R because of the existence of the offset voltages of the comparators CP1 and CP2. The influence resulting from the change of V_R can be compensated for by such means as initial setting in the same way as the compensation of the deviation of the integration capacitance C2 and resistor R2 from the set values; hence, the influence is not hereby dealt with.

[0019] If the following relation is given in the formula (6),



then, D is given as follows:

[0020] V_f is the sum of the offset of the triangular wave and the offset of the comparator CP3 but with a different polarity. Accordingly, this is referred to as an "overall offset". If such an overall offset voltage exists, the mean value V_M of V_M in one cycle of the triangular wave, that corresponds to the formula (5), is given by the following formula:

[0021] Accordingly, the frequency f₀ of the pulse S_v becomes f «(V + V_f) x E., and the overall offset voltage V_f occurs as an error. This error depends upon the product of the overall offset V_f and E_i and hence, it is almost impossible to compensate for the error after detection of the pulse S . It is therefore necessary to cancel in advance the overall offset inside the pulse width modulation circuit.

[0022] Thus, it has been necessary conventionally either to select the comparators CP1 through CP3 having offset voltages as small as possible, or to add an offset adjusting circuit. This results eventually in an increase of the cost of producina the circuit.

SUMMARY OF THE INVENTION

[0023] It is therefore an object of the present invention to provide a pulse width modulation circuit which can cancel the mean error, with respect to time, of the degree of pulse width modulation due to the offset voltages of the triangular wave and comparators, by adding a simple circuit of a pulse width modulation circuit.

[0024] It is another object of the present invention to provide an integration circuit forming the product of two analog signals, which circuit makes use of the pulse width modulation circuit described above.

[0025] To accomplish the objects described above, the present invention combines in principle means for cancelling the offset of a triangular wave by inverting either a triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal every predetermined period, with means for eliminating the offset of comparators by inverting the output of the comparator, for replacing the input ter- minals of the comparators if the input signal is not inverted, and if the input signal is inverted, for connecting the input terminals of the comparator as such.

[0026] A pulse width modulation circuit is constituted which comprises means for inverting the input signal and applying it to the same terminal of a comparator and means for inverting the output of the comparator, or a pulse width modulation circuit is constituted which comprises means for inverting a triangular wave signal and connecting the triangular wave signal and the input signal in an opposite manner to the inputs of the comparator and means for inverting the output of the comparator. Thus, a pulse width modulation circuit is provided which can simultaneously eliminate both of the offset of the triangular wave and the offset of the comparator.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] 

Figure 1 is a circuit diagram showing the principal portion of a conventional circuit for an electronic appliance having a pulse width modulation circuit;

Figure 2 is a circuit diagram showing an equivalent circuit of the pulse width modulation circuit of the circuit shown in Figure l^lwhile the offset of the pulse width modulation circuit is taken into consideration;

Figure 3 is a diagram showing the time chart of the signal of the equivalent circuit shown in Figure 3;

Figure 4 is a block diagram showing a first embodiment of an integration circuit for an analog product using the pulse width modulation circuit of the present invention;

Figure 5 is a diagram showing the time chart of the signal of the integration circuit shown in Figure 5; and

Figure 6 is a second embodiment of the integration circuit for the analog product using the pulse width modulation circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] In Figure 4, like reference numerals and symbols are used to identify like constituents as in Figure 1. Added in Figure 4 are an exclusive-OR gate (EOR gate) L2 for inverting the output V₉ of the comparator CP3, a toggle type flip-flop FF3 whose state is inverted by a pulse SA, generated - once a period of the triangular wave, and hence, producing a pulse formed by halving the frequency of SΔ, and an EOR gate Ll for inverting the output V_g' of the EOR gate L2.

[0029] The flip-flop FF3 generates a signal which controls the switch SW3 and the EOR gate L2 in a predetermined period, and +E_v or -E_v is selected by the switch SW3 in accordance with S_T = 1 or S_T = 0.

[0030] The EOR gate L2 is disposed in order to eliminate the mean error, with respect to time, of the degree of pulse width modulation, as will be described elsewhere. It inverts the signal V_g' when the signal SΔ is 1. The EOR gate Ll inverts the output V_g' of the EOR gate L2 when the output pulse S _vof the pulse generator 20 is 1, and the output S_I of this EOR gate Ll is applied in place of the signal V_g of Figure 1 to the switch SW2 (shown in Figure 1) inside the pulse generation circuit 20.

[0031] The duty of the width modulated pulse V_g generated from the comparator CP3 can be determined on the basis of a triangular wave VΔ' oscillating between two reference voltages V_R' and -V_R' that are obtained by gathering all the offset of the comparators CPl through CP3, as explained in con- junction with the formula (7) and also on the basis of an equivalent input voltage V_X' which is formed by adding the input voltage E_x to the inversion input terminal of the comparator CP3 and the overall offset voltage V_f. Here, the following equation is given:

[0032] In other words, the triangular wave VA' and the equivalent input voltage V ' can be regarded as being compared with each other by an ideal comparator CP3 devoid of the offset. Figure 5 is a timing chart showing the relation between various signals and the triangular wave VA'. The signal S changes from 0 to 1 or from 1 to 0 whenever the signal VΔ' coincides with either of ±V_R'. Since the signal S_T is formed by halving the frequency of the signal SΔ, it changes from 0 to 1 or from 1 to 0 whenever the signal VA' coincides with either one of ±V_R'. Figure 5 shows the case in which the level of the signal S_T changes whenever the signal VΔ' coincides with V_R'. On the other hand, the input voltage V_X becomes E_V and -E_V whenever the signal S_T becomes 0 and 1, respec- tively. Figure 5 shows the case in which V_f>0 for the signal V_X'.

[0033] Among the signals V_g and V_g', the solid line represents the pulses whose width is modulated and which are produced from the comparator CP3 and from the EOR gate L2 with respect to the signal V_x', respectively.

[0034] In other words, the signal V_g becomes 1 during the first period I in which the signal VΔ' exceeds the signal V_X' and the signal VA' then becomes equal to the signal V_X'. On the other hand, the signal V_g' becomes 1 during the second period II in which the signal V_g is 1 and the signal S_T is 0, or during the third period III in which the signal V_g is 0 and the signal S_T is 1. As can be seen from the diagram, the signals V_g and V_g' become pulses having the waveforms represented by broken lines when V_f = 0.

[0035] When V_f>0, therefore, the pulse width of the signal V_g' becomes wide at the portion where S_T = "1" (period III) and becomes narrow at the portion where S_T = 0 (period II). When one period of S_T or the two periods of the triangular wave are considered, therefore, the influence of the overall voltage upon the degree of pulse width modulation can be seen offset.

[0036] The above is expressed by the formula. The degree of pulse width modulation D₁ of the pulse V_g' with respect to the period in which V_g' = "1" when S_T = 1 can be given as follows, because V_X = -E_V :

[0037] The degree of pulse width modulation D₂ of the pulse V ' with respect to V ' = 1 when S_T = 0 can be given as follows, because V_X = +E :

[0038] Accordingly, the mean degree of pulse width modulation D in one cycle of S_T or the two cycles of the triangular wave is given as follows:

[0039] Thus, the influence of all the offset voltages contained in the triangular wave VΔ and in the com- - parator CP3 upon the mean degree of pulse width modulation can be cancelled by using the two cycle units of the triangular wave as the measuring unit.

[0040] When S_V = 0, the output S_I of the EOR gate Ll is equal to the signal V_g'. In this case, the mean value V_M of the output V_M of the switch SW2 (shown in Figure 1) inside the pulse generation circuit 20 over the two cycles of the triangular wave becomes equal to the formula (5-1). When S_V = 1, the signal S_L is equal to -V_g'. Hence, the mean value V_M over the two cycles becomes equal to the formula (5-2).

[0041] As has been described already with reference to Figure 1, the output S_V of the flip-flop FF2 is inverted whenever the signal V_P obtained by integrating this V_M becomes equal to either one of ±V_R in the same way as in the case shown in Figure 1. Accordingly, the frequency of the pulse S_V is proportional to the integrated value of the product of the signals E_V and E_i. Thus, a pulse having a frequency proportional to the power can be obtained on the basis of the signal V_M.

[0042] In Figure 4, the inversion signal S_T is produced by halving the frequency of the output SΔ of the triangular wave generation circuit. This is the most simple and reliable method. A method which increases the frequency division ratio by some multiples and a method which divides the frequency on the non-multiple basis can be used, in principle, but these methods are not much advantageous because the time required for each cancelling becomes long. If cancelling is effected in a period shorter than the period of the triangular wave, a problem will occur that the cancelling effect drops if the difference of inclinations of the triangualr wave exists. However, this method may be employed depending upon the intended application.

[0043] Figure 6 shows the second embodiment of the present invention, in which like reference numerals are used to identify like constituents as in Figure 4. This embodiment includes further acircuit 30 for generating a triangular wave signal -V which has the opposite polarity to the triangular wave signal VΔ by use of resistors R3 and R4 having the same value and an operational amplifier A3, and switches SW4 and SW5 for changing over +E_v and ±V by the output S_T of the flip-flop FF3 and connecting them to the comparator CP3. The rest are the same as those of the circuit shown in Figure 4.

[0044] When S_T = 0, for example, the switches SW4 and SW5 connect +E_v to the inversion input terminal of the comparator CP3 and -V to its non-inversion input terminal V_cp+, as shown in Figure 6. When S_T = 1, they connect -V to the inversion input terminal V_cp- and E_v to the non-inversion input terminal V_cp+. In the circuit 30 for producing -V, the resistors R3 and R4 must be equal substantially accurately. The offset voltage of the operational amplifier A3 must be extremely small.

[0045] The reason why the offset of the triangular wave or that of the comparator CP3 can be cancelled in this circuit is the same as in the first embodiment. Assume the offset voltage of the comparator CP3 as V_f3 and the offset voltage of the triangular was signal VΔ as V_fΔ in the same way as-in Figure - 2. Then, in the cycle of S_T = 1 as viewed from the output V_g' of the EOR gate L2, +E_v is applied to the non-inversion input terminal of the CP3 and VΔ (with the proviso that the offset voltage V_f is added) is applied to its inversion input terminal. In consideration of the offset voltage, V_g' = 0 is produced when ^E_v - VΔ - V_fΔ - V_f3 is positive and V_g' = 1 is produced when the latter is negative. Accordingly, the degree of pulse width modulation D₁ of V_g' with respect to the time in which V_g' = 1 is given as follows:

[0046] In the cycle of S_T = 0, -VA (with the proviso that the offset voltage -V_fΔ is added) is applied to the non-inversion terminal of the comparator CP3 and +E_v, to the inversion input terminal. Hence, the output of V_g' becomes 0 when E_v + VΔ + V_fΔ + V_f3 is positive and 1 when it is negative. Accordingly, the degree of pulse width modulation D₂ with respect to time in which V ' = 1 is given as follows:

[0047] Accordingly, the mean degree of pulse width modulation D when S_T = 0 and when S_T = 1 is given as follows:

[0048] Thus, the error due to the offset voltages can be eliminated.

[0049] As described above, the present invention can realize a voltage-frequency convertor which pro- vides a mean degree of pulse width modulation with respect to time, which is devoid of the influence of the triangular wave or comparator, with a high level of accuracy.

Claims

1. A pulse width modulation circuit comprising:

signal generation means (10) for generating a triangular wave signal having a predetermined frequency;

clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal;

comparison means (CP3) for comparing two input signals to generate binary signal and receiving said triangular wave signal at one of its input terminals;

switch means (SW3) for changing over an analog signal to be used for pulse width modulation in response to said clock signal and its inversion signal and applying said inversion signal to the second input terminal of said comparison means (CP3); and

inversion means (L2) for selectively responding to the first value of said clock signal and inverting the output of said comparison means (CP3).

2. A pulse width modulation circuit comprising:

means (10, 30) for generating a triangular wave'signal having a predetermined frequency and its inversion signal;

clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal;

comparison means (CP3) for comparing two input signals and producing a binary signal;

switch means (SW4, SW5) for applying said triangular wave signal and an analog signal to be used for pulse width modulation to the first and second input terminals of said comparison means (CP3), respectively, in response to the first value of said clock signal, and applying said analog signal and said inverted triangular wave signal to the first and second input terminals, respectively, in response to the second value of said clock signal; and

inversion means; (L2) for inverting the output of said comparison means selectively in response to the first value of said clock signal.

3. The pulse width modulation circuit as defined in claim 1 or 2, wherein said clock signal generation means (FF3) include means for dividing the frequency of said triangular wave signal by an integer.

4. The pulse width modulation circuit as defined'in any of claims 1 to 3, wherein said inversion means is an exclusive-OR circuit (L2) to which the output of said comparison means (CP3) and said clock signal are applied.

5. An analog product forming integration circuit comprising:

a pulse width modulation circuit as defined in any of claims 1 to 4; and

operation means (20) including selection means (SW2) for selecting the second analog signal and the inversion signal of said second analog signal in response to the output of said inversion means (L2), and means for integrating (INT2) the signal thus selected.

6. The integration circuit as defined in claim 5, wherein said operation means (20) further include means for generating a pulse whenever the output of said integration means (INT2) reaches a predetermined value.

7. The integration circuit as defined in claim 5 or 6, wherein said operation means further include first means (CP4, CP5) for comparing the output of said integration means with first and second reference values, second means (L1) for inverting the output of said inversion means (L2), disposed between said selection means (SW2) and said inversion means (L2), and third means (FF2) for. controlling said second means (L1) so that said second means alternately effect inversion and non-inversion in synchronism with detection of the coincidence with the first and second reference value by said first means (CP4, CP5).

8. The integration circuit as defined in claim 7, wherein said third means consist of flip-flop means (FF2) set alternately to first and second state whenever the coincidence is detected by said first means (CP4, CP5), and said second means consist of an exclusive-OR gate (L1) to which the output of said inversion means (L2) and the output of said flip-flop means (FF2) are applied.

Drawing