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(11) | EP 0 102 750 A2 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Character font display systems |
| (57) A system for producing a cathode ray tube display comprising programmable character
fonts utilizes a random access memory (18) in addition to a read only memory (16)
for the storage of character fonts. The random access memory (18) is programmable
via a microprocessor (12) for the entry of the desired character fonts therein. The
microprocessor (12) can access either the read only memory (16) or the random access
memory (18), via a display memory (20), for the retrieval of the proper character
font for display on a cathode ray tube (38). |
[0002] A typical raster scan type color cathode ray tube display generally comprises characters displayed in fixed rows and columns on a cathode ray tube. The display is refreshed internally by storing character codes (ASCII), along with color blink information, in a random access memory (RAM). The display is refreshed by sequentially reading these codes, which are used as address information, to access a read only memory (ROM) in which the character fonts are stored. These characters fonts are typically formed by dots within a matrix. Generally, a fixed repertoire of characters is displayable, typically 64 alphanumerics and 64 special symbols. Inasmuch as the repertoire of characters is fixed, the flexibility of the foregoing systems is very limited since characters cannot be changed in or added to the read only memory (ROM) by the operator.
[0003] Because of the foregoing, it has become desirable to develop a system wherein additional characters are available and these characters can be programmed by the operator.
[0004] According to the invention there is provided a system for providing character fonts to a display device, the system comprising first memory means having character fonts contained therein and being characterised by microprocessing means having a program memory associated therewith, second memory means having character fonts contained therein, and means for selecting between the first memory means and the second memory means to cause the appropriate character fonts contained therein to be transferred to the display device.
[0005] A preferred embodiment of the present invention described hereinbelow solves or at least alleviates the aforementioned problems associated with the prior art by providing a random access memory (RAM), in addition to the read only memory (ROM), for the storage of the character fonts. The RAM is accessible and programmable by a microprocessor (central processing unit) for the entry of character fonts therein. In operation, the microprocessor can access either the read only memory (ROM) or the random access memory (RAM), via a display memory, which contains character codes that are used as address information. Depending upon whether the read only memory (ROM) or the random access memory (RAM) is selected, the contents of the proper memory location associated with the character code is transferred to a video generator which, in turn, is connected to a sweep deflection driver and color drivers of a cathode ray tube display. In this manner, the fixed characters from the read only memory and the programmable characters from the random access memory can be displayed on the cathode ray tube.
[0006] The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which:
Figure 1 is an electrical schematic of a system embodying this invention; and
Figure 2 is an electrical schematic of isolation and control circuitry of the system of Figure 1 illustrating its interconnection to a read only memory (ROM) and a random access memory (RAM) used for character generation.
[0007] Figure 1 is an electrical schematic of a system 10 embodying this invention for providing character fonts to a display device in the form of a color cathode ray tube. The system 10, which provides a color graphic cathode ray tube display using writeable character fonts, includes a. microprocessor 12 having a program memory 14 associated therewith, a character generator in the form of a read only memory (ROM) 16, a programmable character generator in the form of a random access memory (RAM) 18, a display memory 20 and a video generator 22.
[0008] The microprocessor 12 (central processing unit) controls the flow of information throughout the system 10 under the direction of the program memory 14. The program memory 14 typically is contained in the microprocessor 12 but may be separate therefrom if the microprocessor 12 does not contain sufficient memory capacity. A data entry keyboard 24 and a communications input 26, for the entry of data from another computer, etc. are provided and can access the microprocessor 12 in order to enter and/or modify data within the program memory 14 or the programmable character generator (RAM) 18. The microprocessor 12 can access the display memory 20 or the read-write isolation and control circuitry, shown generally as numeral 28, through which it has access to the programmable character generator (RAM) 18. The program memory 14 is programmed to select the proper character generator and does so through the display memory 20 which has character codes (ASCII), used as address information, stored therein. The display memory 20, through a line buffer 30, accesses either the programmable character generator (RAM) 18, via the isolation and control circuitry 28, or the character generator (ROM) 16. Depending upon which character generator is selected, the contents of the proper memory location associated with the character code (ASCII) is transferred to a tri-state buffer 32. In the case of the character generator (ROM) 16, this transfer is directly from this generator 16 to the buffer 32, whereas if the programmable character generator (RAM) is utilized, the transfer of the contents of the proper memory location in the character generator 18 to the buffer 32 occurs via the isolation and control circuitry 28. In either case, the output of the buffer 32 is connected to the input to a video shift register 34 whose output is connected to the input to the video generator 22. The output of the video generator 22 is connected to a sweep deflection driver 36 which controls the horizontal and vertical sweeps on a cathode ray tube 38 and is also connected to color drivers 40 which control the red, blue and green colors on the cathode ray tube 38. In this manner, writeable character fonts, formed by dots within a dot matrix, are produced and the resulting characters are displayed in fixed rows and columns, typically 80 columns by 48 rows, on the cathode ray tube 38.
[0009] Referring now to Figure 2, the read-write isolation and control circuitry 28, along with its interconnection with other circuit components, is detailed. Figure 2 illustrates an eight bit address and an eight bit isolation system. Such isolation is required to permit the microprocessor 12 to program the character generator 18 and to then permit the character generator 18 to subsequently provide data to the video generator 22. This isolation and control circuitry 28 comprises
[0010] AND gates A1 to A8, AND gates A9 to A16, AND gates D1 to D8, AND gates Dg to D76, inverters B1 and B4, and amplifiers B2 and B3. The address bus from the microprocessor 12 is connected to one input to each of the AND gates A to A8, while the other input to each of these gates A1 to A8 is connected to the output of the amplifier B2 whose input is connected to the program command bus of the microprocessor 12. The address bus from the display memory 20 is connected to one input to each of the AND gates A9 to A16, while the other input to each of these gates A9 to A16 is connected to the output of the inverter B1 whose input is also connected to the program command bus of the microprocessor 12. The outputs of the gates A1 to A8 and gates A9 to A16 are respectively connected together and the resulting connections form an input to the programmable character generator (RAM) 18. The data bus from the microprocessor 12 is connected to one input to each of the AND gates D1 to D8, while the other input to each of these gates D1 to D8 is connected to the output of the amplifier B3 whose input is connected to the program command bus of the microprocessor 12. The outputs of these gates D to D8 are respectively connected to the inputs to AND gates D 9 to D16 and form another input to the programmable character generator (RAM) 18. The other input to each of these AND gates D9 to D16 is connected to the output of the inverter B4 whose input is connected to the program.command bus of the microprocessor 12. The outputs of the gates D9 to D16 are connected to the input to the tri-state buffer 28.
[0011] In operation, the microprocessor 12 programs the display memory 20 with character codes (ASCII) corresponding to the addresses of the characters required. When the character generator (ROM) 16 receives a particular address from the display memory 20, it outputs the digital equivalent of the character required through the tri-state buffer 32 to the video shift register 34 which, in turn, transmits these data to the video generator 22. The video generator 22, through the sweep deflection driver 36, controls the horizontal and vertical sweep of the cathode ray tube 38, and also controls the color drivers 40 which produce the various color dots which form the desired characters on the cathode ray tube.
[0012] Through the use of the isolation and control circuitry 28, the microprocessor 12 can program the character generator (RAM) 18 which can then act as a special character generator. In this case, the display memory 20, through the line buffer 30, can select either the programmable character generator (RAM) 18 or the character generator (ROM) 16 and transfer the data contained therein to the tri-state buffer 32 and then to the video shift register 34 for transmission of same to the video generator 22.
[0013] Referring again to Figure 2, in order to program the programmable character generator (RAM) 18, a program command signal in the form of a digital (1) is received on the program command bus from the microprocessor 12. This digital (1) is inverted by the inverter B to a digital (0) which is applied to an input to each of the AND gates A9 to A16 disabling all of these gates and preventing the address bus from the display memory 20 from accessing the programmable character generator (RAM) 18. Similarly, this digital (1) signal passes through amplifier B2 and is applied to an input to each of the AND gates A1 to A8 enabling same permitting the address bus from the microprocessor 12 to access the programmable character generator (RAM)18. While this is occurring, this digital (1) is applied to an input to each of the AND gates D1 to D8 enabling same permitting the data bus from the microprocessor 12 to gain access to the programmable character generator (RAM) 18. This same digital (1) signal is inverted by inverter B4 to a digital (0) which is applied to an input to each of,the AND gates Dg through D16 disabling same preventing the data bus from the microprocessor 12 from transmitting data directly to the tri-state buffer 32. In this manner, the microprocessor 12 can address the programmable character generator (RAM) 18.
[0014] As previously stated, during normal operation of the system, the display memory 20 transmits a particular address along its address bus to the character generator 16. The character generator 16, in turn, transmits the digital equivalent of the characters required to the tri-state buffer 32 which, in turn, transmits these data to the video shift register 34. If, however, a character from the programmable character generator (RAM) 18 is required, a program command signal in the form of a digital (0) is transmitted by the microprocessor 12 on the program command bus. This digital (0) signal is transformed into a digital (1) by the inverter B1 causing the AND gates Ag to A16 to be enabled allowing the address bus for the display memory 20 to access the programmable character generator (RAM)18. The foregoing digital (0) also disables AND gates A1 to A8 and D1 to D8 preventing the address bus and the data bus from the microprocessor 12 from accessing the programmable character generator (RAM) 18. While this is occurring, this digital (0) signal is inverted by inverter B4 to a digital (1) resulting in the enabling of AND gates D9 to D16. The display memory 20 can then access the programmable character generator (RAM) 18 directly which, in turn, transmits the digital equivalent of the character required to the tri-state buffer 32 via the AND gates D9 to D16. The tri-state buffer 32 then transmits these data to the video shift register 34. In this manner, the character generator memory capacity has been effectively expanded by the capacity of the programmable character generator (RAM) 18.
1. A system for providing character fonts to a display device, the system (10) comprising
first memory means (16) having character fonts contained therein and being characterised
by microprocessing means (12) having a program memory (14) associated therewith, second
memory means (18) having character fonts contained therein, and means for selecting
between the first memory means and the second memory means to cause the appropriate
character fonts contained therein to be transferred to the display device (38).
2. A system according to claim 1, wherein the operation of the selecting means is
controlled by the program memory (14).
3. A system according to claim 1, including a display memory (20) containing address
information as to the character fonts respectively stored in the first memory means
(16) and the second memory means (18), the display memory (20) being accessible by
the microprocessing means (12) and being operable to select between the first memory
means (16) and the second memory means (18) in response to an address supplied by
the program memory (14).
4. A system according to claim 1, claim 2 or claim 3, wherein the second memory means
(18) is accessible by the microprocessing means (12) to permit the entry of and modification
of the character fonts contained therein.
5. A system according to any one of the preceding claims, including accessing means
(24, 26) for accessing the microprocessing means (12) to permit the entry of and modification
of information within the system.
6. A system according to claim 5, wherein the accessing means comprises a communication
input means (26).
7. A system according to any one of the preceding claims, wherein the first memory
means (16) is a read only memory means.
8. A system according to any one of the preceding claims, wherein the second memory
means (18) is a random access memory means.