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(11) | EP 0 110 130 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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Circuit producing an output free from a leakage between output and input ends Schaltungsanordnung bei welcher das Fliessen eines Verluststromes zwischen Eingang und Ausgang verhindert wird Circuit d'empêchement de fuite de courant entre l'entrée et la sortie |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
Background of the invention
[0001] The present invention relates to a circuit producing an output signal free from a leakage between output and input ends, and more particularly to a coefficient multiplying circuit which multiplies an input signal by a predetermined coefficient defined by the capacitance ratio of capacitors.
[0002] A conventional circuit multiplying an input signal by a predetermined coefficient is known from IEEE-journal of Solid-state-circuits, Volume SC-16, No. 4, August 1981, page 369, figure 3; and consists of an input terminal, a first capacitor connected to the input terminal through a first switch, a second capacitor connected in series with the first capacitor, an operational amplifier having an inverting input port and an output port which are connected to the terminals of the second capacitor, respectively, and a non-inverting input port which is connected to a point of a reference voltage or a power supply voltage, an output terminal connected to the output port of the operational amplifier, a second switch connected in parallel with the second capacitor, and a third switch connected between the point of a reference voltage or a power supply voltage and the electrode on the input terminal side of the first capacitor. The first, second and third switches are usually transistors able to operate at high speed. In particular, MOS field effect transistors are most favorable because of their high resistances when nonconductive.
[0003] Even MOS field effect transistors, however, do not have an infinite resistance when nonconductive. Therefore, the electric charges stored in the first and second capacitors discharge through the switches. In other words, the output obtained deviates from the value to be produced by multiplying the input voltage by the capacitance ratio of the first and second capacitors, so that a correct output is not obtained.
Summary of the invention
[0004] The object of the present invention is to provide a circuit producing an output signal free from the leakage of charges between an output and input ports.
[0005] Another object of the present invention is to provide a coefficient multiplying circuit which does not generate leakage currents through the switches between an output and input ports when the switches are turned off.
[0006] The circuit according to the present invention comprises an operational amplifier, a capacitor coupled between the inverting input terminal and the output terminal of the operational amplifier a first analog switch coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier, and a means coupled prior to the inverting input terminal of the operational amplifier for determining a feed-back value in cooperation with the capacitor, the non-inverting input terminal of the operational amplifier being connected to the ground or a reference potential terminal and is characterized by further comprising a second analog switch inserted between the first analog switch and the output terminal of the operational amplifier and a third analog switch coupled between the non-inverting input terminal of the operational amplifier and the connection point of the first and second analog switches.
[0007] According to the circuit of the present invention, one terminal of the first analog switch is connected to the inverting input port of the operational amplifier. The inverting input port is nearly at the ground or reference potential, when the operational amplifier is balanced, because the non-inverting input port is connected to the ground or the reference potential terminal. The other terminal of the first analog switch is connected, when it is OFF state, to the ground or the reference potential terminal through the third analog switch. The third analog switch is turned on when the first analog switch is turned off, while the second analog switch operates together with the first analog switch. Since the both terminals of the first analog switch are maintained at the same ground or reference potential when the first analog switch is turned off, substantially no potential difference exists across the both terminals and any leakage current does not flow through the first analog switch.
Brief description of the drawings
[0008] The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:
Figure 1 is a diagram of a conventional coefficient multiplying circuit;
Figure 2(a) is a diagram of a coefficient multiplying circuit according to an embodiment of the present invention; and
Figure 2(b) is a diagram of examples of switches employed in the circuit of Figure 2(a).
Detailed description of the invention
[0009] Figure 1 shows a conventional coefficient multiplying circuit in which an input signal of voltage V11 is applied between a reference potential line N15 and an input terminal N11. The input terminal N11 is connected to a first capacitor 12 through a first switch 14. A connection node N12 between the first switch 14 and the first capacitor 12 is connected with a second switch 15 which is connected to the reference potential line N95. The reference potential line N15 is maintained, for example, at ground potential. The first capacitor 12 has a capacitance C12 and is connected to the inverting input port "-" of an operational amplifier 11 at a connection node N13. The non-inverting input port "+" of the operational amplifier 11 is connected to the reference potential line N15, and its output port is connected to an output terminal N14. A second capacitor 13 having a capacitance C13 and a third switch 16 are connected in parallel between the inverting input port "-" and the output port of the operational amplifier 11. The first, second and third switches 14, 15, and 16 are, for example, between source and drain electrodes of MOS field effect transistors which change their conductivities between source and drain electrodes in response to voltages of pulses φ1, φ2 generated by a switch drive circuit 17 and applied to their gate electrodes. The switches 14,15, and 16 are actuated by the switch drive circuit 17 in such a manner that the second and third switches 15, 16 are open when the first switch 14 is closed, and vice versa. Namely, the switches 14 and 15 and the switch 16 are opened and closed alternately.
[0010] On the first phase of the operation, the first switch 14 is opened and the second and third switches 15 and 16 are closed to initialize the circuit. The node N,3 and the output terminal N14 are made at the same potential to discharge electric charges stored in the second capacitor 13. The node N12 is at the same potential as the line N15 by the operation of the amplifier 11 and the node N11 is made connected to the line N15. Therefore, the first capacitor 12 is also discharged. On the second phase, the first switch 14 is closed and the second and third switches 15 and 16 are opened. The input signal is applied to the capacitor 12 and electric charges of a quantity of V11 · C12 are charged into the first capacitor 12. To neutralize the electric charges of the first capacitor 12, electric charges of the same quantity are charged into the second capacitor 13 from the output terminal N14 or from the power supply terminal (not shown) through the operational amplifier 11. The second capacitor 13 has a capacitance C13 and, hence, the voltage between its terminals is given by
i.e., a voltage of
is obtained at the output terminal N14 as an output signal. Thereafter, the first phase and the second phase are repeated alternately, so that the input signal is sampled at a predetermined rate, and voltages obtained by multiplying the sampled voltage by the capacitance ratio C12/C13 of the first and second capacitors 12 and 13 are produced at the output terminal N14 in succession.
[0011] The switches 14, 15 and 16 have finite resistances such as 10 gigaohms even when they are under open conditions. Therefore, electric charges inevitably leak through these finite resistances. The output voltage of the coefficient circuit is determined by the quantity of electric charges stored in the second capacitor 13. Therefore, if the electric charges leak through the third switch 16 during the second phase, the value of the output voltage is deviated from the true value. Assumed that the third switch 16 under the open condition has a resistance of 10 gigaohms and the first capacitor 12 has a capacitance C12 of 1 pF which the input signal has a voltage V11 of 5 volts and pulses φ1, φ2 driving the switches 14, 15 and 16 have a frequency of 1 KHz, an error of about 0.5 volt is generated in the output voltage at the output terminal N14.
[0012] Referring to Figures 2(a) and 2(b), an embodiment of the present invention will be described. In this embodiment, the input portion is similar to the prior art circuit of Figure 1. An input terminal N21 receiving an input signal of a voltage V21 is connected to a connection node N22 through a first switch 24. A second switch 25 is connected between the connection node N22 and a reference potential line N25. Although the reference potential line N25 is preferably maintained at ground potential, it may be kept at another fixed potential such as several volts or power supply voltage. The connection node N22 is further connected to a connection node N23 through a first capacitor 22 which has a capacitance C22 of, for example, 1 pF. The inverting input port "-" of an operational amplifier 21 is connected to the connection node N23, its non-inverting input port "+" is connected to the reference potential line N25, and its output port is connected to an output terminal N24. A second capacitor 23 of a capacitance C23 of, for example, 10 pF is connected between the output port of the operational amplifier 21 and the connection node N23. One terminal of a third switch 26 is connected to the node N23. According to this embodiment, a fourth switch 27 is connected between the other terminal N26 of the third switch 26 and the output terminal N24 and a fifth switch 28 is connected between the node N26 and the reference potential line N25. An output signal of a voltage V24 is obtained at the output terminal N24.
[0013] The first, second, third, fourth, and fifth switches 24, 25, 26, 27, and 28 are MOS field effect transistor or bipolar transistors, as shown in Figure 2(b). The switches 24, 25, 26, 27 and 28 are opened and closed in response to the voltages applied to the control electrodes (gate or base electrodes) thereof. These voltages are applied from a switch drive circuit 29 as the drive pulses φ1 and φ2. The drive pulses φ1 and φ2 have two levels: a high level of, for instance, +2.5 volts and a low level of, for instance, -2.5 volts, and have phases opposite to each other. Their frequency is, for example, 1 KHz. The drive pulse φ1 is supplied to the first switch 24 and the fifth switch 28 to open and close them simultaneously. The drive pulse φ2 is supplied to the second, third, and fourth switches 25, 26, 27 to open and close them simultaneously.
[0014] The operation of the circuit will be described below. On the first phase of the operation, the first and fifth switches 24, 28 are opened, and the second, third, and fourth switches 25, 26, 27 are closed. As a result, the connection nodes N22, N23 and N26 and the output terminal N24 reach the same reference potential, and the electric charges in the first and second capacitors 22, 23 are discharged. The whole circuit is initialized by this first phase for the following second phase.
[0015] Then the first and fifth switches 24 and 28 are closed, and the second, third, and fourth switches 25, 26, and 27 opened, so that electric charges of C22 V21 are charged into the first capacitor 22 by the voltage V21 of the input signal. To neutralize these electric charges, electric charges of the same quantity as C22 · V21 are charged into the second capacitor 23 from the output terminal N24, or from the output port of the operational amplifier. Therefore, a voltage V24 is obtained by dividing the electric charges by the capacitance C23 of the second capacitor 23 across the capacitor 23 and derived from the output terminal N24. This state is referred to as the second phase. The first phase and the second phase are repeated, so that the input signal is sampled at the repetition frequency of the drive pulses φ1 and φ2 and output voltages obtained by multiplying the sampled values by the capacitance ratio C22/ C23 of the first and second capacitors 22, 23 are produced in succession.
[0016] In the second phase, the connection node N23 is connected to the inverting input port "-" of the operational amplifier 21 which is at a potential equal to that of the non-inverting input port "+" when the amplifier 21 is balanced. Therefore, the potential at the node N23 is equal to the potential at the potential at the reference potential line N25. The connection node N26, on the other hand, is connected directly to the reference potential line N25 by the closed fifth switch 28. Therefore, the connection node N26 also reaches a potential at the reference potential line N25. Thus, both terminals of the third switch 26 are a potential equal to that of the reference potential line 25. Therefore, the electric charges stored in the second capacitor 23 do not leak through the third switch 26. Accordingly, the voltage V24 obtained at the output terminal N24 has the correct value of
[0018] The coefficient multiplying circuit shown in Figure 2(a) is preferably formed as a monolithic integrated circuit on a single semiconductor chip. The switches 24, 25, 26, 27, and 28 may be either MOS field effect transistors or bipolar transistors, as shown in Figure 2(b). MOS field effect transistors are preferable because of their large resistances between source and drain electrodes when non-conductive. The operational amplifier 21 may be made up of either MOS field effect transistors or bipolar transistors. Where the switches are composed of MOS field effect transistors, the operational amplifier 21 should also be made up of MOS field effect transistors and, favorably, be made up of complementary MOS field effect transistors. On a monolithic integrated circuit, a capacitor is able to have a capacitance of about 100 pF at the greatest. Therefore, the capacities C22, C23 of the first and second capacitors 22, 23 are selected to be within this range. The ratio C22/C23 of the capacitances can be selected as required.
[0019] In the above embodiment, the present invention is applied to the coefficient multiplying circuit. However, the principal of the present invention may be applied to other circuits. For example, the invention may be applied to a comparator comparing the sampled input signal with the reference voltage, in which the second capacitor 23 in Figure 2(a) is omitted. According to this comparator, on the first phase, the switches 24 and 28 are opened and the switches 25, 26 and 27 are closed to discharge the charges in the capacitor 22 for the initialization of the circuit..On the second phase, the switches 24 and 28 are closed and the switches 25, 26 and 27 are opened to receive the input signal for comparison. The potentials at the connection nodes N23 and N26 has the same value, as explained above. Therefore, any leakage from the output terminal 24 to the connection node N23 does not occur. The obtained output signal does not involve any offset voltage based on the leakage and shows an exact voltage. Similarly, the invention may be applied to a circuit employing the operational amplifier whose inverting input port and output port are required to be operatively connected by an analog switch.
an input terminal (N21) for receiving an input signal;
an output terminal (N24) for taking out an output signal;
a reference potential terminal (N25);
an operational amplifier (21) having an inverting input port, a non-inverting input port and an output port, said output port being coupled to said output terminal and said non-inverting input port being coupled to said reference potential terminal;
a capacitive feed-back path (23) coupled between said inverting input and output ports of said operational amplifier;
a first means (22, 24, 25) coupled between said input terminal and said inverting input port of said operational amplifier for determining a feed-back value in cooperation with said capacitive feed-back path,
a second means (26, 27) coupled between said inverting input and output ports of said operational amplifier for shortcircuiting therebetween to discharge said capacitive feed-back path; and
a third means (29) for controlling said second means,
characterized in that said second means includes
a first switch (26) having one end coupled to said inverting input port of said operational amplifier and another end, a second switch (27) having one end coupled to said output port of said operational amplifier and another end and a third switch (28) having one end coupled to said other ends of said first and second switches and another end coupled to said reference potential terminal, said third means controlling said first and
said second switches to open when said third switch is closed and said first and second switches to be closed when said third switch is opened.
einem Eingangsanschluß (N21) zum Empfangen eines Eingangssignals;
einem Ausgangsanschluß (N24) zum Abziehen eines Ausgangssignals;
einem Bezugspotentialanschluß (N25);
einem Operationsverstärker (21) mit einem invertierenden Eingang, einem nicht invertierenden Eingang und einem Ausgang, wobei der Ausgang mit dem Ausgangsanschluß verbunden ist und der nicht invertierende Eingang mit dem Bezugspotentialanschluß;
einem kapazitiven Rückkopplungsweg (23), welcher zwischen den invertierenden Eingang und den Ausgang des Operationsverstärkers geschaltet ist;
einer ersten Vorrichtung (22, 24 und 25), die zwischen den Eingangsanschluß und den invertierenden Eingang des Operationsverstärkers geschaltet ist, um einen Rückkopplungswert zu bestimmen in Zusammenwirkung mit dem kapazitiven Rückkopplungsweg;
einer zweiten Vorrichtung (26, 27), die zwischen den invertierenden Eingang und den Ausgang des Operationsverstärkers geschaltet ist zum Kurzschließen derselben, um den kapazitiven Rückkopplungsweg zu entladen; und
einer dritten Vorrichtung (29) zum Steuern der zweiten Vorrichtung,
dadurch gekennzeichnet, daß die zweite Vorrichtung aufweist:
einen ersten Schalter (26), dessen eines Ende mit dem invertierenden Eingang des Operationsverstärkers verbunden ist und der ein zweites Ende aufweist, einen zweiten Schalter (27), dessen eines Ende mit dem Ausgangsanschluß des Operationsverstärkers verbunden ist und der ein anderes Ende aufweist und einen dritten Schalter (28), dessen eines Ende mit den anderen Enden des ersten und zweiten Schalters verbunden ist und dessen anderes Ende mit dem Bezugspotentialanschluß verbunden ist, wobei die dritte Vorrichtung den ersten und zweiten Schalter steuert, so daß diese sich öffnen, wenn der dritte Schalter geschlossen ist und sich schließen, wenn der dritte Schalter geöffnet ist.
-une borne d'entrée (N21) pour recevoir un signal d'entrée;
-une borne de sortie (N24) pour prélever un signal de sortie;
-une borne de potentiel de référence (N25);
-un amplificateur opérationnel (21) ayant un point d'entrée d'inversion, un point d'entrée de non inversion et un point de sortie, ce point de sortie étant couplé à la borne de sortie et le point d'entrée de non inversion étant couplé à la borne de potentiel de référence;
-un trajet capacitif de réaction (23) couplé entre les points d'entrée d'inversion et de sortie de l'amplificateur opérationnel;
-un premier moyen (22, 24, 25) couplé entre la borne d'entrée et le point d'entrée d'inversion de l'amplificateur opérationnel pour déterminer une valeur de réaction en coopération avec le trajet capacitif de réaction;
-un second moyen (26, 27) couplé entre les points d'entrée d'inversion et de sortie de l'amplificateur opérationnel pour réaliser un court-circuit entre eux afin de décharger le trajet capacitif de réaction, et
-un troisième moyen (29) pour commander le second moyen, caractérisé en ce que le second moyen comprend:
-un premier commutateur (26) ayant une extrémité couplée au point d'entrée d'inversion de l'amplificateur opérationnel et une autre extré-
mité, un second commutateur (27) ayant une extrémité couplée au point de sortie de l'amplificateur opérationnel et une autre sortie, et un troisième commutateur (28) ayant une extrémité couplée aux autres extrémités des premier et second commutateurs et une autre extrémité couplée à la borne de potentiel de référence, ce troisième moyen commandant les premier et second commutateurs pour qu'ils s'ouvrent lorsque le troisième commutateur est fermé et pour que les premier et second commutateurs se ferment quand le troisième commutateur est ouvert.