CMOS INTEGRATED CIRCUIT WITH GUARD BANDS FOR LATCH-UP PROTECTION - Patent 0119260

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EP 0 119 260 A1

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(43)	Date of publication:
	26.09.1984 Bulletin 1984/39

(21)	Application number: 83903252.0

(22)	Date of filing: 19.09.1983

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International Patent Classification (IPC):

H01L 29/ 78^{( . )}
H01L 27/ 092^{( . )}

H01L 27/ 08^{( . )}
H01L 29/ 06^{( . )}

(86)	International application number:
	PCT/US1983/001420

(87)	International publication number:
	WO 1984/001241 (29.03.1984 Gazette 1984/09)

(84)	Designated Contracting States:
	CH DE FR GB LI NL SE

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Priority:

20.09.1982 US 19820420115

(71)	Applicant: SEMI PROCESSES INC.
	Santa Clara CA 95132 (US)

(72)	Inventors:
	DENHAM, Paul Cupertino, CA 95014 (US) ALLEN, Patrick, Charles Sunnyvale, CA 94087 (US)

(74)	Representative: Reinländer & Bernhardt Patentanwälte
	Orthstrasse 12 D-8000 München 60 D-8000 München 60 (DE)

(54)	CMOS INTEGRATED CIRCUIT WITH GUARD BANDS FOR LATCH-UP PROTECTION