Variable dwell I.C. engine ignition system

Abstract

 @ A dwell control for an ignition system of the general type including a closed loop control which operates to vary the instant after each spark at which energy storage is commenced for the next spark. At low speeds the closed loop control is overridden and the circuit output (Q44) is operated at constant duty ratio. Switch over between the two modes of operation is effected under the control of a bistable circuit (Q₁₈, Q₁₉) which is set to one state in which a variable timer (C₁, Q₂, Q₃, 04) incorporated in the closed loop control determines the instant of energy storage commencement, whenever the time duration for which the energy stored exceeds a threshold in less than a predetermined duration. The bistable is set to its other state, to provide fixed duty cycle operation, whenever the timer period exceeds a limiting value, or when a pulse arrives at the circuit input (Q₁) from a transducer (10) before the expiry of the timer period. This control scheme for the bistable prevents undesirable hunting between the two operating modes.

Description

[0001] This invention relates to a variable dwell i.e. engine ignition system.

[0002] Generally. speaking i.e. engine ignition systems operate by building up a store of energy for a period and then releasing the energy quickly to provide a spark. The conventional contact-breaker/coil ignition system utilises a contact breaker driven by the engine to control the flow of current in a coil primary. Energy release is provided by interrupting the coil current at the required instant of ignition. The phase of the ignition sparks is varied mechanically by the contact breaker in accordance with engine parameters such as speed and air intake mainfold pressure and the mechanical arrangement for speed and vacuum timing control have become very sophisticated over a long period of development.

[0003] More recently there have been many proposals for controlling the timing of the ignition sparks electronically and in such proposals, mechanical vacuum and speed timing control is unnecessary. However, there exists a demand for hybrid systems in which timing control is effected mechanically, but electronic circuits control the actual coil current. Thus, for example, the conventional contact breaker may be replaced by a transducer which is driven by the engine and which incorporates conventional speed and vacuum timing controls. Such a transducer may be, for example, one relying on variable reluctance, on Hall effect, or on other "non-contact" switching arrangements, the transducer providing a pulse train of constant duty ratio with the "trailing edges" of the pulses marking the desired instants of ignition. Clearly, such a transducer simulates the conventional contact breaker, but avoids its mechanical problems such as contact bounce, wear, contact erosion, etc.

[0004] Because of the fixed duty ratio of the transducer pulse train, if the "leading edge" of each pulse is used to turn the coil current on, (as with a conventional contact breaker system) the coil on-time will be a fixed proportion of the cycle time and hence will reduce as speed increases. This involves making a compromise between very inefficient operation at low speed and an inadequate on-time at high speeds. To overcome this problem it has already been proposed, e.g. in UK-A-2113761 to vary the coil duty ratio in accordance with the duration of the interval between the transducer pulses so as to increase the fractional coil on-time as speed increases. A closed-loop correction system was employed to provide a relatively slow correction to maintain the proportion of each cycle for which the coil current was above a set level substantially constant in steady running.

[0005] The previously proposed apparatus was found to be too sensitive to the jitter which was found to occur when a chain drive from the engine to the transducer was used, particularly if the chain was improperly tensioned.

[0006] It is an object of the present invention to provide a variable dwell i.c. engine ignition spark ignition system which can operate satisfactorily when in the presence of substantial timing jitter and which also is relatively insensitive to supply voltage variations.

[0007] In accordance with the invention there is provided a dwell control for an ignition system employing a transducer driven by the engine and producing a pulse train of approximately constant duty ratio and including mechanical means for varying the phase of the pulse train relative to the engine cycle in accordance with engine operating conditions, energy storage means controlled by said transducer for releasing energy to create ignition sparks in synchronism with specific events in said pulse train, means sensitive to different specific events in said pulse train for commencing an energy storage period in each ignition cycle at relatively low engine speeds, timer means operating at relatively high engine speeds and operating under the control of said transducer to commence said energy storage period at an instant in each cycle earlier than said different specific event, the timing period of said timer being determined by closed loop control means so as to regulate the fractional time during which the energy stored by said energy storage means exceeds a threshold value, characterised by mode selection bistable switch means for determining whether or not said timer or said different specific event is to cause commencement of said energy storage period, said bistable switch means being switched to a state in which said timer causes commencement of said energy storage period whenever the time duration for which the energy stored by said energy storage means exceeds a threshold value is less than a predetermined duration and to its other state in which said different specific events cause commencement of the energy storage period either when timing period of the timer exceeds a limiting value or when said different specific event occurs before expiry of the timing period of said timer.

[0008] Where the energy storage means is a coil, the energy storage period is commenced by completing a path for coil current and, in this case, the closed loop control means senses the coil current and determines the timer timing period so that the coil current is above a threshold level for a predetermined proportion of the cycle duration.

[0009] The accompanying drawing is an electrical circuit diagram of one example of a variable dwell i.c. engine ignition system in accordance with the invention.

[0010] The system shown includes a transducer 10 which senses the angular position of a conventional mechanically timed ignition distributor. The transducer may be a Hall-effect device, a variable reluctance device or any other known "no-contact" device which provides, in well known manner, a pulse train of fixed duty ratio and with the trailing edges of the pulses in the pulse train coinciding with the desired instants of sparks. Since transducers of this type are generally known no further description is given herein. The transducer is designed, in the present case, to provide a duty ratio of about 15%.

[0011] The output of the transducer 10 is connected by a pull-up resistor R₁ to a supply rail 11 to which a regulated voltage is applied by a known regulator circuit 12. The transducer output is also connected by a resistor R₂ to the base of an npn transistor Ql, which has its emitter connected to a ground rail 13, so that transistor Q_l is conductive whenever the output of the transducer 10 is high. A resistor R₃ connects the base of transistor Q_l to the ground rail 13. The collector of the transistor Q₁ is connected to the cathodes of two diodes D_l and D₂. The anode of diode D_l is connected to one side of a capacitor C_l, the other side of which is connected to the collector of a pnp transistor Q₂ which has its base connected to a bias voltage source V₁ and its emitter connected by a resistor R₄ to the rail 11. The emitter of the transistor Q₂ is also connected by a resistor R5 to the collector of a pnp transistor Q₃ which has its emitter connected to rail 11 and its base connected to the collector of an npn transistor Q₄, the emitter of which is connected by a resistor R₆ to the ground rail 13 and the base of which is connected to said other side of the capacitor C_l. the anode of the diode D₂ is connected to the rail 11 by a resistor R₇.

[0012] Another diode D₃ has its anode connected to the anode of diode D₂ and its cathode connected by a resistor R₈ to rail 13. The cathode of diode D₃ is connected to the base of an npn transistor Q5, the collector of which is connected by two resistors R₉, R₁₀ in series to the rail 11. The emitter of the transistor Q₅ is connected to the collector of an npn transistor Q₆ the emitter of which is connected to the junction of two resistors R₁₁ and R₁₂ in series between rails 11 and 13. The base of transistor Q₆ is connected by a resistor R₁₃ to said other side of capacitor C_l.

[0013] The anode of the diode D₁ is connected to the emitters of two pnp transistors Q₇ and Q₈. Transistor Q₇ has its base connected to the bias voltage source V₁ and its collector connected by a resistor R₁₄ to rail 13. An npn transistor Qg has its base connected to the collector of transistor Q₇, and its emitter grounded to rail 13. The emitter of transistor Q8 is connected by a constant current source S_l to the rail 11 and its collector is grounded to rail 13. the base of transistor Q₈ is connected by another current source S₂ to rail 11 and to the emitter of a pnp transistor Q₁₀. The collector of transistor Q₁₀ is connected to the collector of transistor Q₈ and to rail 13 and its base is connected to the collectors of an npn transistor Q₁₁ and a pnp transistor Q₁₂. Transistor Q₁₁ has its base connected to another bias voltage source V₂ and its emitter grounded to rail 13 via a resistor R₁₅. The transistor Q₁₂ has its base connected to the bias voltage source V₁ and its emitter connected by a resistor R₁₆ to the rail 11. The base of transistor Q₁₀ is also connected by a resistor R₁₇ and a capacitor C₂ in series to the rail 11. The base of transistor Q₁₀ is also connected to the cathode of a diode D4, the anode of which is connected by a resistor R₁₈ to the rail 11. Anode of diode D₄ is also connected to the anode of a diode D₅, the cathode of which is connected to the transducer output, and to the collector of an npn transistor Q₁₃ which has its emitter grounded to rail 13.

[0014] A pnp transistor Q₁₄ has its emitter connected to that of transistor Q₁₂ and its collector connected to the emitter of transistor Q₁₁. The base of transistor Q₁₄ is connected by a resistor R₁₉ to rail 11 and by a resistor R₂₀ to the collector of transistor Q_l, so that transistor Q₁₄ turns on whenever transistor Q₁ is conductive and so directly connects the emitters of transistors Q₁₁, Q₁₂ together.

[0015] The emitter of transistor Q₁₂ is also connected to the anode of a diode D₆, the cathode of which is connected to the collector a pnp transistor Q₁₆ and to ground via a current sink S₃. The emitter of transistor Q₁₆ is connected to rail 11 and a resistor R₂₁ connects the base of transistor Q₁₆ to that rail. The base of transistor Q₁₆ is also connected to the collector of an npn transistor Q₁₅, the emitter of which is connected to the emitter of transistor Q₁₁ and the base of which is grounded via a resistor R₂₂. A resistor R₂₃ connects the base of transistor Q₁₅ to the anode of a diode D₇, the cathode of which is connected to ground by a resistor R₂₄. The emitter of an ^npn transistor Q₁₇ is connected to the cathode of diode D₇ and the base of transistor Q₁₇ is connected to the junction of two resistors R₂₅, R₂₆ connected in series between the rails 11, and 13.

[0016] An npn transistor Q₁₈ has its emitter connected to rail 13 and its collector connected by two resistors R₂₇, R₂₈ in series to rail 11. The junction of these resistors R₂₇, R₂₈ is connected to the base of a pnp transistor Q₁₉, the emitter of which is connected to rail 11 and the collector of which is connected by three resistors ^R70, ^R₂₉, R₃₀ in series to rail 13, with the junction of resistors R₂₉, R₃₀ connected to the base of transistor Q₁₈. Transistor Q₁₈, Q₁₉ form a bistable switch, turned on as hereafter explained by turning on transistor Q₁₉ and turned off, as also explained by turning off transistor Q₁₈. The collector of the transistor Q_lg is also connected via a resistor R₃₁ to the base of transistor Q₁₃, and by a resistor R₃₂ to the anode of a diode Dg, the cathode of which is connected to the base of the transistor Q₅. The collector of transistor Qg is connected to the junction of resistors R₇₀ and R₂₉ so that when transistor Q₁₉ turns on it sinks any current being passed by transistor Q₁₉ and causes transistor Q₁₈ to turn off.

[0017] An npn transistor Q₂₀ has its collector connected to the junction of resistor R₁₇ and capacitor C₂, its base connected to the bias voltage source V₂ and its emitter connected by a resistor R₃ to the collector of another npn transistor Q₂₁, the emitter of which is grounded to rail 13. A diode Dg has its anode connected to the collector of the transistor Q₁₉ and its cathode connected to the junction of resistors R₇₀ and R₂₉. Transistor Q₂₁ has its base connected to the junction of two resistors R₃₃, R₃₄ connected in series between the collector of a pnp transistor Q₂₂ and rail 11. Transistor Q₂₂ has its emitter connected to the base of a pnp transistor Q₂₃, the emitter of which is connected to rail 11. The base of transistor Q₂₂ is connected to the junction of two resistors R₃₅ and R₃₆ which are in series between the rail 11 and the output of the transducer 10. The junction of these two resistors R₃₅ and R₃₆ is also connected to the collector of a pnp transistor Q₂₄ which has its emitter connected to rail 11 and its base connected to the collector of transistor Q₂₃ which is also connected to ground by a resistor R₃₇.

[0018] An npn transistor Q₂₅ has its emitter grounded to rail 11 and its collector connected to the collector of transistor Q₉. The base of transistor Q₂₅ is connected to rail 13 by a resistor R₃₈ and also to the collector of a pnp transistor Q₂₆. Transistor Q₂₆ has its base connected by a resistor R₃₉ to rail 13, and by two resistors R₄₀, R₄₁ in series to rail 11. The junction of resistors R₄₀, R41 is connected to the anode of a diode D₉, the cathode of which is connected to rail 13 by a current sink S₄. An npn transistor Q₂₇ has its emitter connected to that of transistor Q₂₆ and by a resistor R₄₂ to rail 11 and its collector connected by a resistor R₄₃ to the rail 13. A transistor Q₂₈ has its base connected to the collector of the transistor Q₂₇, its emitter grounded to rail 13 and its collector connected to the base of the transistor Q₂₇. A current sink S₅ also connectes the base of transistor Q₂₇ to ground rail 11.

[0019] A capacitor C₃ is connected at one side to the base of transistor Q₂₇ and at the other side to the anode of a diode D₁₀ the cathode of which is connected to the cathode of diode D₉. These two cathodes are connected to the collector of a pnp transistor Q₂₉ which has its emitter connected to rail 11, and its base connected by a resistor R₄₄ to rail 11, by a resistor R₄₅ to the collector- of transistor Q₁₇ and by a resistor R₄₆ to the anode of a diode D₁₁, the cathode of which is connected to the collector of the transistor Q₂₀. The anode of diode D₁₀ is connected to ground rail 11 by a current sink S₆, to the base of a pnp transistor Q₃₀ and to the collector of a pnp transistor Q₃₁. Transistor Q₃₁ has its emitter connected to rail 11 and its base connected by a resistor R₄₇ to the rail 11.

[0020] The collector of transistor Q₃₀ is connected by a current sink S₇ to rail 13 and its emitter is connected by a resistor R₄₈ to rail 11. The collector of transistor Q₃₀ is also connected to the base of an npn transistor Q₃₂, the emitter of which is grounded to rail 13 and the collector of which is connected by a resistor R₅₀ to the emitter of the transistor Q₃₀. An npn transistor Q₃₃ has its base and emitter connected to the collector of transistor Q₃₂ and its emitter connected by a resistor R₅₁ to ground.

[0021] An npn transistor Q₃₄ has its base connected to the junction of two resistors R₅₂, R₅₃ in series between collector of a pnp transistor Q₃₅ and rail 13. Transistor Q₃₅ has its emitter connected to rail 11 and its base connected to the junction of the resistors Rg and R_IO. The emitter of transistor Q₃₄ is connected to rail 13 and its collector is connected by a resistor R₅₄ to rail 11 and by a resistor R₅₅ to the base of an npn transistor Q₃₆, which has emitter grounded to rail 13. Transistor Q₃₆ has its collecter connected by two resistors R₅₆, R₅₇ in series to rail 11, and by another two resistors R₅₈, R₅₉ in series to the rail 11. The junction of the latter two resistors is connected to the cathode of a diode D₁₂, the anode of which is connected to the base of the transistor Q₂₃. The junction of the two resistors R₅₆, R₅₇ is connected to the base of a pnp transistor Q₃₇ which has its emitter connected by a resistor R₆₀ to rail 11 and its collector connected by a resistor R₆₁ to rail 13. the collector of the transistor Q₃₇ is also connected by a capacitor ^C4 and two resistors R₆₂, R₆₃ in series to the rail 13, the junction of these resistors being connected to the base of an npn transistor Q₃₈, the emitter of which is connected to the base of the transistor Q₃₆ and the collector of which is connected by a resistor R₆₄ to the base of the transistor Q₁₉.

[0022] The emitter of transistor Q₃₇ is connected to the base of a pnp transistor Q₃₉, the emitter of which is connected to rail 11 and the collector of which is connected by a resistor R₆₅ to the collector of an npn transistor Q₄₀, the base of which is connected to the collector and base of the transistor Q₃₃. The collector of transistor Q₃₉ is also connected to the base of a pnp transistor Q₄₁, which has its emitter connected to rail 11 by a current source Sg, and its collector connected by a resistor R₆₆ to the anode of a diode D₁₃, the cathode of which is connected to the collector of a transistor Q₄₀. The emitter of transistor Q₄₁ is connected to the base of a pnp transistor Q₄₂ which has its emitter connected to rail 11 and its collector connected by a current sink S₉ to rail 13. The collector of transistor Q₄₂ is connected to the base of an npn transistor Q₄₃, which has its collector connected to rail 11 and its emitter connected by two resistors R₆₇, R₆₈ in series to rail 13. The junction of resistors R₆₇, R₆₈ is connected to the base of an npn integrated Darlington type output transistor Q₄₄ which has its emitter connected to rail 13 by a current sensing resistor R₆₉ and its collector connected via the ignition coil primary winding 14 to the raw supply 15. The emitter of transistor Q₄₀ is connected to the emitter of transistor Q₄₄ so that transistor Q₄₀ starts to turn off whenever the voltage across resistor R₆₉ rises to that across resistor R₅₁.

[0023] A pnp transistor Q₄₅ has its emitter connected to rail 11, its base connected to the junction of two resistors R₇₂, R₇₁ in series between the emitter of transistor Q₄₃ and rail 11, and its collector connected to the anode of diode D₇.

[0024] In operation transistor Q_l operates to invert the negative-going output pulses from the transducer 10. Thus following each transducer pulse capacitor C_l has the potential of its said one side pulled down to approximately one diode voltage drop above ground, cutting off transistors Q₈ and Q₆ in consequence. At low and medium speeds this has the effect of cutting off transistors Q₃ and Q₄ and capacitor C₁ subsequently discharges linearly via transistor Q₂ acting as a constant current source, until transistor Q₄ turns on, whereupon transistor Q₃ shunts the emitter resistor R₄ of transistor Q₂. This increases the charging rate of capacitor C_l, which charges up by about 1 volt more, after which its "other side" becomes clamped when transistor Q₆ turns on, at which point the timer constituted by the capacitor C₁ and various transistors controlling its charge, has timed out. During the transducer pulse, the potential of the "other side" of capacitor C_l remains clamped whilst that of the "one side" rises until clamped by transistor Q₈ which forms part of a Darlington voltage follower driven by the voltage on capacitor C₂. This voltage therefore controls the delay between the transducer pulse trailing edge and the turning on of the transistor Q₆, this delay increasing in response to increases in the control voltage. At sufficiently low values of the control voltage, the potential of the "other side" of capacitor C_l, is not lowered sufficiently to turn off transistor Q₄; hence the augmented charging rate provided by transistor Q₃ is operative throughout the timer's action. This enables the coil off time to be controlled over a sufficiently wide range of non-zero values.

[0025] Under normal operating conditions of the timer transistor Q₇ is non-conductive. During dwell control operation (to be described hereinafter) however, when the voltage across capacitor C₂ approaches the value at which maximum time delay is produced, transistors Q₇ and Q₉ turn on to provide detection of a "timer outranged" condition.

[0026] When transistor Q₁₃ is conductive (ie in a timer controlled turn on condition), diode D₄ is non-conductive, and the voltage on capacitor. C₂ is controlled by transistors Q₁₁ and Q₁₂. Both of these are held off by transistor Q₁₄ except during the transducer pulses. Transistor Q₁₂ is held off unless transistor Q₁₆ is saturated, i.e. unless transistor Q₁₅ is on. This condition is met during transducer pulses only if the current limit (to be explained hereinafter) is in control; hence transistor Q₁₂ acting as a constant current source is turned on only when the current limit is in control during transducer pulses. Transistor Q_ll, which acts as a constant current sink, is held off when transistor Q₁₅ is conducting, so that it is operative only when the current limit is not in control during transducer pulses.

[0027] The magnitudes of the sink and source currents have a ratio of about 2:1, so that in steady state the current limit is in operation for about two thirds of the transducer pulse duration, i.e. about 10% of the ignition cycle period.

[0028] When the dwell control loop is not in operation the voltage on capacitor C₂ is pre-conditioned by means of transistor Q₁₃ and diode D₄. Diode D₅ prevents pre-conditioning from being applied during transducer pulses, thereby leaving the dwell control voltage undisturbed if the timer is pre-empted by the transducer pulse as a result of rapid acceleration at low engine speeds in dwell control.

[0029] Under engine running conditions, transistors Q₃₀, Q32 are held off and current passing via diode strapped transistor Q₃₃ provides a reference voltage for the current control loop. This loop is gated by transistor Q₃₉ which when off enables the current control loop transistors Q40, Q41, Q42, Q₄₃ and Q₄₄, which all operate in saturation until coil current has risen to a value at which the voltage across resistor R₆₉ causes these stages to desaturate in succession as the current limit comes into control. When transistor Q₄₃ is unsaturated, transistor Q₄₅ is switched on, thereby signalling when the output stage is either in current limit or not conducting at all.

[0030] Capacitor C₅ and resistor R₇₃ control the high frequency gain of the current limit amplifier.

[0031] The command signal for coil switching operates via transistors Q₃₄, Q₃₆, Q₃₇ and Q₃₉, with transistor Q₃₈ providing a brief hold-off pulse lasting about 0.3mS in order to prevent spurious coil turn-on due to spark interference. This hold-off pulse is also used to turn on the mode control switch (Q₁₈, Q₁₉), and it also ensures that transistor Q₃₁ is held on despite spark interference, thereby assuring undisturbed measurement of current limit duration by the associated circuit.

[0032] Transistor Q₃₁ conducts only when the coil is off. Consequently, during each transducer pulse, transistor Q₃₁ is off and transistors Q₂₇ and Q₂₈ are latched on, thereby holding off transistors Q₂₆ and Q₂₅. The "lower" side of capacitor C₃ is therefore held near ground potential as it discharges, initially at about lyA. If the mode control bistable switch is off, transistor Q₂₉ turns off when current limit is reached, causing capacitor C₃ to be discharged additionally at about 100µA. If the period of this augmented discharge falls short of about 1mS, transistors _Q27 and Q28 remain on when transistor Q₃₁ turns on, and capacitor C₃ is recharged rapidly. If the 1mS threshold is exceeded, the base potential of the transistor Q₂₇ is raised above that of transistor Q₂₆ when transistor Q₃₁ turns on, resulting in transistors Q2₇ and Q₂₈ turning off and transistors Q₂₆ and Q₂₅ turning on. In this event capacitor C₃ recharges relatively slowly, enabling a modest excess of current limit duration above the threshold value to produce an output from transistor Q₂₅ outlasting the coil hold-off pulse.

[0033] At a voltage on capacitor C₃ lower than the threshold for switching off transistors Q₂₇, Q₂₈ the augmented discharge current resulting when transistor Q₂₉ is non-conducting is removed by means of diodes D₉, D₁₀. and capacitor C₃ continues to discharge at about 1µA. After about 300mS, transistors Q₃₀ and Q₃₂ turn on and follow the voltage of capacitor C₃, shutting down the current limit control reference and thereby smoothly turning off the coil current without creating a spark. The coil current thus turns off under control and without a spark being created following an engine stall.

[0034] The transistors Q₂₂, Q₂₃ and Q₂₄ form a bistable circuit which delivers an output from transistor Q₂₂ if the negative going transducer pulse applied to its base occurs before it is shorted out by the positive going coil turn-on signal applied via diode D₁₂. If transistor Q₂₂ is turned on by the transducer pulse occurring first, then transistor Q₂₃ is held on, thereby sustaining the output until the end of the transducer pulse. The output is used via transistor Q₂₁ to turn off the mode control bistable switch (Q_l8, Q₁₉) for the duration of any transducer pulse which pre-empts the timer. It also provides for this period, a discharge current via transistor Q₂₀ for capacitor C₂, affording a "forcing" dwell control correction.

[0035] The leading edge of the transducer pulse turns on transistor Q₂₂ directly, but it turns on transistor Q₂₄ via the turn-off delays of overdriven transistors Q₁, Q₃₆ and Q₂₃. Thus, the "race" condition is reliably "won" by transistor Q₂₂ whenever the timer is pre-empted.

[0036] As mentioned above transistors Q₁₈ and Q_lg form a complementary bistable mode control switch which when on enables timed turn-on by means of transistor Q₅. When the mode control switch is off, transistor Q₅ conducts only during transducer pulses, giving direct coil control by the transducer signal.

[0037] The arrangements described ensure that the mode control switch is not turned to "off" (direct control) when spurious sparks could result. Three separate means are provided for turning the mode control switch off and two of these, viz the "timer outranged" detector and the "timer-pre-empted" detector both have outputs which are effectively gated by the transducer pulse. The switch is turned on, if not already on, by the coil hold-off pulse, and is turned off immediately afterwards if a more persistent output is received from the current limit duration detector.

[0038] Mode change due to falling speed with negligible jitter is normally caused by "timer outranged" detection at, for example, about 700 rpm engine speed.

[0039] Jitter-induced hunting between modes is avoided since at speeds high enough for mode change to timer operation, the timed turn-on is early enough to avoid being pre-empted despite substantial jitter (up to 6% with typical value of coil-current growth time).

[0040] For optimum dynamic performance in following engine acceleration, the magnitudes of the sink and source currents passed by transistors Q₁₁ and Q₁₂ are chosen in relation to the capacitor C₂ and in relation to the time constants of the timer circuit to ensure that the dwell time error in any given cycle is approximately matched by the resultant timer delay correction in the next cycle at speeds at which transistors Q₃, Q₄ turn off. At high speeds the reduced coil off time can result in residual coil energy at coil turn on, causing random variations in the coil current growth time. Under these circumstances a reduced correction per cycle provides desirable smoothing of the response when transistors Q₄ and Q₃ remain on.

[0041] If necessary, a voltage limiting protective zener diode feedback circuit of known kind may be associated with transistor Q₄4.

Claims

1. A dwell control for an ignition system employing a transducer (10) driven by the engine and producing a pulse train of approximately constant duty ratio and including mechanical means for varying the phase of the pulse train relative to the engine cycle in accordance with engine operating conditions, energy storage means (14) controlled by said transducer for releasing energy to create ignition sparks in synchronism with specific events in said pulse train, means (Q22) sensitive to different specific events in said pulse train for commencing an energy storage period in each ignition cycle at relatively low engine speeds, timer means (C_l, Q₂, Q₃ and Q₄) operating at relatively high engine speeds and operating under the control of said transducer to commence said energy storage period at an instant in each cycle earlier than said different specific event, the timing period of said timer being determined by closed loop control means so as to regulate the fractional time during which the energy stored by said energy storage means exceeds a threshold value, characterised by mode selection bistable switch means (Q18, Q19) for determining whether or not said timer or said different specific event is to cause commencement of said energy storage period, said bistable switch means being switched to a state in which said timer causes commencement of said energy storage period whenever the time duration for which the' energy stored by said energy storage means exceeds a threshold value is less than a predetermined duration and to its other state in which said different specific events cause commencement of the energy storage period either when the timing period of the timer exceeds a limiting value or when said different specific event occurs before expiry of the timing period of said timer.

2. A dwell control as claimed in claim 1 in which the energy storage means is an ignition coil (14), current in the coil being sensed by the closed loop control means.

3. A dwell control as claimed in claim 2 comprising a semiconductor switch device (Q₄₄) and a current sensing element (R69) in series with the coil (14), a drive amplifier (Q37, Q39, Q₄₁, Q₄₂, Q₄₃) for providing drive current to said switch device (Q₄₄), current limit semiconductor means (Q₄₀) connected to said current sensing element (R₆₉) and to the drive amplifier and operating to reduce the current supplied to the switch device (Q₄₄) when the coil current exceeds a threshold level and means (Q₄₅) connected to the drive amplifier and providing a feedback signal to the closed loop control means when the current limit semiconductor means (Q₄₀) is in operation.

4. A dwell control as claimed in any preceding claim in which a capacitor (C₃) is employed in a timer circuit (Q₂₇, Q₂₈) for detection of when the time duration for which the energy stored by the energy storage means exceeds a threshold value is greater than said predetermined duration.

5. A dwell control as claimed in claim 4 in which said capacitor (C₃) preserves a charge signalling such detections until after spark interference has subsided, which charge then determines whether the mode selection bistable switch means (Q₁₈, Q₁₉) is switched from said first-mentioned state to said other state.

6. A dwell control as claimed in claim 4 or 5 in which said capacitor (C₃) also operates so as smoothly to turn off the coil current when necessary after the transducer signal has ceased.

7. A dwell control as claimed in claim 6 in which said capacitor (C₃) is connected to said closed loop control means so as to provide a signal thereto representing said threshold value which reduces gradually as said capacitor (C₃) discharges following cessation of the transducer signal.

Drawing