Circuit for applying a voltage to a memory cell mos capacitor of a semiconductor memory device

(19)

(11)

EP 0 144 710 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	21.01.1987 Bulletin 1987/04

(43)	Date of publication A2:
	19.06.1985 Bulletin 1985/25

(21)	Application number: 84113079

(22)	Date of filing: 30.10.1984

(84)	Designated Contracting States:
	DE FR GB IT

(30)

Priority:

09.11.1983 JP 21009983

(71)	Applicant: KABUSHIKI KAISHA TOSHIBA
	()

(72)	Inventors:
	Ogura, Mitsugi c/o Patent Division () Masuoka, Fujio c/o Patent Division ()

(54)	Circuit for applying a voltage to a memory cell mos capacitor of a semiconductor memory device

(57) A voltage applying circuit (b) is adapted to a semiconductor memory device comprising a plurality of memory cells (1) which each include MOS memory capacitors (3) one terminal of each being connected to a common point. The output terminal of said voltage applying circuit is connected to the common point of the MOS capacitor (3), and a low voltage for normal operation of the MOS capacitor (3) and a screening voltage for distinguishing a memory device, which is higher than that voltage, are selectively applied to the common connection point.

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