The present invention relates, generally, to computer data graphics systems and, more particularly, to a method and apparatus for generating patterned vector attribute data in conjunction with the creation of a vector in the refresh memory for the graphic system visual display device.
In the typical graphics display system, a cathode ray tube monitor, or similar visual display device, provides the user with a visual image that is generated from data stored in a refresh memory. Typically, the refresh memory contains data which defines the attributes of each pixel of the cathode ray display. Thus, there is a one-to-one correspondence between the data in the refresh memory and the visual information displayed by the cathode ray tube display. In a computer graphics display system, the user generates a visual image on the cathode ray tube by writing attribute data into the refresh memory. At the beginning of a new picture, the refresh memory is typically erased and loaded entirely with a background intensity level. When a new picture is created, a foreground intensity replaces the background intensity, along the image being created.
In the past, the structure for implementing such an operation involved the use of a first register loaded with the background level, and a second register loaded with the foreground level. These registers would then supply these levels to a two-to-one multiplexer. The output of the two-to-one multiplexer would be supplied to the refresh memory data input line. In the two-to-one multiplexer, the outputs thereof would be selected between the foreground and the background by an appropriate control signal. A vector generator generated the addressing to the refresh memory for the point in the refresh memory at which the image was being created. In a modification of this structure disclosed in WO-A-82/ 01614, the refresh memory was split up into an attribute memory, and an information memory. Such an arrangement required that there be participation by a controller, such as the control processing unit or system microprocessor in the designation of the vector attributes on a pixel by pixel basis and, as such, represents an inefficient use of processing time.
These problems of prior art vector attribute generating systems are overcome by the present invention, as claimed in claims 1 and 12, for use in a graphics display system, wherein a refresh memory supplies image data to a visual display device for display, and wherein the contents of the refresh memory are written therein according to addresses supplied by a vector address generator and to attributes supplied by the present invention in accordance with an attribute format instruction. The present invention includes a memory means for storing data corresponding to a plurality of different attributes at selected addresses. The plurality of attributes can include different levels of intensity, color and the like. Also included are means for addressing the attribute storage means in response to the attribute format instruction and in conjunction with the addresses supplied from the vector address generator. With such a structure, the addressing means execute the attribute format instructions to generate a set of addresses which cause the memory means to provide the appropriate attribute data to the refresh memory in concert with the addressing to the refresh supplied thereto by the vector address generator means. This greatly reduces the amount of time that the microprocessor must spend in the generation of the screen image.
In a preferred embodiment of the present invention, the addressing means includes scaler counter means, address counter means and length counter means. The attribute format instructions include a scaler parameter, a length parameter, and a starting address. The scaler counter means receives a control signal from the vector generator which is generated in conjunction with the addressing of the refresh memory. An increment count pulse is output after the number of pulses specified by the scaler parameter have been received from the vector address generator control signal. In response to the count pulse from the scaler counter means, the address counter increments the starting address by one count. The length counter means is also responsive to the count pulse, counting the number of count pulses provided by the scaler counter means and, thereafter, outputting a load pulse to the address counter means after a number of counts, specified by the length parameter, have been received from the scaler counter means. When the address counter means receives the load signal from the length counter means, it reloads the original starting address and begins incrementing that starting address anew.
It is therefore an object of the present invention to provide a method and apparatus for generating vector information for storage in a refresh memory.
It is another object of the present invention to provide a method and apparatus for generating vector attributes for storage in a refresh memory which minimizes participation by the central processing unit therein.
It is a further object of the present invention to provide a method and apparatus for generating vector attributes for storage in a refresh memory wherein a microprocessor provides attribute instructions to an address generating means, and a vector address generator supplies control signals to the address generating means, and further wherein the address generating means, in response to the attribute data, address a attribute storage means to cause the attribute storage means to provide selected attribute data to the refresh memory in concert with the addressing supplied by the vector means to the refresh memory.
These objectives, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description and accompanying drawings.
Referring to Fig. 1, it can be seen that a display device 10, such as a cathode ray tube, receives display data from a refresh memory 12. Display device 10 supplies appropriate addressing signals on display control line 14 to cause the contents of refresh memory 12 to be read out over display data line 16 on a periodic basis.
During the vertical retrace cycle, or a similar cycle which has been designated for display modification, the contents of refresh memory 12 are modified. This modification is typically conducted on a pixel-by-pixel basis. The location of each pixel to be modified is provided by addresses on line 18. These addresses are provided by vector address generator 20. Vector address generator 20 also provides a write enable signal to the refresh memory 12.
The actual data which describes the attribute for the particular pixel being modified is supplied to refresh memory 12 on line 22. The attribute data, in turn, is supplied on line 22 from attribute random access memory (RAM) 24.
Attribute RAM 24 is addressed by addressing circuitry 26. The contents of attribute RAM 24 are supplied by central processing unit 28 via data line 30 and control line 32. Central processing unit (CPU) 28 also supplies attribute format instructions to addressing circuitry 26 on data line 30, along with control signals on lines 34.
As can be seen from Fig. 1, CPU 28 also communicates with vector address generator 20. Finally, vector address generator 20 supplies control signals to addressing circuitry 26 via line 37.
With respect to vector address generator 20, the function of this device is to provide addressing on a pixel-by-pixel basis of the location of the image in the refresh memory, in response to signals received from the central processing unit 28, or some interface unit (not shown). In turn, the signals from the interface unit or the central processing unit 28, are derived from input signals from the user. These signals take the form of location, direction and length information. Vector address generator 20 converts these signals into specific pixel addresses. When these pixel addresses are supplied to refresh memory 12, along with attribute information on line 22, an image is created within refresh memory 12. Vector address generation is well known in the graphics display area. Methods and structures for implementing such a function are described in numerous texts.
Addressing circuitry 26 includes a presettable address counter 36, which is supplied with a starting address by address register 38. The presettable address counter 36 increments the starting address according to a clock supplied on line 40 from presettable scaler counter 42. Scaler counter 42, in turn, is supplied with the control signal on line 37 from vector address generator 20. Scaler counter 42 counts the number of pulses present on line 37 and outputs a clock pulse on line 40 after a predetermined number of pulses have appeared on line 37. This predetermined number is specified by the contents of scaler register 44.
Also responsive to the clock signal on line 40 from scaler counter 42 is presettable length counter 46. Presettable length counter 46 receives length data from length register 48 and issues a load pulse to address counter 36 after a predetermined number of clock pulses, as specified by the length data, have been detected on line 40.
As can be seen from Fig. 1, length register 48, starting address register 38, and scaler register 44 receive data and control signals from central processing unit 28 on lines 30 and 34, respectively. This data can be viewed as an instruction from central processing unit 28, which instruction is executed by addressing circuitry 26 without the need for further participation by central processing unit 28 during the execution of the instruction.
Attribute RAM 24 can be viewed as a look-up table, the contents of which can be modified by central processing unit 28 via lines 30 and 32. Attribute RAM 24 preferably contains selected addressesforall of the vector attribute information required for the images sought to be generated. This attribute information would include data such as background intensity, color, and the like, data on the various degrees of intensity which are to be used in the display, data on the various colors which are to be used in the display, and other similar information. As mentioned above, this information is stored at selected addresses so that the instructions supplied by the central processing unit 28 to the addressing circuitry 26, will cause the addressing circuitry 26 to address the attribute RAM 24 to select the appropriate attributes required for the vector being written into refresh memory 12 and for the image being generated.
For a given attribute format instruction from central processing unit 28, the resulting attribute data supplied to refresh memory 12 from attribute RAM 24 can be viewed as an attribute format which is being written into refresh memory 12 at the locations specified by the addressing from vector address generator 20.
The structure of the present invention as illustrated in Fig. 1 provides a high degree of flexibility in the generation of different attribute formats. The scaling data supplied to the scaler counter 42 determines for how many pixels the attribute currently being addressed in the attribute RAM 24 will continue to be supplied to refresh memory 12. Thus, if the scaling data represents a large number, the attribute being currently addressed will be supplied for a large number of pixels. Conversely, if the scaling data represents a small number, then the attribute data will change frequently.
The starting addresses supplied to address counter 36 from starting address register 38 specify at what point in the range of possible attributes the attribute actually being generated will be located. Similarly, where an attribute is being varied between a background level and some other level, the starting address will then be typically specified so that the background level is stored in the attribute RAM 24 at a location adjacent to the location of the other attribute level.
The length data determines the number of address counter iterations which will be permitted to occur before the address counter is reset to the starting address. Thus, length counter 46 provides a cyclical control or a segment control of the attribute format being generated.
As can be seen from Fig. 1, individual load lines are supplied to length register 48, starting address register 38 and scaler register 44. This permits the central processing unit 24 to modify the contents of a particular register without affecting the contents of the other registers. Thus, the central processing unit 28 can change the starting address in starting address 38 while the address circuitry 26 is processing data from the previous instruction. Thus, when length counter causes address counter 36 to be loaded with the starting address from starting address register 38, a new starting address can be supplied to address counter 36. The nature of the attribute, therefore, can be changed by modifying the starting address for the attribute format being generated.
The generation of these attribute formats will be more readily understood upon consideration of the examples provided in Figs. 2 and 3.
Fig. 2 illustrates the generation of a dashed-line attribute format in which the image varies between five pixels of background level and five pixels of intensity M, for example. The background level intensity attribute is located at address N in attribute RAM 24, while the intensity level M is located at address N+1 in attribute RAM 24, for example. For such a format, the central processing unit 28 supplies a starting address of N, a scaler count of 5, and a length count of 2.
The first line of Fig. 2 illustrates the signal on vector generator control signal line 37, while the second line of the figure illustrates the addresses being supplied to refresh memory 12. Line 3 illustrates the output of scaler counter 42, while line 4 illustrates the output of address counter 36. Line 5 illustrates the output of length counter 46. Finally, line 6 illustrates the attribute which is output from attribute RAM 24.
As can be seen from Fig. 2, for the first five pulses on vector generator control signal line 37, the address being supplied to parameter RAM 24 is N. This results in a attribute RAM 24 output of intensity level M. This intensity level is then stored at refresh memory locations A through A+4. At the fifth pulse on vector generator control line 37, scaler counter 42 provides a clock pulse. In response thereto, the address from address counter 36 is incremented by one. In turn, parameter RAM 24 provides the background intensity attribute.
After the second set of five pulses has occurred, scaler counter 42 provides a second clock pulse. In response thereto, length counter 46 provides an output pulse which causes address counter 36 to reload the starting address from starting address register 38. Thus, the output of address counter 36 at this point is N. This pattern continues so long as pulses are provided on vector control line 37, or until central processing unit 28 provides the next instruction to the addressing circuitry 26.
Referring to Fig. 3, an attribute format wherein the intensity level is permitted to increase every two pixels for a total of 128 pixels is illustrated. As with Fig. 2, the first line of Fig. 3 depicts the signals on vector generator control line 37. The second line illustrates the scaler counter 42 output. The third and fourth lines illustrate the length counter output and the address counter output, respectively. Finally, the fifth line illustrates the graphical equivalent of the attribute information being supplied from attribute RAM 24. In order to generate the above-described format, the scaler counter 42 is loaded with the number 2, the length counter is loaded with length 64, and the starting address counter is loaded with address M. As can be seen from Fig. 3, scaler counter 42 provides a pulse for every two pulses on the vector generator control line 37. With each pulse from scaler counter 42, address counter increments its output by 1, starting with starting address M. After the scaler counter 42 has output 64 pulses, corresponding to 128 pixels being addressed by vector generator 20, length counter 46 outputs a load pulse to address counter 36, thereby causing the original starting address M to be loaded into address counter 36. As can be seen from the fifth line of Fig. 3, a stair step-like attribute is created by this format.
The functional blocks shown in Fig. 1 can be implemented by commercially available devices. For example, parameter RAM 24 can be a 256 x 4 RAM comprising four 256 x 1 random access memories which are addressed in parallel. Commercially available parts such as industry number 10422, manufactured by Motorola, Inc. of Phoenix, Arizona are suitable for use in such an application. Similarly, the counter functional blocks 46, 36 and 42 can be industry part number 10136, manufactured by Motorola, Inc. of Phoenix, Arizona. Finally, registers 48, 38 and 44 can be commercial part number 74LS374, manufactured by Signetics Corporation of Sunnyvale, CA.
In accordance with the method of the present invention, a storage means which stores a plurality of different attribute data at selected locations provides attribute data to a refresh memory associated with a visual display device, in conjunction with addresses supplied thereto by a vector address generator. Addressing for the storage means is supplied from an address generator. In order to generate vector attributes for storage in a refresh memory, the method of the present invention comprises the steps of storing a plurality of different attributes at selected addresses in the storage means, providing an attribute format instruction to the addressing means, addressing the storage means in accordance with the attribute format instruction, wherein the addressing step includes the steps of starting the addressing at a specified starting address, incrementing the address whenever a predetermined number of pixel addresses has been supplied to the refresh memory by the vector address generator, wherein the predetermined number is supplied in the attribute format instruction, and restarting the addressing from the starting address when a predetermined number of increment counts has been supplied wherein the predetermined number is provided in the attribute format instruction.
The terms and expressions which have been employed here are used as terms of description and not of limitations, and there is no intention, the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.