(57) A high resolution video graphics system for use with a processor and characterized
by improved memory expandability particularly in connection with color display. The
high resolution video graphics system incluldes a video memory which is preferably
comprised of a plurality of video memory planes and video counter means for providing
display timing. There are basically four buses that are used with the system including
a control bus, a read bus, a write bus, and an address bus. A multiplexer means is
provided for receiving either video counter addresses or direct addresses from the
processor. There is associated with the video memory means for converting to serial
output data which the preferred embodiment includes a series of shift registers corresponding
to the number of separate memory planes employed. In the preferred embodiment the
system has three memory planes, each of 16K by 16 capacity. The shift register output
is coupled to a high speed static palette RAM with the shift register outputs being
the addresses thereto. The data outputs of the palette RAM couple to guns on a color
monitor or to the back plane in connection with black and white graphics.
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