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(11) | EP 0 161 885 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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| (54) |
Amplifier circuit Verstärkerschaltung Circuit amplificateur |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
Background of the Invention
[0001] The present invention relates to a multistage amplifier circuit constituted by cascade-connecting at least two field effect transistors (FETs), and more particularly to a simplified feedback type amplifier circuit which can improve frequency characteristics in a low frequency range.
[0002] Initially, a two-stage amplifier circuit as an example of a conventional multistage amplifier circuit constituted with at least two FETs cascade-connected to each other will be described with reference to Fig. 1. This amplifier circuit comprises a first-stage FET 1, the next (second)-stage FET 2 cascade-connected to the FET 1, and an interstage capacitor 3 connected between a drain D₁ of the FET 1 and a gate G₂ of the FET 2. Both drains D₁ and D₂ of the FETs 1 and 2 are connected commonly to a drain bias power supply terminal 6 through load impedances 4 and 5, respectively. Further, sources S₁ and S₂ are grounded and gates G₁ and G₂ are connected to a gate bias terminal 9 through gate bias power feed impedances 7 and 8, respectively. To provide a flat gain over a wide frequency band, a first amplifier stage comprised of the FET 1 is provided between the drain D₁ and the gate G₁ with a series circuit comprising first-stage feedback netwrok 10 and a capacitor 11 for blocking a dc component of a feedback singal (which will be called a dc block capacitor 11 hereinafter). Likewise, the second amplifier stage comprised of the FET 2 is provided between the drain D₂ and the gate G₂ with a series circuit comprising a second stage feedback network 12 and a capacitor 13 for blocking a dc component of a feedback signal (which will be called a dc block capacitor 13 hereinafter). The amplifier circuit further comprises an input terminal 14 which is connected to the gate G₁ of the FET 1, and an output terminal 15 which is connected to the drain D₂ of the FET 2.
[0003] In the amplifier circuit thus configured, when an input signal is supplied to the gate G₁ through the input terminal 14, the input signal is amplified by the FET 1. The amplified output from the drain D₁ of the FET 1 is inputted to the gate G₂ through the interstage capacitor 3 and then is amplified by the FET 2, thus producing an output signal on the output terminal 15 connected to the drain D₂ of the FET 2. In this amplifier circuit, negative feedbacks are implemented to both the FETs 1 and 2 through the first-stage feedback network 10 and the dc block capacitor 11 and through the second-stage feedback network 12 and the dc block capacitor 13, respectively.
[0004] However, since the conventional multistage amplifier circuit configured as shown in Fig. 1 is provided with a feedback circuit per each amplifier stage, it requires dc block capacitors 11 and 13 in the respective feedback loops in addition to the interstage dc block capacitor 3.
[0005] For this reason, in general, when n stages of amplifiers are configured with such a conventional amplifier circuit, (2n - 1) capacitors are required, leading to the drawbacks that circuit configuration becomes complicated and this conventional system is not economical. In addition, it has the drawback in characteristics that frequency characteristics of the amplifier in a low frequency range is limited by the capacitance, except for the interstage capacitor, existing in each feedback loop.
[0006] Further, when the above-mentioned amplifier circuit is configured as an integrated circuit (IC), the total capacitance value of capacitors has a great influence on the IC size to such a degree that it determines the IC size. For this reason, it is strongly required that the capacitance value of capacitors in the IC is as small as possible. To satisfy this requirement, first is to take the measure for reducing the number of capacitors used and second is to take the measure for configuring the IC at a minimum capacitance value required.
Summary of the Invention
[0007] In view of the above, the present invention has been made so as to eliminate such drawbacks and meet the above requirements and has for its object to provide an amplifier circuit which can improve frequency characteristic in a low frequency range with a simplified circuit configuration.
[0009] The impedance circuit means of the present invention may be configured as an impedance circuit of less capacitive nature. The impedance circuit may comprise a resistance element, an inductance element, or a network comprising resistance and inductance elements coupled thereto.
[0010] The gate of the (i - 1)th stage field-effect transistor has the same potential as that of the i-th stage field-effect transistor. The drain of the i-th stage field-effect transistor has the same potential as that of the (i - 1)th stage field-effect transistor.
[0011] Further, gates of the n number of field-effect transistors may be commonly connected to a gate bias terminal through impedance elements, respectively, drains of the n number of field-effect transistors may be commonly connected to a drain bias power supply terminal through load impedance elements, respectively.
Brief description of the drawing
[0012] The features and advantages of an amplifier circuit according to the present invention will become more apparent from the following description taken in conjunction with the accompanying drawing, in which:
Fig. 1 is a circuit diagram illustrating an example of a conventional amplifier circuit; and
Fig. 2 is a circuit diagram illustrating an embodiment of an amplifier circuit according to the present invention.
Detailed description of preferred embodiment
[0013] A preferred embodiment of an amplifier circuit according to the present invention will be described with reference to attached drawing.
[0014] Fig. 2 is a circuit diagram illustrating the embodiment of an amplifier circuit comprising a plurality of FETs successively connected to each other wherein by way of example, there is shown a two-stage amplifier circuit configured so that an input signal is applied to the gate of the first stage amplifier to produce an output signal from the drain of the next stage amplifier.
[0015] In Fig. 2, parts designated by the same reference numerals as those in Fig. 1 show corresponding ones, respectively, and therefore their explanation will be omitted. The embodiment of the present invention is characterized in that there are provided a first impedance circuit means 16 for negative feedback which connects the gate G₁ of the first-stage FET 1 to the gate G₂ of the next-stage FET 2, and a second impedance circuit means 17 for negative feedback which connects the drain D₁ of the first-stage FET 1 to the drain D₂ of the next stage FET 2. These first and second impedance circuit means provide impedance of feedback circuits provided in the first and second amplifier stages comprising FET 1 and the FET 2, respectively. Each impedance circuit means functions to allow a dc component of a feedback signal to pass therethrough. That is, this impedance circuit means is configured as an impedance circuit of less capacitive nature. For example, the impedance circuit comprises a resistance element, an inductance element, or a network comprising resistance and inductance elements coupled to each other.
[0017] An input signal from the input terminal 14 is applied to the gate G₁ of the first-stage FET 1 and is amplified thereby. An output signal from the drain D₁ of the first-stage FET 1 is inputted to the gate G₂ of the next-stage FET 2 and is amplified thereby. Thus, an output signal is produced on the output terminal 15 connected to the drain D₂ of the next-stage FET 2.
[0018] With an improvement in a feedback system in mind, in this embodiment, there is provided the circuit component 16 functioning as impedance for negative feedback which provides a feedback impedance of the first-stage FET 1 between both gates G₁ and G₂ of the FET 1 and FET 2, at which potentials are equal to each other. In this instance, when the amplifier circuit is caused to be operative under the condition where no current flows between the gate bias terminal 9 and each gate of the FETs, either of circuit elements 7 and 8 providing gate bias power feed impedance can be omitted.
[0019] In this instance, by suitably selecting the device parameters of the FET 1 and the FET 2 and the values of the load impedances 4 and 5, a potential at the drain D₁ of the FET 1 can be equal to a potential at the drain D₂ of the FET 2. By further providing a circuit component 17 functioning as impedance for negative feedback between the drains D₁ and D₂ of the FET 1 and the FET 2 and as a feedback circuit of the second-stage FET 2, it is possible to constitute a feedback type amplifier circuit without a dc block capacitor in the feedback loop.
[0020] In the above-mentioned embodiment, it has been described that the present invention is applied to the two-stage amplifier circuit. However, the present invention is not limited to this embodiment. It is needless to say that the present invention is applicable to a multistage amplifier circuit comprising a plurality of FETs cascade-connected to each other.
[0021] Accordingly, when generally realizing n stages of feedback amplifiers by making use of this circuit system, the number of dc block capacitors required therefor is (n - l). Thus, the improved amplifier circuit makes it possible to reduce the number of capacitors to less than one-half as compared to the (2n - l) capacitors required for the conventional amplifier circuit. Further, it is possible to omit each dc block capacitor provided in the feedback loop except for the dc block capacitor of the elementary feedback circuit in the first-amplifier stage. Thus, circuit configuration becomes simple, resulting in low cost and improvement in frequency characteristics in a low frequency range.
[0022] As stated above, the present invention can provide a simplified circuit configuration by improving the feedback system in a multistage type amplifier without using complicated means. Accordingly, this circuit is extremely advantageous in a practical use as follows: It is possible to reduce the required number of dc block capacitors to less than one-half when compared to the prior art circuit and to reduce the area of capacitors which is an important factor for determining the chip area when realizing an integrated circuit. Further, the feedback loop newly employed by the present invention is not provided with a dc block capacitor, thus enabling the improvement in frequency characteristics of the amplifier in a low frequency range. In addition, the amplifier circuit of the invention is quite effective in that the price can be reduced due to realization of simplified configuration.
1. An amplifier circuit including n number of amplifier stages each comprising a field-effect transistor (1)(2), cascade-connected
to each other (where n is an integer equal to or more than two) through interstage capacitors (3), a signal
being input to the first stage and output from the nth stage, characterised in that:-
a) the (i -1)th amplifier stage (where i = 2, 3, 4 ....n) is provided with a negative feedback circuit (16) including impedance circuit means functioning to allow a dc component of a feedback signal to pass therethrough, the impedance circuit means provided in the (i - 1)th amplifier stage being coupled between respective gates (G₁)(G₂) of the (i -1)th-stage and the i-th stage field-effect transistors, and in that
b) the i-th amplifier stage is provided with a negative feedback circuit (17) comprising impedance circuit means having the same function as that of said impedance circuit means of said feedback circuit provided in said (i-1)th amplifier stage, said impedance circuit means provided in said i-th amplifier stage being coupled between respective drains (D₁)(D₂) of the i-th and the (i-1)th amplifier stages.
2. An amplifier circuit as claimed in claim 1 characterised in that the impedance circuit
means (16) (17) are each configured as an impedance circuit of less capacitive nature.
3. An amplifier circuit as claimed in either claim 1 or claim 2, characterised in that
the impedance circuits (16)(17) each include a resistance element, an inductance element,
or a network comprising resistance and inductance elements coupled to each other.
4. An amplifier circuit as claimed in any one of the preceding claims characterised in
that the gate of the (i - 1)th-stage field-effect transistor has the same potential
as that of the second stage field-effect transistor.
5. An amplifier circuit as claimed in any one of the preceding claims characterised in
that the drain of the i-th stage field-effect transistor has the same potential as
that of the (i - 1)th stage field-effect transistor.
6. An amplifier circuit as claimed in any one of the preceding claims characterised in
that the gates of the n number of field-effect transistors are connected in common to a gate bias terminal
(9) through impedance elements (7)(8), respectively.
7. An amplifier circuit as claimed in claim 6, characterised in that the amplifier circuit
is operative under the condition in which when no current flows between each of the
gates (G₁)(G₂) of the n number of field-effect transistors and the gate bias terminal (9), the number of
the impedance elements (7)(8) is reduced to at least one-half.
8. An amplifier circuit as claimed in any one of the preceding claims characterised in
that the drains of the n number of field-effect transistors are connected in common to a drain bias power
supply terminal (6) through load impedance elements (4)(5), respectively.
9. An amplifier circuit as claimed in any one of the preceding claims characterised in
that the first-stage field-effect transistor (G₁) is provided with an input terminal
(14) coupled to the gate thereof, and the final stage field-effect transistor (G₂)
is provided with an output terminal (15) coupled to the drain (D₂) thereof.
10. An amplifier circuit including at least two stages of field-effect transistors (1)(2)
cascade-connected to each other, an input terminal (14) for an input signal provided
in the first stage field-effect transistor, an interstage capacitor (3) coupled between
successively connected field-effect transistors (1)(2), and an output terminal (15)
coupled to the drain (D₂) of the final one of the field-effect transistor stages,
thereby to output an amplifier signal from the output terminal (15), characterised
in that there are first impedance circuit means (16) providing negative feedback which
allows a dc component of a feedback signal to pass therethrough, the first impedance
circuit means (16) being coupled between respective gates (G₁)(G₂) of the first stage
and the second stage field-effect transistors (1)(2), second impedance circuit means
(17) providing negative feedback having the same function as that of the first impedance
circuit means (16), the second impedance circuit means (17) being coupled between
the drains (D₁)(D₂) of the first and the second field-effect transistors (1)(2).
11. An amplifier circuit as claimed in claim 10, characterised in that each of the first
and second impedance circuit means (16)(17) is configured as an impedance circuit
of less capacitive nature.
12. An amplifier circuit as claimed in claim 11, characterised in that an impedance circuit
includes a resistance element, an inductance element, or a network comprising resistance
an inductance coupled to each other.
13. An amplifier circuit as claimed in either claim 10 or claim 11 characterised in that
the gate (G₁) of the first stage field-effect transistor has the same potential as
that of the second stage field-effect transistor.
14. An amplifier circuit as claimed in claim 10, wherein each of the drains (D₁)(D₂) of
the first and the second field effect transistors is connected to the second impedance
circuit means (17) to have the same potential.
15. An amplifier circuit as claimed in claim 10, characterised in that the gates (G₁)(G₂)
of the field-effect transistors (1)(2) which are connected in cascade with one another
are connected in common to a gate bias terminal (9) through impedance elements (7)(8),
respectively.
16. An amplifier circuit as claimed in claim 10, characterised in that the drains (D₁)(D₂)
of the field-effect transistors (1)(2) which are connected in cascade are connected
in common to a drain bias power supply terminal (6) through load impedance elements
(4)(5), respectively.
1. Verstärkerschaltung mit einer Anzahl n von Verstärkerstufen, die jeweils einen Feldeffekttransistor (1)(2) aufweisen, und
miteinander über Zwischenstufenkondensatoren (3) miteinander kaskadenverbunden sind
(wobei n eine ganze Zahl ist gleich oder größer 2), wobei ein Signal in die erste Stufe eingegeben
und von der n-ten Stufe ausgegeben wird, dadurch gekennzeichnet, daß
a) die (i -1)-te Verstärkerstufe (wobei i = 2, 3, 4 ... n ist) mit einer negativen Rückkopplungsschaltung (16) versehen ist, die eine Impedanzschaltungseinrichtung aufweist, die dazu dient eine DC-Komponente eines Rückkopplungssignals durchzulassen, wobei die in der (i - 1)-ten Verstärkerstufe vorgesehene Impedanzschaltungseinrichtung zwischen den zugehörigen Gates (G₁) (G₂) der Feldeffekttransistoren der (i - 1)-ten Stufe und i-ten Stufe verbunden ist, und daß
b) die i-te Verstärkerstufe mit einer negativen Rückkopplungsschaltung (17) versehen ist mit einer Impedanzschaltungseinrichtung, die die gleiche Funktion wie die Impedanzschaltungseinrichtung der in der (i-1)-ten Verstärkerstufe vorgesehenen Rückkopplungsschaltung hat, wobei die in der i-ten Verstärkerstufe vorgesehene Impedanzschaltungseinrichtung zwischen zugehörigen Drains (D₁) (D₂) der i-ten und der (i-1)-ten Verstärkerstufen verbunden ist.
2. Verstärkerschaltung nach Anspruch 1, dadurch gekennzeichnet, daß die Impedanzschaltungseinrichtungen (16) (17) jeweils als eine Impedanzschaltung
mit niedriger Kapazität ausgeführt sind.
3. Verstärkerschaltung nach Anspruch 1 oder Anspruch 2, dadurch gekennzeichnet, daß die Impedanzschaltungen (16) (17) jeweils ein Widerstandselement, ein Induktivitätselement
oder ein Netzwerk aus miteinander verbundenen Widerstands- und Induktivitätselementen
sind.
4. Verstärkerschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß das Gate des Feldeffekttransistors der (i-1)-ten Stufe das gleiche Potential
aufweist, wie das des Feldeffekttransistors der zweiten Stufe.
5. Verstärkerschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß das Drain des Feldeffekttransistor der i-ten Stufe das gleiche Potential aufweist
wie das des Feldeffekttransistors der (i - 1)ten Stufe.
6. Verstärkerschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß die Gates der Anzahl n Feldeffekttransistoren jeweils über Impedanzelemente (7) (8) gemeinsam mit einem
Gatevorspannungsanschluß (9) verbunden sind.
7. Verstärkerschaltung nach Anspruch 6, dadurch gekennzeichnet, daS die Verstärkerschaltung unter der Bedingung betrieben werden kann, bei der die
Anzahl der Impedanzelemente (7)(8) auf mindestens die Hälfte reduziert ist, wenn kein
Strom zwischen jedem der Gates (G₁)(G₂) der Anzahl n Feldeffekttransistoren und dem Gatevorspannungsanschluß (9) fließt.
8. Verstärkerschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß die Drains der Anzahl n Feldeffekttransistoren jeweils über Lastimpedanzelemente (4)(5) gemeinsam mit einem
Drainvorspannung-Spannungsversorgungsanschluß (6) verbunden sind.
9. Verstärkerschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß der Feldeffekttransistor (G₁) der ersten Stufe mit einem Eingangsanschluß (14)
der mit dessen Gate verbunden ist, versehen ist, und daß der Feldeffekttransistor
(G₂) der letzten Stufe mit einem Ausgangsanschluß (15), der mit dessen Drain (D₂)
verbunden ist, versehen ist.
10. Verstärkerschaltung von mindestens zwei Stufen von miteinander kaskadenverbundenen
Feldeffekttransistoren (1)(2), einem Eingangsanschluß (14) für ein Eingangssignal,
der in dem Feldeffekttransistor der ersten Stufe vorgesehen ist, einem Zwischenstufenkondensator
(3), der zwischen aufeinanderfolgend verbundene Feldeffekttransistoren (1)(2) verbunden
ist, und einem Ausgangsanschluß (15), der mit dem Drain (D₂) des Feldeffekttransistors
der letzten Stufe verbunden ist, so daß ein verstärktes Signal von dem Ausgangsanschluß
(15) ausgegeben wird, gekennzeichnet durch eine erste Impedanzschaltungseinrichtung (16) zum Bereitstellen einer negativen Rückkopplung,
die es ermöglicht, daß eine DC-Komponente eines Rückkopplungssignals hindurchgelassen
wird, wobei die erste Impedanzschaltungseinrichtung (16) zwischen zugehörigen Gates
(G₁) (G₂) der Feldeffekttransistoren (1)(2) der ersten Stufe und der zweiten Stufe
verbunden ist, eine zweite Impedanzschaltungseinrichtung (17) zum Bereitstellen einer
negativen Rückkopplung, die die gleiche Funktion wie die erste Impedanzschaltungseinrichtung
(16) hat, wobei die zweite Impedanzschaltungseinrichtung (17) zwischen den Drains
(D₁) (D₂) des ersten und des zweiten Feldeffekttransistors (1)(2) verbunden ist.
11. Verstärkerschaltung nach Anspruch 10, dadurch gekennzeichnet, daß die erste und die zweite Impedanzschaltungseinrichtung (16)(17) als eine Impedanzschaltung
mit niedriger Kapazität ausgebildet ist.
12. Verstärkerschaltung nach Anspruch 11, dadurch gekennzeichnet, daß eine Impedanzschaltung ein Widerstandselement, ein Induktivitätselement oder
ein Netzwerk mit miteinander verbundenem Widerstand und Induktivität aufweist.
13. Verstärkerschaltung nach Anspruch 10 oder Anspruch 11, dadurch gekennzeichnet, daß das Gate (G₁) des Feldeffekttransistors der ersten Stufe das gleiche Potential
aufweist, wie das des Feldeffekttransistors der zweiten Stufe.
14. Verstärkerschaltung nach Anspruch 10, wobei das Drain (D₁)(D₂) jeweils des ersten
und des zweiten Feldeffekttransistors mit der zweiten Impedanzschaltungseinrichtung
(17) verbunden ist, so daß das gleiche Potential vorhanden ist.
15. Verstärkerschaltung nach Anspruch 10, dadurch gekennzeichnet, daß die Gates (G₁)(G₂) der Feldeffekttransistoren (1)(2), die miteinander in Kaskaden
verbunden sind, jeweils über Impedanzelemente (7)(8) gemeinsam mit einem Gatevorsprungsanschluß
(9) verbunden sind.
16. Verstärkerschaltung nach Anspruch 10, dadurch gekennzeichnet, daß die Drains (D₁) (D₂) der Feldeffekttransistoren (1)(2), die miteinander in Kaskade
verbunden sind, jeweils über Lastimpedanzelemente (4)(5) gemeinsam mit einem Drainvorspannungs-Spannungsversorgungsanschluß
(6) verbunden sind.
1. Circuit amplificateur comportant n étages amplificateurs, chacun comprenant un transistor à effet de champ (1)(2), connectés
en cascade l'un à l'autre (où n est un nombre entier égal à ou supérieur à deux) par l'intermédiaire de condensateurs
interétages (3), un signal étant entré vers le premier étage et sorti d'un nième étage, caractérisé en ce que :
a) le (i - 1)ième étage amplificateur (où i = 2, 3, 4 ... n) est prévu avec un circuit de contre-réaction négative (16) comportant un moyen de circuit d'impédance fonctionnant pour permettre à une composante continue d'un signal de contre-réaction de passer à travers, le moyen du circuit d'impédance prévu dans le (i - 1)ième étage amplificateur étant couplé entre les grilles respectives (G₁)(G₂) des transistors à effet de champ du (i - 1)ième étage et du iième étage, et en ce que
b) le iième étage amplificateur est prévu avec un circuit de contre-réaction négative (17) comprenant un moyen de circuit d'impédance ayant la même fonction que celui du moyen de circuit d'impédance du circuit de contreréaction prévu dans le (i - 1)ième étage amplificateur, le moyen du circuit d'impédance prévu dans le iième étage amplificateur étant couplé entre les drains respectifs (D₁)(D₂) du iième et du (i - 1)ième étage amplificateur.
2. Circuit amplificateur selon la revendication 1, caractérisé en ce que les moyens de
circuit d'impédance (16)(17) sont chacun configurés comme un circuit d'impédance de
nature moins capacitive.
3. Circuit amplificateur selon la revendication 1 ou 2, caractérisé en ce que les circuits
d'impédance (16)(17) comportent chacun un élément de résistance, un élément d'inductance,
ou un réseau comprenant des éléments de résistance et d'inductance couplés l'un a
l'autre.
4. Circuit amplificateur selon l'une quelconque des revendications précédentes, caractérisé
en ce que la grille du transistor à effet de champ du (i - 1)ième étage présente le même potentiel que celle du transistor à effet de champ du second
étage.
5. Circuit amplificateur selon l'une quelconque des revendications précédentes, caractérisé
en ce que le drain du transistor à effet de champ du iiéme étage présente le même potentiel que celui du transistor à effet de champ du (i -
1)ième étage.
6. Circuit amplificateur selon l'une quelconque des revendications précédentes, caractérisé
en ce que les grilles des n transistors à effet de champ sont connectées en commun à une borne de polarisation
de grille (9) à travers des éléments d'impédance (7)(8), respectivement.
7. Circuit amplificateur selon la revendication 6, caractérisé en ce que le circuit amplificateur
est mis en oeuvre dans l'état dans lequel lorsqu'aucun courant ne circule entre chacune
des grilles (G₁)(G₂) des n transistors à effet de champ et la borne de polarisation de grille (9), le nombre
des éléments d'impédance (7)(8) est réduit à au moins la moitié.
8. Circuit amplificateur selon l'une quelconque des revendications précédentes, caractérisé
en ce que les drains des n transistors à effet de champ sont connectés en commun à une borne d'alimentation
de polarisation de drain (6) à travers des éléments d'impédance de charge (4)(5),
respectivement.
9. Circuit amplificateur selon l'une quelconque des revendications précédentes, caractérisé
en ce que le transistor à effet de champ du premier étage (G₁) est prévu avec une
borne d'entrée (14) couplée à sa grille et le transistor à effet de champ de l'étage
final (G₂) est prévu avec une borne de sortie (15) couplée à son drain (D₂).
10. Circuit amplificateur comportant au moins deux étages de transistors à effet de champ
(1)(2) connectés en cascade l'un à l'autre, une borne d'entrée (14) pour un signal
d'entrée prévue dans le transistor à effet de champ du premier étage, un condensateur
interétage (3) couplé entre les transistors à effet de champ successivement connectés
(1)(2) et une borne de sortie (15) couplée au drain (D₂) de l'étage final des étages
des transistors à effet de champ, pour sortir de ce fait un signal amplifié depuis
la borne de sortie (15), caractérisé en ce qu'il existe des premiers moyens de circuit
d'impédance (16) délivrant une contre-réaction négative qui permet à une composante
continue d'un signal de contre-réaction de passer à travers celui-ci, le premier moyen
de circuit d'impédance (16) étant couplé entre les grilles respectives (G₁)(G₂) des
transistors à effet de champ du premier étage et du second étage (1)(2), un second
moyen de circuit d'impédance (17) assurant une contre-réaction négative ayant la même
fonction que celui du premier moyen de circuit d'impédance (16), le second moyen de
circuit d'impédance (17) étant couplé entre les drains (D₁)(D₂) des premier et second
transistors à effet de champ (1)(2).
11. Circuit amplificateur selon la revendication 10, caractérisé en ce que chacun des
premier et second moyens de circuit d'impédance (16)(17) est configuré comme un circuit
d'impédance de nature moins capacitive.
12. Circuit amplificateur selon la revendication 11, caractérisé en ce qu'un circuit d'impédance
comporte un élément de résistance, un élément d'inductance, ou un réseau comprenant
une résistance et une inductance couplée l'une à l'autre.
13. Circuit amplificateur selon soit la revendication 10, soit la revendication 11, caractérisé
en ce que la grille (G₁) du transistor à effet de champ du premier étage présente
le même potentiel que celle du transistor à effet de champ du second étage.
14. Circuit amplificateur selon la revendication 10, dans lequel chacun des drains (D₁)(D₂)
des premier et second transistors à effet de champ est connecté au second moyen de
circuit d'impédance (17) pour présenter le même potentiel.
15. Circuit amplificateur selon la revendication 10, caractérisé en ce que les grilles
(G₁)(G₂) des transistors à effet de champ (1)(2) qui sont connectés en cascade l'un
à l'autre sont connectées en commun à une borne de polarisation de grille (9) à travers
les éléments d'impédance (7)(8), respectivement.
16. Circuit amplificateur selon la revendication 10, caractérisé en ce que les drains
(D₁)(D₂) des transistors à effet de champ (1)(2) qui sont connectés en cascade sont
connectés en commun à une borne d'alimentation de polarisation de drain (6) à travers
des éléments d'impédance de charge (4)(5), respectivement.