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(11) | EP 0 173 526 A2 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Digital signal repeater including means for controlling a transmitter |
| (57) 57 A digital signal repeater has a receiver for receiving a modulated carrier wave
and demodulating a digital signal, a transmitter for transmitting a carrier wave modulated
by the digital signal, and a controller responsive to the output of the receiver for
providing a control signal controlling the transmitting operation of the transmitter,
the controller including first decision means for detecting the level of the modulated
carrier wave of an intermediate frequency band of the receiver and providing a first
signal, second decision means for detecting a clock frequency component in the output
of the receiver and providing a second signal, logic means responsive to the first
and second signals for providing a third signal first means for smoothing the third
signal, and comparator means for comparing the output of the first means with a reference
level and providing the control signal. |
Background of the Invention
[0001] The present invention relates to a digital signal repeater for repeating digital signals and, more particularly, to a repeater of the type including a controller for controlling activation/non-activation of a radio transmitter.
[0002] A repeater of the type described is generally made up of a radio receiver, a radio transmitter, and a controller. The receiver receives a modulated wave from a terminal station or the like and demodulates it to provide a digital signal, while the transmitter transforms the digital signal again to a modulated wave which is sent to another terminal station or the like. The controller controls the transmitter such that while a modulated wave is received the transmitter is activated (turned on) to repeat a digital signal to another terminal station or the like and, while a modulated wave is not received, it is not activated (turned off) not to repeat a digital signal. Whether or not a modulated wave has been received may be determined by detecting the level of a modulated wave in the intermediate frequency'<IF) band of the receiver.
[0003] However, this kind of approach has the drawback that the IF band modulated wave level sometimes reaches a sufficient value even when an interference wave from another system is received, thereby undesirably activating the transmitter to repeat needless signals.
Summary of the Invention
[0004] It is therefore an object of the present invention to provide a digital signal repeater having an improved controller which is free from the above-described drawback.
[0005] In accordance with the present invention, there is provided a digital signal repeater having a receiver for receiving a modulated carrier wave and demodulating a digital signal, a transmitter for transmitting a carrier wave modulated by the digital signal, and a controller responsive to the output of the receiver for providing a control signal controlling the transmitting operation of the transmitter. The controller comprises first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal, second decision means for detecting a clock frequency component in the output of the receiver and providing.a second signal, logic means responsive to the first and second signals for providing a third signal, first means for smoothing the third signal, and comparator means for comparing the output of the first means with a reference level and providing the control signal.
Brief Description of the Drawings
[0006] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
FIG. 1 is a circuit diagram showing a first embodiment of a digital signal repeater in accordance with the present invention;
FIGS. 2A - 2I are timing charts representative of the operation of the repeater shown in FIG. 1; and
FIG. 3 is a circuit diagram showing another embodiment of the present invention.
Detailed Description of the Invention
[0007] Referring to FIG. 1 of the drawings, a digital signal repeater embodying the present invention is shown and generally comprises a receiver 1, a transmitter 2, and a controller 100. A carrier wave modulated by a digital signal and coming in through an antenna is applied to and amplified by a radio frequency (RF) amplifier 31 which is included in the receiver 1. The output of the RF amplifier 31 is converted by a frequency converter 32 to an intermediate frequency (IF) and, then, amplified by an IF amplifier 33. The modulated wave in the IF band is demodulated by a demodulator 34 and, then, transformed into a digital signal (DATA).
[0008] In the transmitter 2, a modulator 41 modulates a carrier wave again by the digital signal (DATA) and applies its output to a frequency converter 42 which converts the input to the RF band. The modulated wave in the RF band is transmitted via a power amplifier 43 to a terminal station or another repeater (not shown) which follows the illustrated repeater.
[0009] The transmission control over the power amplifier 43 is performed by the controller 100 as will be described in detail hereinafter.
[0010] The controller 100 comprises a first decision circuit 3, a second decision circuit 4, an AND gate 5, a time constant circuit 6, and a comparison circuit 7. The first decision circuit 3 is adapted to detect the level of the IF modulated wave outputted from the IF amplifier 33 so as to determine whether nor not the receiver 1 is receiving a signal and, for this purpose, it comprises a level detector 8, a comparator or differential amplifier 9, and a potentiometer 10. As shown in FIG. 2A, the modulated wave IF has undergone level fluctuation due to fading particular to a radio section. The level detector 8 is adapted to detect the modulated wave IF. As shown in FIG. 2B, the output x8 of the level detector 8 appears as an envelope. The comparator 9 compares the detector output x8 with a reference voltage VCl which is determined by the potentiometer 10 and, if the former is higher than the latter, produces- an output x3 showing that the receiver 1 is receiving a signal. The comparator output x3 is delivered to the AND gate 5 as an output of the first decision circuit 3 (FIG. 2C).
[0011] The second decision circuit 4 is made up of a bandpass filter 11, a level detector 12, a comparator or differential amplifier 13, and a potentiometer 14. The function assigned to the decision circuit 4 is detecting the level of a recovered clock which is synchronous with a received digital signal in order to see if the receiver 1 is receiving a digital signal. Applied to the input terminal of the decision circuit 4 is a signal CF which contains a clock frequency component obtained by full-wave rectification of the output of the demodulator 34.
[0012] The bandpass filter 11 separates the clock frequency component from the input signal CF of the decision circuit 4, thereby producing an output signal xll as shown in FIG. 2D. Comparing FIGS. 2A and 2D, it will be seen that the signal x11 appears as noise so long as the receiver 1 does not receive a signal and, hence, the bandpass filter 11 outputs a clock frequency component which is contained in the noise; as the receiver 1 receives a signal, the signal xll greatly flucturates because the clock frequency is significantly lower than the intermediate frequency and because the clock frequency component is effected by a code pattern of information which is being transmitted.
[0013] The level detector 12 detects a level of the signal x11 to deliver an output x12. As shown in FIG. 2E, the detector output x12 appears as an envelope. The comparator 13 compares the signal x12 with a reference voltage VC2 which is determined by the potentiometer 14 and, if the former is higher than the latter, produces an output x4 (FIG. 2F) as an output of the decision circuit 4, showing that the receiver 1 is receiving a digital signal.
[0014] What is of prime importance here is how to mix the output x3 of the decision circuit 3 (FIG. 2C) and the output x4 of the decision circuit 4 (FIG. 2F). The output x3 of the decision circuit 3 which shows whether or not a received intermediate frequency is present rises even when interference waves such as attributable to adjacent channels are received, if the interference waves are sufficient in level. Therefore, should the transmitter 2, i.e., the power amplifier 43 be activated by the output x3 of the decision circuit 3 only, there would be brought about the problem of erroneous repeating.
[0015] Although the transmitter 2 may be activated by directly using the output x4 of the decision circuit 4 only, such an approach also involves the fear of erroneous repeating considering the fact that the clock frequency contained in the noise waveform sometimes reaches a sufficient level even if the receiver is not receiving a signal.
[0016] In accordance with the present invention, the shortcoming of the decision circuits 3 and 4 as discussed above is compensated for by applying the output x3 of the decision circuit 3 and the output x4 of the decision circuit 4 to the time constant circuit 6 after the AND gate 5. Specifically, when the output x3 of the decision circuit 3 has built up responsive to an interference wave as derived from another system or from adjacent channel, the output of the AND gate 5 does not rise because the clock frequency component cannot rise to a sufficient level. When the output x4 of the decision circuit 4 has risen responsive to noise in a non-receiving condition of the receiver 1, it is not reflected by the output x5 of the AND gate 5 because the output of the decision circuit 3 remains logical "0" then.
[0017] The output x5 of the AND gate 5 (FIG. 2G) is routed to the time constant circuit 6. As shown, the time constant circuit 6 comprises an RC circuit made up of a resistor 15 and a capacitor 18 and, in addition, a series connection of a resistor 16 and a diode 17 which is connected in parallel with the resistor 15, thereby attaining a fast rise response and a slow fall response. Such a response characteristic of the time constant circuit 6 not only allows the response at the start of signal reception to be designed fast but also eliminates the influence of the logical "0" level of the output x5 of the AND gate 5 which may occur momentarily when the level of the modulated wave IF has lowered due to fading or when the clock component of the input CF to the decision circuit 4 has decreased effected by a code pattern of information.
[0018] The output x6 of the time constant circuit 6 (FIG. 2H) is compared by a differential amplifier 19 of the comparison circuit 7 with a reference voltage VC3 which is determined by a potentiometer 20, whereby a transmission control signal x7 (FIG. 2I) is produced. The control signal x7 is adapted to selectively enable and disenable the transmission of a wave by on-off controlling a power source associated with the power amplifier 43 or controlling an attenuator which is connected to the former stage of the power amplifier 43.
[0019] In the particular embodiment shown in FIG. 1, each of the level detectors 8 and 12 is provided with a relatively fast response characteristic, that is, it responds within a relatively short period of time. Although such fast response will be reflected by fast changes of "1" or "0" in the output x5 of the AND gate 5, the time constant circuit 6 successfully removes the fluctuation of the output x5. Since the AND gate 5 shows a fast response at the time of rising, even the whole circuitry 3-7 is capable of rapidly operating when signal reception is started.
[0020] Referring to Fig. 3, a digital signal repeater in accordance with another embodiment of the present invention is shown. As shown, the repeater in this particular embodiment is constructed by adding to the repeater of FIG. 1 a time constant circuit 21, a comparison circuit 22, and a resistor 27, so that even more positive operation than the repeater of FIG. 1 may be accomplished at the time of signal reception. Specifically, in Fig. 3, data indicative of a level of recovered clock is picked up from the output x12 of the detector 12 and applied to the time constant circuit 21. Comprising a resistor 23 and a capacitor 24, the time constant circuit 21 removes fluctuation taking a substantial period of time. The comparison circuit 22, i.e., a differential amplifier 25 compares an output of the time constant circuit 21 with a reference voltage VC4 which is determined by a potentiometer 26. In this construction, the output of the comparison circuit 22 becomes low level when the recovered clock has been decided to be at a sufficient level taking a comparatively long period of time.
[0021] In this manner, the result of decision appearing at the output terminal of the comparator 22 is free from the influence of noise and that of a code pattern and, hence, it can be positively regarded as indicating that the receiver 1 is receiving a digital signal. At this instant, the level of the reference voltage VC3 applied to the comparator 7 may be lowered by a suitable value by the output of the comparator 22 via a resistor 27 in order to stably maintain the output of the comparator 7 constant even when the output of the time constant circuit 6 undergoes significant fluctuation due to fading or any Other cause.
[0022] In summary, it will be seen that the present invention provides a digital signal repeater which is immune to interference due to adjacent channels and the like and, yet, rapidly identifies reception of a digital signal. The repeater, therefore, is desirably applicable to transmission control in a digital signal repeating system.
1. A digitil signal repeater having a receiver for receiving a modulated carrier wave
and demodulating a digital signal, a transmitter for transmitting a carrier wave modulated
by the digital signal, and a controller responsive to the output of the receiver for
providing a control signal controlling the transmitting operation of the transmitter,
characterized in that the controller comprises:
first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal;
second decision means for detecting a clock frequency component in the output of the receiver and providing a second signal;
logic means responsive to the first and second signals for providing a third signal;
first means for smoothing the third signal; and
comparator means for comparing the output of the first means with a reference level and providing the control signal.
2. A digital signal repeater as claimed in Claim 1, wherein the first means shows
a fast response to the start of the third signal and a slow response to the end of
the third signal.
3. A digital signal repeater as claimed in Claim 1, wherein the controller further
comprises third decision means for detecting that the clock frequency component in
the output of the receiver has a sufficient level for a comparatively long period
of time and varying the reference level.