(19)
(11) EP 0 192 139 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
25.04.1990 Bulletin 1990/17

(43) Date of publication A2:
27.08.1986 Bulletin 1986/35

(21) Application number: 86101598.0

(22) Date of filing: 07.02.1986
(51) International Patent Classification (IPC)4G09G 1/16
(84) Designated Contracting States:
DE FR GB NL

(30) Priority: 19.02.1985 US 702982

(71) Applicant: TEKTRONIX, INC.
Beaverton Oregon 97077 (US)

(72) Inventor:
  • Knierim, David L.
    Wilsonville Oregon 97070 (US)

(74) Representative: Liesegang, Roland, Dr.-Ing. 
FORRESTER & BOEHMERT Franz-Joseph-Strasse 38
80801 München
80801 München (DE)


(56) References cited: : 
   
       


    (54) Frame buffer memory controller


    (57) A frame buffer memory controller (24) allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller (24) controls one or more pixel depth columns comprising one or more frame buffer memory chips (22) per pixel. Each frame buffer memory controller (24) listens on a display processor bus (26) for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer (35) for execution during the first free memory cycle.







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