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(11) | EP 0 192 139 A3 |
(12) | EUROPEAN PATENT APPLICATION |
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(54) | Frame buffer memory controller |
(57) A frame buffer memory controller (24) allows rapid image updating while maintaining
screen refresh data flow rate. One frame buffer memory controller (24) controls one
or more pixel depth columns comprising one or more frame buffer memory chips (22)
per pixel. Each frame buffer memory controller (24) listens on a display processor
bus (26) for read, write or read-modify-write commands addressed to a pixel, or memory
chip, under its control. Such commands, along with the associated addresses and data,
are stored in a first-in, first-out (FIFO) buffer (35) for execution during the first
free memory cycle. |