(19)
(11) EP 0 195 883 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
11.07.1990 Bulletin 1990/28

(43) Date of publication A2:
01.10.1986 Bulletin 1986/40

(21) Application number: 86100110.5

(22) Date of filing: 07.01.1986
(51) International Patent Classification (IPC)4: G09G 1/00
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 28.02.1985 US 706801

(71) Applicant: International Business Machines Corporation
Armonk, N.Y. 10504 (US)

(72) Inventor:
  • Le, Trung
    Austin Texas 78727 (US)

(74) Representative: Schuffenecker, Thierry 
Compagnie IBM France, Département de Propriété Intellectuelle
06610 La Gaude
06610 La Gaude (FR)


(56) References cited: : 
   
       


    (54) Glitch energy reduction in digital gray scale CRT diplay


    (57) A circuit addition is described for a digital, gray scale CRT display circuit to substantially reduce glitch distortion during CRT beam intensity changes. A high pass filter and DC restoration circuit couples the control grid of the CRT to the video amplifier such that the cathode and control grid substantially track each other during a glitch. This results in no substantial change in beam intensity as would otherwise be perceived during a glitch. This is accomplished without signal conditioning prior to the output of the video amplifier circuit by means of either delaying the higher order bits of the binary value corresponding to the desired intensity level or sampling and holding the analog output of the D/A converter prior to application of that signal to the video amplifier.






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