|
(11) | EP 0 197 965 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
|
|
| (54) |
A FIELD EFFECT TRANSISTOR CURRENT SOURCE FET-STROMQUELLE SOURCE DE COURANT POUR TRANSISTOR A EFFET DE CHAMP |
|
|
|||||||||||||||||||||||||||||||
| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
[0001] This invention relates to an integrated circuit comprising a current source adapted to provide a constant current.
[0002] Most linear circuits are biased by means of a current source. It is usually thought desirable that this source provide a current that is independent of temperature, power supply, and process variations. One current source in common use takes advantage of the logarithmic insensitivity of a bipolar transistor's forward base-emitter voltage, VBE, to power supply and process variations A resistor placed across the emitter-base junction of an active transistor will give a reference current equal to VBE/R. CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuits have also used this technique by taking advantage of the intrinsic bipolar transistor in the CMOS structure. Unfortunately, this current source has a large temperature dependence, since VBE has an intrinsic negative temperature coefficient of approximately -2 mv/degree C, and the resistor has a positive temperature coefficient. Hence, the current from this source has a large negative temperature coefficient.
[0003] A great deal of work has been done on circuits that provide a constant reference voltage, but relatively less on the apparently similar job of producing a constant reference current. In the case of field effect transistor (FET) current sources, steps are frequently taken to mitigate the effects of large lot-to-lot variations in device parameters, for which field effect transistors are notorious. In particular, circuits are usually designed to minimize the effects of threshold and gain variations that occur for field effect transistors on different wafers. For example, a resistor is typically included in the source path of a FET to provide degenerative feedback, which reduces these variations.
[0004] U.S.A. patent no. 4009432 discloses a constant current supply which includes a field effect transistor having a gate-source resistor, and means for providing an output current. A current mirror increases the gain of the circuit, thereby improving the power supply rejection. There is no suggestion or description of achieving a desired temperature coefficient.
[0006] When utilized with analog or digital field effect transistor circuitry implemented on the same semiconductor substrate, the reference circuit also compensates for processing variations. In a preferred embodiment, the field effect transistor is an enhancement mode type.
Brief Description of the Drawings
[0007]
FIG. 1 illustrates a field effect transistor current source reference circuit;
FIG. 2 illustrates a first circuit for use in implementing the present invention;
FIG. 3 illustrates a second circuit for use in implementing the present invention;
FIGS. 4 and 5 show controlled transistors for implementing current sources relative to positive and negative voltage terminals, respectively;
FIGS. 6 and 7 illustrate a prior art current source reference resistor;
FIGS. 8, 9 and 10 illustrate a novel current source reference resistor; and
FIG. 11 illustrates the effect of process variations on current source output for reference resistors of differing widths for the resistor type shown in FIGS. 8-10.
Detailed Description
[0008] The following description relates to a circuit which can provide a temperature and power supply independent current, and in a preferred embodiment actively compensates for inherent process variations. This results in a smaller spread of linear circuit parameters, such as operational amplifier slew rate, gain, and gain-bandwidth, than can be obtained with an "ideal" current source. The present technique results in part from a recognition that positive and negative temperature coefficient terms can be balanced to a desired degree in a FET, to obtain a desired temperature coefficient. The present invention also provides that the current source FET may be fabricated by the same fabrication process (e.g., on the same semiconductor substrate) as the circuits utilizing the controlled current. Then, process variations produce changes in the current source FET that offset changes in performance parameters (e.g., gain, slew rate, etc.) in the controlled circuit. By this technique, a FET is utilized to good advantage as a current source.
[0009] The basic core of the source is shown in FIG. 1, wherein a field effect transistor has a reference resistor (R) connected between the gate and the source. The field effect transistor is typically an insulated gate type (i.e., an IGFET), which may be a metal-oxide-silicon field effect transistor (MOSFET) type. In the saturation region, the current through the channel of the IGFET is:
where β is the gain, VGS is the voltage of the gate with respect to the source and Vt is the threshold voltage, of the IGFET. For a MOSFET, the gain ((3) may be approximated as β = (Z/L) p Cox, wherein Z is the width of the channel, L is the length of the channel, u is the mobility of majority carriers in the channel, and Cox is the gate capacitance per unit area. The value of Cox can be calculated as: The permittivity of free space times the dielectric constant of the gate insulator (about 3.85 for an oxide) divided by the thickness of the gate insulator. Equation (1) may be solved for VGS:
For a constant channel current I, the temperature coefficient of VGS is the sum of two terms. The first involves β, whose temperature dependence arises from that of the mobility of the majority carriers flowing in the channel between the source and the drain. The mobility (p) is limited by lattice scattering, which has a temperature dependence of:
where %0 is the mobility at temperature To. Typical values of µ0 range from 520 to 775 cm2/volt-sec for n-channel FET's, and from 185-240 cm2/volt-sec for p-channel FET's, at To = 20°C. In practice, surface scattering changes the exponent somewhat from its theoretical value of -3/2.
[0010] The threshold voltage (Vt) has an intrinsic negative temperature coefficient that depends only weakly on process parameters. For a typical Complementary MOS (CMOS) technology based upon 3-5 micrometer design rules, this value is -2.3 mv/degree C. Equation (2) can now be written as:
Note that β0 is the gain at temperature To. It is now apparent that VGS is the sum of two terms with opposing temperature coefficients; that of β0 being positive, and Vt being negative. In addition, the magnitude of the second term in Equation (4) depends on the channel current, so that the total temperature coefficient of VGS can easily be adjusted. (A complete analytical treatment is included in the Appendix.) Since the reference current IR = VGS/R, it is apparent that the desired temperature coefficient of the reference current is dependent on the threshold voltage (Vt), the channel current (I), and the gain (p).
[0011] The ability of this source to compensate for process variations is also shown in Equation 4. A "fast" (e.g., relatively thin gate oxide and short channel length) process will have a large (3, and thus a small value of VGS. The reference current (IR) is equal to VGS/R, so it will decrease. A "slow" (e.g., relatively thick gate oxide and long channel length) process with a small β wil have a larger VGS, and thus a larger reference current. In terms of the physical process, a fast process usually results from relatively more etching of the gate material, which reduces its length relatively more than its width. Hence, when the channel is formed, the ratio Z/L is increased. The opposite is true for a slow process. Other factors may also be involved, such as semiconductor junction depths, gate insulator thicknesses, doping levels, etc.
[0012] A simple circuit that uses the VGS/R concept to generate a constant current is shown in FIG. 2. To obtain a desired temperature coefficient (TC), the channel current through the reference transistor (M3) should be held proportional to the reference current (IR). For this purpose, transistor M1 mirrors the channel current in M5, which is connected as a diode. Note that M5 also causes the reference current IR to flow through R1. Hence, IR is identical to the channel current flowing through M5. If a current I is flowing in M1 and M5, then current 21 is mirrored in M4, which is twice the size of M2. The channel current in reference transistor M3 is equal to that in M4 minus that delivered by M5. The final result is that a current I flows through all the transistors except M4, which has a current of 21. Since the channel current through M3 is forced to be equal to the reference current in R1, a stable feedback loop is formed. Thus the current mirrors are means for causing the channel current (I) in the reference transistor (M3) and the reference current (IR) through the reference resistor (R1) to be proportional. In general, these currents need not be equal, but merely proportional. Thus, I > IR, I = IR, and I < IR are all possible design variations.
[0013] Two output bias voltages are available from this circuit. The bias-out positive (BOP) provides a voltage to the gate of one or more P-channel current output transistors M50; see FIG. 4. The output current, lout is proportional to the reference current, IR. The proportionality constant depends upon the size of M50 as compared to M5 of FIG. 2 (or as compared to M48 of FIG. 3.) A corresponding bias-out negative (BON) can be supplied to one or more N-channel current output transistors M60; see FIG. 5. However, the circuit of FIG. 2 has two stable current states, one of them I = 0. Hence it is desirable to include means to prevent the circuit from reaching the I = 0 state.
[0014] A more typical circuit employing the inventive concept is shown in FIG. 3. The widths and lengths of the transistor channels, in micrometers, is given as W/L for each associated transistor. Transistor M410 and its bias resistors are included to provide proper start-up conditions, i.e., prevent I = 0. For this purpose, M410 is sized to drw a small current, typically less than 0.1% of the current through reference resistor R1, which is set at a nominal value of 100pa. M410 and its bias resistors can be replaced by a depletion transistor. The other additional transistors are optionally included to improve power supply rejection by cascading all of the mirrors, and to mirror the current to M413, which actually drives the negative bias output (BON). A positive bias output (BOP) is provided from the drain of M48.
[0015] The reference resistor R1 can be of any type that gives a positive temperature coefficient of resistance. It is advantageously made with a P+ diffusion, which has a much lower TCR (temperature coefficient of resistivity) and VCR (voltage coefficient of resistivity) than the P-tub. The absolute control of the P+ sheet resistance is also very good, typically within plus or minus 15% of the nominal value. R1 can alternately be made of polysilicon or other material. The sizes of R1 and reference transistor M45 are typically set to give a zero TCC (temperature coefficient of current) in M413 and M48 at nominal conditions. The resistance of the reference resistor (R1) is typically greater than 100 ohms, and typically less than 10 megaohms, although a wider range is possible. The size of the reference transistor (M45) is desirably chosen so that the channel length (L) is large enough to minimize processing variations. A length of about 8 to 10 micrometers is suitable for typical processing conditions. Then, the gain may be set by choosing the width, Z, to give the desired temperature coefficient. One methodology for obtaining the desired temperature coefficient of the current from the source is as follows:
1. Determine the temperature coefficient of the reference resistor (e.g., by measurement or estimates based on material type).
2. Choose a desired reference current (e.g., IR = 100 microamps) and a desired proportionality between channel current in the reference transistor to the reference current (e.g., I/IR = 1).
3. Estimate the approximate size of the reference transistor (e.g., W = 50 micrometers, L = 10 micrometers).
4. Determine Vt and β for the reference transistor thus selected.
5. Determine VGS for the reference transistor, as from equation (2) (e.g., VGS = 1.7 volts).
6. Set reference resistor R = VGS/IR (e.g., 1.7/100x10-s = 17K).
7. Calculate the temperature coefficient of the reference current: (i.e., IR = VGS/R) from 1 above and equation (2).
8. If the IR temperature coefficient is not within desired limits, change a variable reflected in equation (2), and repeat steps 3-7 until desired value obtained (e.g., decrease size of reference transistor to W = 40 micrometers L = 10 micrometers, which reduces the value of P, and increases VGS to 1.815 volts, so that R = 18.15K, which produces approximately zero T.C. for IR).
[0017] Note that in FIG. 3, the reference transistor M45 is shown in its own P-tub, with the back-gate bias, VBX=0. This is desirable to minimize power supply induced variations on the back gate. For this reason, the circuit performance is typically better in CMOS than it would be in NMOS. If a CMOS technology using isolated N-tubs were used, the entire circuit would simply be "flipped" over vertically, and M45 would be a P-channel device in an isolated N-tub. However, the present technique can also be usefully implemented in NMOS (or PMOS) technology, when isolated tubs are not available. In that case, the back-gate of the current control transistor is then connected to the semiconductor substrate, which is connected to the negative (N-channel) or positive (P-channel) power supply terminal.
[0018] To compare the present technique with prior art techniques, computer simulations were done on four different current sensors. The nominal current at 25°C was set at 100pa for all four sources. The effect of temperature on these sources, as well as process variations for both low speed (worst-case slow) and high speed (worst-case fast) conditions, were investigated. The four sources were as follows:
Source A 100pa ideal source
Source B Band-gap source, I=VBG/R, VBG=1.2 volts
Source C VBE/R source
Source D VGS/R source (FIG. 3)
[0019] In sources B-D, the resistor R was assumed to be made with P+ diffusion, and to have a plus or minus 15% maximum variation with processing.
[0020] Varying the temperature from 0 to 100°C showed that the VBE/R source has by far the largest temperature variation. However, the band-gap source (B) also has an appreciable TCC due to the finite TCR of the resistor. The self-compensating feature of the VGS/R source was apparent. At 25°, the low speed process gives 35% higher current, and the high speed process 30% lower current than nominal. Both cases show a larger TCC than exists with the nominal process, but no worse than that of the band-gap source (B).
[0021] The effect of the different current sources on the performance of a typical operational amplifier (op-amp) has also been investigated. The op-amp used in these simulations was a simple two stage design. There are two independent effects of temperature on op-amp performance. The first is the intrinsic effect of temperature on the op-amp, independent of current. The second is the effect of current variations due to the temperature dependence of the current source. The ideal current source (A) is used in these simulations to separate these two effects. The slew rate, gain-bandwidth product (GBW), and gain, as a function of temperature, were investigated for nominal processing at a constant current of 100pa.
[0022] The effect of current variation on these same parameters was also investigated for "worst case (W-C) fast" and "worst case (W-C) slow" conditions, as follows:
[0023] The minimum and maximum values, and the total spread expressed as a % of the median value of the three parameters, are summed up in Table I.
[0024] The performance improvement is most noticeable in those parameters which have the strongest dependence on current, but in all cases the VGS/R source results in a higher minimum value and a lower maximum value. Some insight as to the relative efforts of temperature and process variations can be gained by independently varying these inputs while keeping the reference current set at 100 pa. The results are shown in Table II. Both the slew rate and gain are more strongly effected by the process variations than by temperature, while the GBW is equally effected.
[0025] Among the other parameters of interest in op-amps and other linear circuits are power supply rejection ratio (PSRR), common mode rejection ratio (CMRR), and common mode range. Computer simulations show that the inventive supply is slightly better than the others in both PSRR and CMRR. The common mode range, however, is somewhat worse. This is due to exactly the self-compensating feature that improves the other parameters. The smallest common mode range exists when the transistors are slow and the current is high. In other current sources there is no connection between these two; even when the worst-case assumption of high current is made, it is not as high as it is in the self-compensating source. For the op-amp used here, this results in a worse-case loss of 500mv of input range. This op-amp was not designed to give a particularly large common mode range, and the loss would be proportionally less on op-amps with larger Z/L ratios on the input transistors.
[0026] All of the discussion and results up to this point has assumed that the value of the reference resistor R1 in the inventive current source is independent of the transistor process. This is a good assumption for resistors made in the usual manner, as shown in FIGS. 6 and 7. In this technique, an opening etched in the field oxide allows the resistor to be formed by doping (as by ion implantation) the semiconductor in the region thus defined. For the resistor shown in FIG. 6, the total resistance is:
where Rs is the sheet resistance of the doped semiconductor, and L and W are the length and width of the field oxide defined opening. An insulating layer (e.g., a glass), is typiclaly deposited over the resistor, with contact windows then etched therethrough.
[0027] Another way to define the resistor is shown in FIGS. 8 and 9. In this case, the polysilicon (poly) level is used instead of the field oxide to define the feature size. The poly line size is one of the most critical and well controlled parameters in the process, and in self-aligned silicon gate technology, the polysilicon layer defines the gate electrode size. Hence, thie poly line size will often determine whether any given wafer is "slow" or "fast". For this reason, a resistor defined by the layer that defines the gate electrode can have a tighter design tolerance than one defined by the field oxide. Let us assume that the actual poly line size differs from the nominal size by an amount DL. A positive DL means wider poly and a slower process, negatiove DL means narrow poly and a fast process. As shown in FIOG. 11, the resistor width is W- DL, so that:
[0028] A positive DL (slow process) causes the resistor to increase, and the negative DL (fast process) causes it to decrease from the design value. This will oppose the "self-compensation" feature of the VGS/R source, since process induced changes in VGS will now be tracked by a similar change in R. The relative value of these two quantities depends on the resistor's nominal width. For an extremely wide resistor, R does not depend on DL at all. As the resistor width decreases, the effect of DL becomes larger. Note that other self-aligned gate electrode materials (e.g., a refractory metal or metal silicide) can be used to define the resistor, to achieve this effect.
[0029] The current I = VGS/R for three different resistor widths is shown in FIG. 11. It was calculated using the 40/10 N-channel transistor M45 in FIG. 3 and nominal process conditions. The case of infinite resistor width corresponds to the case discussed above. At 7 microns the current is nearly independent of poy line size, and at 4 microns the process compensation is actually the reverse of that discussed above.
[0030] The circuit shown in FIG. 3 has been implemented in a typical 3.5 micron Twin-Tub CMOS process on a n-type substrate on a lot in which the poly width was intentionally varied. The resistor R1 was poly defined, with a nominal width of 4 microns. The current vs. temperature curves for three different wafers were determined. The sheet resistance of the P+ diffusion, was measured at 10 percent below the nominal value for this lot. This accounts for most of the difference between the measured current of 107 jja and the design value of 100 pa for the nominal poly. For a wafer with a measured DL=+0.44 pm, the current calculated from FIG. 11 was 87% of the nominal value, and the measured current was 84% of the nominal. For a wafer with a measured DL=-0.22pm, the calculated current was 105% nominal, and the measured current was 114% of the nominal. For the nominal poly, the maximum variation of current over the temperature range 10°C-120°C was 2.1%. From 25°C-120°C it is 1.5%. Both the narrow and wide poly had similar temperature variations of their current.
[0031] The foregoing has shown that in the present technique the temperature coefficient of current can be zero (nominally, as second order effects give a slight curvature).
[0032] For a zero temperature coefficient of current the resulting controlled current can be readily maintained within ±5 percent, and typically within ±2 percent, of the average value, over a temperature range of from 0°C to 100°C, or even wider. These values are even more readily obtained over a typical commercial temperature range of from 0°C to 70°C. The current source automatically compensates for variations in the transistor process, with a "fast" process giving lower current and a "slow" one giving a higher current. If desired, this compensation can be reduced or eliminated with respect to variations in the polysilicon line width size by proper resistor design. While the above example has been for an enhancement mode MOSFET, similar considerations apply for depletion mode devices, including junction field effect transistors, and Shottky gate field effect transistors (e.g., MESFETS) implemented in gallium arsenide or other III-V materials.
[0033] However, one advantage of the present technique is that it does allow the use of enhancement mode FET's; i.e., those having a threshold voltage, Vt, that is >0 for an n-channel device, and Vt < 0 for a p-channel device. Note that thee voltages are measured at the gate in reference to the source; i.e., VGS. Enhancement mode field effect transistors are typically of the insulated gate (IGFET) type, of which MOSFET's are an example. Their use is advantageous because a smaller channel current can then typically be utilized in the reference transistor than if a depletion-mode device were used. This is because in the present technique, the reference current is directed through the reference resistor in the direction that causes the channel current in the reference transistor to flow (or to increase its flow), as the reference current increases. That is, VGS is generated in the direction of forward bias by the reference current. Hence, the power dissipation can be less with enhancement mode FET's. Furthermore, enhancement mode field effect transistors are usually available on an integrated circuit using fewer process steps than depletion mode devices require. A depletion mode device may be used, however, by operating it in the enhancement mode; i.e., where the channel current is greater in magnitude than the channel current for VGS = 0. Note that the means for causing the channel current and the reference current to be proportional (e.g., a current mirror) inherently produces the desired direction of reference current flow. This is in contrast with the prior art technique of biasing a current source FET using degenerative feedback by placing a resistor in the source path. In that case, an increase in the current through the resistor causes a change in VGS in the direction that tends to decrease the channel current of the FET.
[0034] While the present invention may be used in analog integrated circuits, it may also be used in digital integrated circuits. For example, in certain random access memory designs, it is known to use a current source for the sense amplifiers, for improved speed and sensitivity. In addition, the use of a controlled current source is known for use with digital logic circuits to reduce chip-to-chip performance variations. In the past, the current source associated with the logic gates has been controlled using a reference clock and comparator circuitry; see "Delay Regulation - A Circuit Solution to the Power/Performance Tradeoff", E. Berndlmaier et al, IBM Journal of Research and Development, Vol. 25, pp. 135-141 (1981). ). The present invention can advantageously be implemented on the same chip or wafer as the logic gates to perform this function.
[0035] Since processing conditions are similar to all circuits on a given semiconductor wafer, the present technique lends itself to wafer scale integration uses. If desired, a single bias circuit (e.g., FIG. 3) can provide control of a plurality of current output transistors (FIGS. 4, 5) located at various places on a chip or wafer. The term "integrated circuit" as used herein includes both utilizations. The controlled current from the present source can be used to produce a controlled voltage, as by passing it through a resistor having a given temperature coefficient, or through a resistor-diode combination; i.e., a band-gap reference, etc. The characteristics of a band-gap reference are described in "New Developments in IC Voltage Regulators", R. J. Widlar, IEEE Journal of Solid State Circuits, Vol. SC-6, pp. 2-7 (1971). Also, the device receiving the controlled current may be formed on a different substrate from the current source.
APPENDIX
[0036] Referring to the current source shown in FIG. 2; define a reference current IR as the current through R1, IDS3 as the current through M3 with gate to source voltage VGS3, and KIR as the current through M4, where K is the feedback constant determined by the relative sizes of M1, M2, M4, and M5. The value of K shown in FIG. 2 is two, but it may be any value consistent with stability. Summing the currents at the drain of M4 gives:
However:
Substituting (1A) into (2A) and rearranging gives:
which is quadratic in ORH. Solving gives:
Squaring and rearranging gives:
[0037] As can be seen in (5A), ther eare two real solutions; however, the solution with the negative sign in the bracket is a class of solutions for VGS2 < Vt, or zero current through M3. These solutions correspond to loss of regulation in the source.
[0039] Which has an inherent negative temperature coefficient. For R1β/(K-1)<<1, Equation (5A) reduces to:
which has an inherent positive temperature coefficient. Even though 1/R12 has negative temperature behavior, it is outweighed by 1/(3 which goes as T3/2.
1. An integrated circuit comprising a current source adapted to provide a constant
current (I Out) to at least one device, wherein said current source comprises a reference
field effect transistor (M3) having a specified threshold voltage, a specified gain,
and a gate electrode connected to a source electrode thereof by means of a reference
resistor (R1), means (M1, M2, M4, M5) for causing a reference current to flow through
said reference resistor in proportion to the current that flows through the channel
of said reference transistor, and means (M50) for causing said constant current to
be proportional to said reference current, characterized in that the magnitude of
the channel current (I) flowing in said reference transistor is such that an approximately
zero temperature coefficient is obtained for said constant current.
2. An integrated circuit as claimed in claim 1 wherein said reference field effect
transistor is an enhancement mode transistor.
3. An integrated circuit as claimed in claim 1 or 2 comprising at least one field
effect transistor of a first channel conductivity type, and at least one transistor
having a channel conductivity type opposite said first type.
4. An integrated circuit as claimed in claim 3 and formed in a semiconductor substrate
comprising at least one first region of said first conductivity type having a plurality
of field effect transistors formed therein, and a second region of said opposite conductivity
type wherein said reference field effect transistor is formed, said second region
being isolated by a p-n junction from said first region.
5. An integrated circuit as claimed in claim 4 wherein the source of said reference
field effect transistor is electrically connected to the isolated region.
6. An integrated circuit as claimed in any preceding claim wherein said reference
field effect transistor has its back-gate electrode connected to a reference voltage.
7. An integrated circuit as claimed in any preceding claim wherein said reference
resistor is formed by implanting a dopant through an opening in a layer of material
that forms said gate electrode, whereby the size of said reference resistor varies
according to process variations that also affect the size of said gate electrode.
8. An integrated circuit as claimed in claim 7 wherein said material comprises polysilicon.
9. An integrated circuit as claimed in any preceding claim wherein said means for
causing a reference current to flow in proportion to said channel current comprises
a current mirror.
1. Integrierte Schaltung mit einer Stromquelle, die einen Konstantstrom Oout) an wenigstens
ein Bauteil liefert, wobei die Stromquelle einen Bezugsfeldeffekttransistor (M3) mit
einer vorgegebenen Schwellenwertspannung und einer vorgegebenen Verstärkung besitzt
und bei dem die Gate-Elektrode mit der Source-Elektrode über einen Bezugswiderstand
(R1) verbunden ist, ferner eine Einrichtung (M1, M2, M3, M4, M5), die einen Bezugsstrom
über den Bezugswiderstand im Verhältnis zu dem Strom, der über den Kanal des Bezugstransistors
fließt, fließen läßt und eine Einrichtung (M50), die bewirkt, daß der Konstantstrom
dem Bezugsstrom proportional ist, dadurch gekennzeichnet, daß die Größe des über den
Bezugstransistor fließenden Kanalstroms (I) so gewählt ist, daß sich für den Konstantstrom
ein Temperaturkoeffizient von etwa Null ergibt.
2. Integrierte Schaltung nach Anspruch 1, bei der der Bezugsfeldeffekttransistor ein
Anreicherungstyp-Transistor ist.
3. Integrierte Schaltung nach Anspruch 1 oder 2, mit wenigstens einem Feldeffekttransistor
eines ersten Kanal-Leitfähigkeitstyps und wenigstens einem Transistor eines Kanal-Leitfähigkeitstyps,
der dem ersten Typ entgegengesetzt ist.
4. Integrierte Schaltung nach Anspruch 3, gebildet in einem Halbleitersubstrat, daß
wenigstens eine erste Zone des ersten Leitfähigkeitstyps mit einer Vielzahl von darin
erzeugten Feldeffektransistoren besitzt, und eine zweite Zone des entgegengesetzten
Leitfähigkeitstyps, in welcher der Bezugsfeldeffektransistor gebildet ist, wobei die
zweite Zone durch eine pn-Übergang von der ersten Zone isoliert ist.
5. Integrierte Schaltung nach Anspruch 4, bei der Source-Anschluß des Bezugsfeldeffekttransistors
elektrisch mit der isolierten Zone verbunden ist.
6. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der die rückseitige
Gate-Elektrode des .Bezugsfeldeffekttransistors mit einer Bezugsspannung verbunden
ist.
7. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der der Bezugswiderstand
durch Implantieren eines Dotierstoffs durch eine Öffnung in einer die Gate-Elektrode
bildenden Schicht erzeugt ist, wobei die Größe des Bezugswiderstands sich entsprechend
den Prozeßänderungen verändert, die auch die Größe der Gate-Elektrode beeinflußen.
8. Integrierte Schaltung nach Anspruch 7, bei der das Material Polysilizium umfaßt.
9. Integrierte Schaltung nach einem der vorhergehenden Ansprüche, bei der die Einrichtung,
die bewirkt, daß ein Bezugsstrom im Verhältnis zu dem Kanalstrom fließt, einen Stromspiegel
umfaßt.
1. Un circuit intégré comprenant une source de courant conçue pour fournir un courant
constant à à au moins un dispositif, dans lequel cette source de courant comprend
un transistor à effet de champ de référence (M3) ayant une tension de seuil spécifiée,
un gain spécifié et une électrode de grille connectée à une électrode de source de
ce transistor par l'intermédiaire d'une résistance de référence (R1 ), des moyens
(M1, M2, M4, M5) pour faire circular un courant de référence dans la résistance de
référence, proportionnellement au courant qui circule dans le canal du transistor
de référence, et des moyens (M50) pour faire en sorte que ce courant constant soit
proportionnel au courant de référence, caractérisé en ce que l'intensité du courant
de canal (I) qui circule dans le transistor de référence est telle qu'on obtient un
coefficient de température approximativement égal à zéro pour le courant constant.
2. Un circuit intégré selon la revendication 1, dans lequel le transistor à effet
de champ de référence est un transistor à mode d'enrichissement.
3. Un circuit intégré selon la revendication 1 ou 2, comprenant au moins un transistor
à effet de champ d'un premier type de conductivité de canal, et au moins un transistor
ayant un type de conductivité de canal opposé au premier type.
4. Un circuit intégré selon la revendication 3, et formé sur un substrat semiconducteur
comprenant au moins une première région du premier type de conductivité dans laquelle
sont formés un ensemble de transistors à effet de champ, et une seconde région du
type de conductivité opposé dans laquelle est formé le transistor à effet de champ
de référence, cette seconde région étant isolée de la première région par une jonction
p-n.
5. Un circuit intégré selon la revendication 4, dans lequel la source du transistor
à effet de champ de référence est connectée électriquement à la région isolée.
6. Un circuit intégré selon l'une quelconque des revendications précédentes, dans
lequel l'électrode de grille arrière du transistor à effet de champ de référence est
connectée à une tension de référence.
7. Un circuit intégré selon l'une quelconque des revendications précédentes, dans
lequel la résistance de référence est formé par implantation d'un dopant à travers
une ouverture dans une couche de matière qui forme l'électrode de grille, grâce à
quoi la taille de la résistance de référence varie conformément à des variations de
processus de fabrication qui affectent également la taille de l'électrode de grille.
8. Un circuit intégré selon la revendication 7, dans lequel la matière précitée consiste
en silicium polycristallin.
9. Un circuit intégré selon l'une quelconque des revendications précédentes, dans
lequel les moyens destinés à faire circuler un courant de référence proportionnel
au courant de canal comprennent un circuit miroir de courant.