BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention relates to a photoelectric converting device having a photocharge
accumulating region whose potential is controlled through a capacitor.
Related Background Art
[0002] As a conventional photoelectric converting system, for example, there is the system
disclosed in the Official Gazette of EPC Application Laid-Open No. 0132076.
[0003] Fig. 1A is a schematic plan view of the conventional photoelectric converting device
disclosed in this Official Gazette and Fig. 1B is a cross sectional view taken along
the line I-I in Fig. lA.
[0004] In these diagrams, photosensor cells are formed and arranged on a substrate 101 like
a line. Each of the photosensor cells is electrically insulated from the adjacent
photosensor cells by an element isolating region 102.
[0005] Each photosensor cell has the following constitution.
[0006] An n epitaxial region (hereinafter, referred to as an n region) 103 is formed on
the substrate 101. A p region 104 and an n region 105 are formed on and over the n
region 103. The p region 104 and n region 105 serve as a base and an emitter of a
bipolar transistor, respectively.
[0007] An oxide film 106 is formed over the n region 103 formed with those respective regions
in this manner. A capacitor electrode 107 having a predetermined area is formed on
the oxide film 106. The capacitor electrode 107 faces the p region 104 through the
oxide film 106. A potential of the p region 104 in the floating state is controlled
by applying a pulse potential to the capacitor electrode 107. F
[0008] In addition, an emitter electrode 108 connected to the n region 105 is formed. An
electrode (not shown) to apply a potential to a collector of the bipolar transistor
through an n region having a high impurity concentration is formed on the back surface
of the substrate 101.
[0009] The fundamental operation will then be described. A light enters the p region 104
as the base of the bipolar transistor. The charges corresponding to the incident light
amount are accumulated into the p region 104 (accumulating operation). The base potential
is changed due to the charges accumulated. A current flowing between the emitter and
collector is controlled due to the potential change, so that an electrical signal
corresponding to the incident light amount can be obtained (reading operation). On
the other hand, to remove the charges accumulated in the p region 104, the emitter
electrode 108 is grounded and a pulse of a positive voltage is applied to the capacitor
electrode 107 (refreshing operation). By applying the positive voltage, the p region
104 is forwardly biased with respect to the n region 105 and the charges accumulated
are removed. Thereafter, the respective accumulating, reading, and refreshing operations
are repeated.
[0010] In other words, according to the system proposed in conventional device, the charges
generated due to the incident light are accumulated into the p region 104 as the base
and the current flowing between the emitter electrode 108 and the collector electrode
is controlled by the amount of accumulated charges. Therefore, after the accumulated
charges were amplified due to the amplifying function of each cell, they are read
out. Thus, the high power, high sensitivity, and further low noise can be accomplished.
[0011] A potential Vp generated in the base by the holes accumulated in the base due to
the light excitation is given by Q/C (namely, Vp = Q/C), wherein Q denotes an amount
of charges of the holes accumulated in the base and C is a capacitance connected to
the base. As will be apparent from this expression, in the case where elements are
highly integrated, both Q and C decrease together with the reduction in the cell size,
so that the potential Vp which is generated due to the light excitation is held almost
constant. Therefore, the system proposed in the conventional device is also advantageous
for the future high resolution.
[0012] However, according to the conventional photoelectric converting device, in the case
of applying the design rule of, e.g., 2 pm, for example, the contact portion on the
emitter region 105 is limited to 2 µm, so that the width of 10 pm or more is needed
per photo sensor cell. Therefore, in the case of arranging, e.g., 1000 cells in a
line, the length of photoelectric converting device itself reaches 10 mm. Such a large
device has the problems such that the yield deteriorates and the variation in characteristics
of the cells becomes large. In addition, the resolution is limited by the design rule
and it is difficult to accomplish the high resolution.
SUMMARY OF THE INVENTION
[0013] It is an object of the present invention to provide a photoelectric converting device
which can solve the problems in the conventional photoelectric converting device.
[0014] Another object of the invention is to provide a photoelectric converting device comprising
a plurality of photoelectric converting cells which are arranged and each of which
has: a semiconductor transistor consisting of two main electrode regions formed of
a semiconductor of one conductivity type and a control electrode region formed of
a semiconductor of the opposite conductivity type; and a capacitor to control a potential
of the control electrode region in the floating state, wherein each of the photoelectric
converting cells accumulates carriers generated dur to the incident light into the
control electrode region and controls an output by an accumulated voltage generated
due to the accumulated carriers by controlling the potential of the control electrode
region in the floating state through the capacitor, and each of the photoelectric
converting cells is composed of a first portion having a high photoelectric converting
efficiency and a second portion which is formed with at least an electrode of the
capacitor and an electrode of the other main electrode region, and a width of the
first portion is narrower than a width of the second portion and the first portion
is arranged like a line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015]
Fig. 1A is a schematic plan view of a conventional photoelectric converting device;
Fig. 1B is a cross sectional view taken along the line I-I in Fig. 1A;
Fig. 2A is a schematic plan view of the first embodiment of a photoelectric converting
device according to the present invention;
Fig. 2B is a cross sectional view taken along the line B-B in Fig. 2A;
Fig. 2C is a cross sectional view taken along the line C-C in Fig. 2A;
Fig. 2D is a cross sectional view taken along the line D-D in Fig. 2A;
Fig. 2E is a cross sectional view taken along the line E-E in Fig. 2A;
Figs. 3A to 3H are diagrams for explaining the manufacturing process of the embodiment;
Fig. 4 is a schematic plan view of the second embodiment of the invention; and
Fig. 5 is a schematic plan view of the third embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0016] An embodiment of the present invention will be described in detail hereinbelow with
reference to the drawings.
[0017] Fig. 2A is a schematic plan view of the first embodiment of a photoelectric converting
device according to the present invention. Fig. 2B is a cross sectional view taken
along the line B-B in Fig. 2A. Fig. 2C is a cross sectional view taken along the line
C-C in Fig. 2A. Fig. 2D is a cross sectional view taken along the line D-D in Fig.
2A. Fig. 2E is a cross sectional view taken along the line E-E in Fig. 2A.
[0018] In those diagrams, an n epitaxial layer 2 is formed on an n silicon substrate 1.
Photo sensor cells electrically insulated from one another by an element isolating
region 6 are arranged in the n epitaxial layer 2.
[0019] In this embodiment, the element isolating region 6 was formed by diffusing impurities.
However, the invention is not limited to this method. The element isolating region
6 may be also formed by the well-known techniques such as LOCOS method, method whereby
impurities are diffused under the oxide film by way of the LOCOS method, SEG (selective
epitaxial growth) method, bulk etching method, etc.
[0020] Each photosensor cell comprises:
A p base region 3 and an n emitter region 5 of a bipolar transistor which are formed
on and over the n epitaxial layer 2;
a polysilicon layer 4 for an electrode which serves as an electrode of a capacitor
to apply a pulse to the p base region 3 and an emitter electrode 7 connected to the
n emitter region 5, the polysilicon layer 4 and emitter electrode 7 being arranged
so as to sandwich an oxide film 13; and
an electrode 15 connected to the polysilicon layer 4 and a collector electrode (not
shown) to apply a potential to a collector of the bipolar transistor through an n
region (not shown) having a high impurity concentration, this collector electrode
being formed on the back surface of the substrate 1.
[0021] Further, an electrode section formed with the polysilicon layer 4 as the capacitor
electrode and with the emitter electrode 7 is covered by a light shielding layer 10.
The portion which is formed by the base region 3 and n epitaxial layer 2 and has a
width thinner than the electrode portion is a photo sensing section.
[0022] The device of this embodiment fundamentally operates in a manner as follows. First,
the p base region 3 biased to a negative potential is set to the floating state and
the holes in the pairs of electrons and holes generated due to the light excitation
are accumulated into the p base region 3 (accumulating operation). Subsequently, the
portion between the emitter and base is forwardly biased and the accumulated voltage
generated due `to the accumulated holes is read out to the emitter side in the floating
state (reading operation). On the other hand, by grounding the emitter side and applying
a pulse of a positive voltage to the polysilicon layer 4 as the capacitor electrode,
the holes accumulated in the p base region 3 are removed to the emitter side (refreshing
operation). After the accumulated holes were removed, the positive voltage pulse to
refresh trails. At this time, the p base region 3 becomes the initial state biased
to the negative potential.
[0023] The reasons why the electrode section is shielded by the light shielding layer 10
are as follows.
[0024] When the accumulating operation is performed without providing the light shielding
layer 10, the pairs of electrons and holes generated, for example, in the depletion
layer between the collector and base (between the n epitaxial layer 2 and the p base
region 3) by the incident light are attracted by the strong electric field and most
efficiently accumulated into the p base region 3 without being recombined. Thus, the
photoelectric converting efficiency of the photo sensing section is high.
[0025] On the other hand, although the holes generated in the emitter region 5 and element
isolating region 6 move to the base region 3 due to the concentration gradient, the
recombination ratio is high in the n impurities, so that the efficiency such that
the holes are accumulated into the base region 3 is low. On one hand, in the case
where the electrodes 7 and 15 are formed of metal of the aluminum system, if the thickness
is 3000 A or more, the transmission factor of the light becomes 1/10000 or less. The
light transmission factor of the polysilicon layer 4 is also low. Consequently, the
photoelectric converting efficiency of the portion just under the electrode is extremely
low.
[0026] Therefore, in this embodiment, as shown in Fig. lA, the electrode section having
a low photoelectric converting efficiency is provided at one end of the cell. The
photosensing section having a high photoelectric converting efficiency is formed so
as to have a width narrower than the electrode section. The cells constituted in this
manner are alternately arranged in a line, thereby remarkably improving the arrangement
density of the photosensing section. However, in such an arrangement, if the light
shielding layer 10 is not provided, an output from the electrode section of a low
arrangement density is added, so that not only the resolution of the photoelectric
converting device deteriorates but also the cells cannot be isolated. Thus, it is
inevitable that the electrode section is shielded against the light by the light shielding
layer 10.
[0027] Figs. 3A to 3H are diagrams for explaining the manufacturing process of this embodiment.
[0028] First, as shown.in Fig. 3A, an n layer 20 for ohmic contact having an impurity concentration
of 1 x 10
17 to 1 x 10
20 cm
-3 is formed on the back surface of the n-type silicon substrate 1 having an impurity
concentration of 1 x 10 to 5 x 10 cm
-3 due to the diffusion of P, As, or Sb. Then, an oxide film 21 (e.g., SiO
2 film) having a thickness of 3000 to 7000 A is formed under the n
+ layer 20 due to a CVD method.
[0029] The oxide film 21 is called back coat and serves to prevent the generation of the
impurity vapors when the substrate 1 is subjected to the heat treatment.
[0030] Next, the surface of the substrate 1 is etched for about one and half minutes at
a temperature of 1000°C under the condition of HCl of 2l/min and H
2 of 60 l/min. Thereafter, a source gas of SiH
2Cl
2 (100%) of 1.2 l/min and a doping gas (PH
3 diluted by H
2, 20 ppm) of 100 ml, for example, are poured and the n epitaxial layer 2 (hereinafter,
referred to as the n layer 2) is formed at a growth temperature of 1000°C and at reduced
pressures of 120 to 180 Torr. In this case, the growth speed of the monocrystal is
0.5 pm/min, the thickness is 2 to 10 pm, and the impurity concentration is 1 x 10
12 to 10
16 cm
-3, preferably, 10
12 to 10
14 cm
-3 (F
ig. 3
B).
[0031] To improve the quality of the n layer 2, the substrate is first subjected to the
heat treatment at temperatures of 1150 to 1250 °C to remove oxygen from the portion
near the surface of the substrate. Thereafter, a number of microdefects are generated
in the substrate due to the heat treatment for a long time at a temperature of about
800°C, thereby forming the substrate having the denuded zone such that the intrinsic
gettering can be carried out. This method is extremely effective to improve the quality
of the n layer 2.
[0032] Subsequently, an oxide film 22 for buffer having a thickness of 500 to 1500 A is
formed on the
n layer 2 due to the pyrogeneic oxidation (H
2 + O
2), wet oxidation (0
2 + H
20), steam oxidation (N
2 + H
2O), or dry oxidation. To further obtain a good oxide film having no stacking fault
or the like, it is proper to carry out the oxidation at a high pressure and at temperatures
of 800 to 1000°C.
[0033] The oxide film 22 is provided to prevent the channeling and surface fault when the
base region is formed due to an ion implantation method. By this process, the oxide
film 21 of the back coat is completely removed.
[0034] Next, a resist 23 is coated and the portions where the base region is formed are
selectively removed (Fig. 3C).
[0035] Subsequently, the B
+ ions or BF
2+ ions produced using BF
3 as a source gas are implanted into the wafer. The surface concentration is 1 x 10
15 to
5 x 10
18 cm
-3, preferably, 1 - 20 x 10
16 cm . The amount of ions which are implanted is
7 x 10
11 to
1 x 1015 cm
-2, preferably, 1 x 10
12 to
1 x 10
14 cm
-2.
[0036] After the ions were implanted in this manner, the resist 23 is removed. Then, the
p base region 3 is formed until a predetermined depth due to the thermal diffusion
at temperatures of 1000 to 1100 °C and in the N
2 gas. At the same time, an oxide film 24 is thickly formed over the surface of the
substrate 1. Subsequently, the oxide film 24 of the portions where the element isolating
region 6 is formed is selectively removed (Fig. 3D).
[0037] The depth of the p base region 3 is, for example, about 0.6 to 1 pm. However, this
depth and impurity .concentration are determined on the basis of the following idea.
[0038] To raise the sensitivity, it is desirable to reduce the impurity concentration of
the p base region 3 and thereby to decrease a capacitance Cbe between the base and
emitter. Cbe is nearly given by the following expression.

where, Vbi is a diffusion potential between the emitter and base and given by the
following expression.

where, ε is a dielectric constant of silicon crystal; N
D is an impurity concentration of the emitter; N
A an impurity concentration of the portion of the base adjacent to the emitter; n
i an intrinsic carrier concentration; Ae an area of the base region; k.a Boltzmann's
constant; T an absolute temperature; and q a unit charge amount. As N
A decreases, Cbe is reduced and the sensitivity increases. However, if N
A is set to be too small, the base region is completely depleted in the operating state
and becomes the punch through state. Therefore, N
A cannot be set to a very small value. It is preferable to set N
A so as to prevent that the base region is completely depleted and becomes the punch
through state.
[0039] As a method of forming the base region 3, there is also the method whereby BSG is
depositied on the wafer and impurities B are diffused until a predetermined depth
due to the thermal diffusion at temperatures of 1100 to 1200 °C.
[0040] Then, a diffusion which causes quality of n
+ is performed to form the element isolating region 6 in this case. The concentration
is preferably set to 10 to 10 cm
-3. As a method, there are the diffusion method from POCl
3 and ion implantation method. In this embodiment, the good results were derived by
the method using POCl
3. The conditions are such that the furnace temperature is 850 to 1000 °C, the carrier
gas for POCl
3 bubble is 50 to 200 ml/min, and the treatment time is 10 to 40 minutes.
[0041] After the element isolating region 6 and base region 3 were formed as described above,
a thick oxide film 9 is further formed over the substrate 1 due to the oxidation process.
Then, the oxide film 9 of the portion where the capacitor electrode and emitter region
are formed is selectively removed and the gate oxide film 13 having a thickness of
100 to 1000 A is formed (Fig. 3E).
[0042] Thereafter, polysilicon doped with As is deposited due to the CVD method by use of
the (N
2 + Si
H4 + AsH
3) or (H
2 + SiH
4 + AsH
3) gas. The deposition temperature is about 550 to 900 °C and the thickness is 2000
to 7000 A. It is also obviously possible to preliminarily deposit non-doped polysilicon
due to the CVD method and thereafter diffuse As or P. The polysilicon film deposited
in this way is partially etched and removed by the photolithography process, thereby
forming the polysilicon layer 4 as the capacitor electrode.
[0043] Subsequently, impurity ions of P, As, or the like are implanted through the oxide
film into the portion where the emitter region is formed due to the ion implantation
method. Then, the heat treatment is carried out to form the n emitter region 5 (Fig:
3F).
[0044] The emitter region 5 has been formed by the ion implantation method in this embodiment.
However, + the n emitter region 5 may be also formed by the following method. Namely,
the oxide film is removed and polysilicon is deposited onto the opening portions simultaneously
with the polysilicon layer 4. The impurities of P, As, or the like in polysilicon
are diffused into the p base region 3 due to the heat treatment, thereby forming the
n emitter region 5.
[0045] Next, a PSG film or SiO
2 film 8 having a thickness of 3000 to 7000 A is deposited due to the CVD method of
the foregoing gas system. Subsequently, contact holes are formed on the polysilicon
layer 4 and emitter region 5 due to the mask matching process and etching process.
The electrodes 7 and 15 (metal such as Al, Al-Si, At-Cu-Si, or the like) are formed
in the contact holes due to the vacuum evaporation method or sputtering method (Fig.
3G).
[0046] Next, an insulating film 12 between layers such as PSG film, SiO
2 film, or the like is deposited so as to have a thickness of 3000 to 9000 A due to
the CVD method. Moreover, the light shielding layer (e.g., Al or the like) 10 of a
thickness of 2800 to 0 5000 A is deposited and the portion of the photo sensing section
is etched and removed.
[0047] Then, a passivation film 11 (PSG film, Si
3N
4 film, or the like) is formed due to the CVD method and a collector electrode (metal
of Al, Al-Si, Au, or the like) is formed on the back surface of the wafer. In this
manner, the photoelectric converting device shown in Figs. 2A to 2E is formed.
[0048] Although the n semiconductor has been used for the element isolating region 6 in
the manufacturing process in this embodiment, the invention is not obviously limited
to this. In the case of a PNP bipolar + transistor, a p semiconductor may be used
or the elements may be isolated by an insulating material.
[0049] Fig. 4 is a schematic plan view of the second embodiment of the invention. As shown
in the diagram, the extent of the base region 3 in the photosensing section is smaller
than that in the first embodiment.
[0050] As set forth in the Official Gazette of EPC Application Laid-Open No. 0132076, in
the photoelectric converting device of such a system, in the case where a voltage
Vr is applied to the capacitor electrode 4, a variation in base potential is expressed
as follows.

where, Cox is a capacitance of the capacitor, Cbe is a capacitance between the base
and emitter, and Cbc is a capacitance between the base and collector. As will be understood
from this expression, it is desirable to set the capacitance Cbc of the deplation
layer between the base and collector to a small value in terms of an increase in output
voltage. Therefore, in this embodiment, the extent of the base region 3 is reduced.
However, the point with regard to a degree of extent of the base region 3 needs to
be determined in consideration of a capture efficiency of the carriers which are generated,
an output voltage, and the like.
[0051] Fig. 5 is a schematic plan view of the third embodiment of the invention. In the
first and second embodiments, the photosensor cells were arranged in a line and the
emitter electrode 7 and electrode 15 were alternately drawn from both sides of the
photosensing surface for each cell. However, as shown in Fig. 5, it is also possible
to use the constitution such that the electrode sections of the adjacent cells are
deviated to the front and back and the adjacent electrodes 7 and 15 and adjacent electrodes
7' and 15' are drawn from the same side.
[0052] However, in this embodiment, the n layer 2 as the photosensing section of the cell
locating backward and the n layer 2 of the electrode section are connected by a wiring
16. The photosensing section consists of only the n layer 2 and the base region 3
is formed in the electrode section.
[0053] In the shape of the cell shown in Fig. 5, the electrodes may be obviously drawn from
both sides for every cell.
[0054] -As described in detail above, in the photoelectric converting device according to
the embodiments, the dimensions of the device can be reduced without being limited
by the design rule and a high resolution can be easily attained. For example, even
in the case of using the design rule of 2 pm as well, according to the invention,
the width of cell can be reduced to 5pm from 10 pm in the conventional device. Even
if 1000 elements are arranged as well, the length of the photoelectric converting
device itself can be set to 5 mm without deteriorating the photoelectric converting
characteristic.