| (19) |
 |
|
(11) |
EP 0 206 576 A3 |
| (12) |
EUROPEAN PATENT APPLICATION |
| (88) |
Date of publication A3: |
|
28.09.1988 Bulletin 1988/39 |
| (43) |
Date of publication A2: |
|
30.12.1986 Bulletin 1986/52 |
| (22) |
Date of filing: 04.06.1986 |
|
|
| (84) |
Designated Contracting States: |
|
BE FR IT NL |
| (30) |
Priority: |
12.06.1985 GB 8514924
|
| (71) |
Applicant: STC PLC |
|
() |
|
| (72) |
Inventor: |
|
- Waller, David Leonard 'Cyreve'
()
|
|
| |
|
| (54) |
Improvements in semiconductor memories |
(57) A bit-line load for a static random access memory incorporates a load comprising
a diode, and current limiting means in series with the diode, the diode/limiter assembly
being shunted by a current source. This overcomes both the V
dd drop problem and the high write cycle current flow experienced with conventional
bit line loads.