(19)
(11) EP 0 228 958 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
21.03.1990 Bulletin 1990/12

(43) Date of publication A2:
15.07.1987 Bulletin 1987/29

(21) Application number: 86402852.7

(22) Date of filing: 18.12.1986
(51) International Patent Classification (IPC)4: G11C 7/00, G11C 8/00
(84) Designated Contracting States:
DE FR GB

(30) Priority: 18.12.1985 JP 282736/85
19.12.1985 JP 284406/85

(71) Applicant: FUJITSU LIMITED
Kawasaki-shi, Kanagawa 211 (JP)

(72) Inventors:
  • Koshizuka, Atuo c/o Seiwa-so
    Kawasaki-shi Kanagawa 212 (JP)
  • Furumochi, Kazuto
    Midori-ku Yokohama-shi Kanagawa 227 (JP)

(74) Representative: Descourtieux, Philippe et al
Cabinet Beau de Loménie 158, rue de l'Université
75340 Paris Cédex 07
75340 Paris Cédex 07 (FR)


(56) References cited: : 
   
       


    (54) Semiconductor memory device with reset signal generating circuit


    (57) A semiconductor memory device includes reset means for equalizing potentials of a pair of signal lines for transferring a complementary signals; a clock generating circuit (32,33) generating a first clock signal (CTC) and a second clock signal (ATC) at a time different from the generation of the first clock; and a logical OR gate circuit (38) generating a reset signal (ϕ) based on the first and second clock signals.
    When the pulse with of an active low chip selection signal (cs) is shorter than a predetermined time period, the pulse width of the reset signal ((p) is made longer than that generated when the pulse width of the signal (cs) is longer than the predetermined time period. As a result, the potentials of a pair of complementary bit lines connected to each cell in the memory cell array (39) can be reliably reset, and the delay time in the access operation can be reduced.






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