(19)
(11) EP 0 241 288 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
08.02.1989 Bulletin 1989/06

(43) Date of publication A2:
14.10.1987 Bulletin 1987/42

(21) Application number: 87303096.9

(22) Date of filing: 09.04.1987
(51) International Patent Classification (IPC)4: G09G 1/16, G06F 13/28
(84) Designated Contracting States:
BE DE ES FR IT NL SE

(30) Priority: 10.04.1986 GB 8608776

(71) Applicant: AMSTRAD PUBLIC LIMITED COMPANY
Brentwood, Essex CM 14 4EF (GB)

(72) Inventor:
  • Mathieson, John Flare Technology
    Cambridge CB1 4DH (GB)

(74) Representative: Abnett, Richard Charles et al
REDDIE & GROSE 16 Theobalds Road
London WC1X 8PL
London WC1X 8PL (GB)


(56) References cited: : 
   
       


    (54) Microprocessor video display system


    (57) In a microprocessor video display system a pixel-mapped video memory (10) can be accessed both by the CPU (12) and by video display logic (14) which delivers video data to the display. Contrary to accepted practice, contention between simultaneous access requests from the CPU and video display logic is avoided by the video display logic deferring its access request for one video memory access period. This is acceptable because: the video control logic can access data at a rate twice that required by the display, the video memory access cycle rate is the same as the CPU clock rate, and the microprocessor accesses the memory for one clock period during operation cycles lasting three orfourclock pulses. The CPU operation is thus kept at its maximum speed without the video data being adversely delayed.






    Search report