(19)
(11) EP 0 244 366 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
07.01.1988 Bulletin 1988/01

(43) Date of publication A2:
04.11.1987 Bulletin 1987/45

(21) Application number: 87830063

(22) Date of filing: 23.02.1987
(84) Designated Contracting States:
DE FR GB NL SE

(30) Priority: 06.03.1986 IT 8360886

(71) Applicant: SGS MICROELETTRONICA S.p.A.
 ()

(72) Inventors:
  • Contiero, Claudio
     ()
  • Andreini, Antonio
     ()
  • Galbiati, Paola
     ()

   


(54) Self-aligned process for fabricating small size DMOS cells and MOS devices obtained by means of said process


(57) Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-­alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment tech­nique, further simplifying the process.







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