(19)
(11) EP 0 244 991 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
18.10.1989 Bulletin 1989/42

(43) Date of publication A2:
11.11.1987 Bulletin 1987/46

(21) Application number: 87303608.1

(22) Date of filing: 24.04.1987
(51) International Patent Classification (IPC)4: G09G 1/00
(84) Designated Contracting States:
BE DE FR GB NL SE

(30) Priority: 03.05.1986 GB 8610888

(71) Applicant: AMT(HOLDINGS) LIMITED
Reading Berkshire RG6 1AZ (GB)

(72) Inventor:
  • Humpleman, Richard James
    Talke Stoke-on-Trent (GB)

(74) Representative: Rackham, Stephen Neil et al
GILL JENNINGS & EVERY, Broadgate House, 7 Eldon Street
London EC2M 7LH
London EC2M 7LH (GB)


(56) References cited: : 
   
       


    (54) Variable delay circuit


    (57) A data processing system is described comprising a display terminal (10) and a processing unit (11). The display terminal includes a video timing generator (14) producing synchronisation signals (VSYNC, HSYNC). This triggers requests (QUAL) for the processing unit to supply video data. The display terminal includes a variable delay circuit (24) which measures the time delay between the outgoing request and the incoming data, and causes the synchronisation signals to be delayed by a corresponding amount. This ensures that the synchronisation signals are maintained in the correct timing relationship with the video data, irrespective of any unknown delays between the display terminal and the processing unit.







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