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(11) | EP 0 261 256 A1 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Display controller circuit |
| (57) A display controller is equipped with a video information storage medium containing
at least two video objects, the storage medium being of type that allows to read out
information related to the different video objects in parallel, an atrribute logic
generating enable signals, a combination logic combining the outputs of said video
inform ation storage medium and the enable signals
and a controller unit, preferably a CPU and/or a video controller. This display controller
is able to produce an overlay of the various stored video objects thereby offering
the opportunity to switch the single objects partially on or off. |
[0001] The present invention relates to a display controller circuit for the generation of a video signal.
[0002] To control a video display unit, for example the beam of a CRT, a video signal has to be provided this video signal representing the information to be displayed, for example the "pixel on/off" information or a color information. Such video signals are usually, for example in the case of a raster display, composed of video information, this video information being stored in an electronic memory such as a random acces memory (RAM). For each pixel of the display, this electronic memory contains a specific information.
[0003] The information contained in this electronic memory is used to compose the video signal. For this purpose, the information contained in the memory in parallel form has to be processed to form a serial bit-stream. This is usually done by the use of shift registers which can be separate components or which can be integrated on the RAM chip.
[0004] Address generation for these video RAMs (ramdom access memory to store the picture information) and generation of the additional video control signals (for example, the horizontal synchronization pulse, the vertical synchronization pulse or the blank signal) is usually performed by a video controller being preferably a special integrated circuit. Therefore, generation of the video signal is basically processed under control of the video controller.
[0005] In some practical applications, it is necessary that various information generated separately is displayed on the screen in specific areas hereinafter called "windows". The complete display is composed of several "windows". For example, this is the case in some medical applications where various waveforms such as the electrocardiogram (ECG) or respiration, various trends such as heart rate, temperature or the like have to be displayed as well as some alphanumerics. All of this information is generated and updated separately. Of course, it is possible to build a complete view on the screen by storing said information in the video RAMs. Nevertheless, this method has several disadvantages: Any time a specific information has to be altered, the information previously stored in the related memory cells must be destroyed and therefore is no longer available for further operation. A very drastic example is a medical monitor showing, for example, the heart rate trend in one window. Whenever the user wants to replace the heart rate by, let us say, temperature, the heart rate information is overridden, therefore destroyed and no longer available if the user wants to see it again. Of course, this disadvantage can be overcome by the use of "back-up" memories, but this method would be very time-comsuming and expensive.
[0006] Another disadvantage of this method is that some time is required to override information in the video RAMs (primarily caused by the limited access time of the host computer to the video RAMs as most of the available time these RAMs must be accessable by the video controller for the purpose of video signal generation), and therefore new information can not be displayed like lightning but some time is required to build the new "window".
[0007] A known attempt to solve the problems outlined above is to organize the various "window" objects in specific RAM locations and to assign appropriate pointers to each of them. The complete video view can then be combined by a special video controller, i.e. a video controller with special capabilities. This video controller uses the pointers describing position and size of each "window" object to build the whole video view whilst generating the video signal. This implies that a list or a list-like data structure has to be processed prior to the display of a line on the screen, i.e. a display consisting of N lines will require N list processings.
[0008] It is reasonable tha t also this attempt to solve the outlined problems has various disadvantages. A special video controller is required the cost of which exceeds those of a usual video controller. Besides that, the procedure (list processing algorithm) to build up the complete view is rather complicated as well as time-critical. This results in a limited refresh rate of the whole system. Moreover, the video controller needs a lot of time for access to the pointer table and to the video RAMs. The video RAM locations to be accessed are not predictable, and this complicates the access mechanisms between the video controller and the sources of new video information; it also complicates arbitration of the video RAM. In a system using such a video controller such as the 82716/VSDD controller of Matra-Harris, more than 90% of the possible access time to the RAMs is needed for video controller access.
[0009] It is a major objective of the present invention to propose an improved display controller circuit which is able to combine various video objects to a complete video view but does not require a specialized video controller.
[0010] According to the invention, this problem can be solved by a combination of the following features:
a) the video information storage medium is of a type that allows to read out the information related to different video objects in parallel, thus forming various video information read-outs, each of these read-outs representing a video object,
b) an attribute logic generating at least one enable signal,
c) at least one controller unit controlling said video information storage medium and said attribute logic and
d) a combination logic combining said video information read-outs to a video signal in dependence on the enable signal generated by said attribute logic.
[0011] A video object in the above sense is a specific object such as a graphic element, a graph or some alphanumerics which may or may not cover the whole screen. In most applications it will only cover part of the whole screen. Several of these video objects are combined to a complete video view.
[0012] In a display controller unit according to the invention, each video object is represented by a "page" - or part of a page (in which case the page contains several video objects) - in the video information storage medium, for example random access memory/memories. Such a page corresponds to a video view covering the whole or part of the screen. The complete and final screen display is built by an "overlay" of the various pages as will be explained in detail below.
[0013] In a typical application, the video information storage medium consists of various RAM "pages" each of these pages corresponding to a specific pixel plane covering part of the CRT screen or the whole screen and representing one or more specific video objects. The output of these RAMs is loaded in appropriate shift registers with serial output. Therefore, for each page a serial bit stream is created these bit streams each representing a complete video view (or possibly a well-defined part of a video view). The serial bit streams of all objects are clocked out from the shift registers simultaneously (in parallel) thus forming N video signals from N objects/pages.
[0014] These video information read-outs are transmitted to a combination logic. THe combination logic also receives at least one enable signal generated by an attribute logic under control of a controller unit (for example, the host computer or the video controller). The enable signal(s) is/are used to control transmission of the various video information read-outs to the video output. The combination logic can - in simple words - be described as a "black box" having N inputs for N video objects/pages, at least one control input (the enable signal) and at least one output being the video signal. The combination logic is used to transmit one (or, if this is wanted, more than one) of the video informat ion read-outs to the output, i.e. the video output.
[0015] Of course, the combination logic can also process the non-serialized data and serialization can be performed after the signals have passed the combination logic.
[0016] In a very simple case, the attribute logic creates only one enable signal used to control two video information read-outs. If the enable signal has a specific value, the first read-out is transmitted to the output, whereas, if the enable signal has another value, the other read-out is transmitted. Of course, this is a very simple example and in practical applications, a more complex combination logic could be required.
[0017] It is understood that the video information storage medium can also be represented by other devices (for example, by a single RAM the output of which is alternatively stored into shift registers each of these registers creating a serial bit stream which represents a complete video object). The same is true for the combination logic and for the controller unit (this controller unit cannot only be the host CPU or the video controller but, for example, also a special hardware like a DMA controller).
[0018] The various video objects can also be of different types; for example, these can be alphanumerics, waves or other graphs or even pictures. The system may also include a character generator, but this is not essential.
[0019] The enable signal(s) generated by the attribute logic can be controlled by the controller unit in different manner. For example, each pixel of all pages could be individually enabled or disabled. Nevertheless, this would require a large attribute RAM (explained below) and processing capability for attribute manipulations.
[0020] In a preferred embodiment, the enable signals are therefore generated dependent on "cells" consisting of one or more pixels in both the horizontal and vertical direction. A cell is defined as a small part of the whole screen, and such a cell (which could have, for example, approximately the size of a character) can only be "switched on/off" by the enable signals as a whole.
[0021] In another preferred embodiment, the attribute logic generates a specific enable signal for every video information read-out. This simplifies the assignment between such a read-out and the related enable signal and especially results in an easy access to the various read-outs. The attribute logic may also generate other attributes like "half/full intensity", "inverse" or "blink". These attributes can also be processed by the combination logic in an appropriate manner.
[0022] According to a preferred embodiment of the invention, the combination logic combines the video information read-outs with the associated enable signals in a circuit of substantially AND-like function. Such an AND-like function can, for example, be realized in discrete hardware components, in a programmable logic array (as integrated circuit) or by gates with an AND-like function. It is understood that such a gate could be an AND gate with the video information read-out at one of its inputs and the associated enable signal at the other input. Nevertheless, the gate must not necessarily be an AND gate; for example, it could also be a NAND gate or, if inverse logic is used, an OR gate or a NOR gate.
[0023] Preferably the outputs of these AND-like function circuits are combined in an OR-like function circuit the output of which being the video signal. Of course, this OR function must also not necessarily been realized in the form of an OR gate; depending on the logic used, it could also be a gate of another type as outlined above, a function realized in discrete hardware or the like.
[0024] The AND-like gates receiving the enable signals and the video information read-outs can also receive other attribute signals at their inputs.
[0025] The attribute logic itself is - in a very simple realization - a buffer loaded by the host computer or the video controller the outputs of said buffer bei ng the various attribute signals. In a more sophisticated embodiment, the attribute logic consists of a random access memory being under control of the controller unit; the output of said random acces memory preferably is buffered.
[0026] Using a random access memory has the advantage of reducing CPU time. The controller unit (microprocessor, video controller or the like) must only load this random access memory with the attributes for the whole video display once, and in the following it has only to generate the appropriate addresses for this RAM.
[0027] The invention offers hardware support for up to N time M separate windows, N being the number of video RAM pages and M the number of "cells". Up to N windows may overlap and still be individually controllable only by manipulating attribute information.
[0028] Another advantage is that fast enabling and disabling of the windows is possible, i.e. the displayed information can be rapidly switched over. The information of the individual pages is not destroyed during such an operation.
[0029] A very important feature of the present invention is that the count of video objects/pages which can be combined to a complete video view is nor hardware-limited. Of coures, the attribute logic and the combination logic can only be designed for a certain limited number of pages; nevertheless, cascading of multiple display controller circuits of the type described herein is possible if the combination logic also receives a signal of an external display controller circuit. In this case, the signal of the external display controller(s) is also processed by the combination logic, therefore generating a video view being combined of pages of a basically not limited counted. Preferably the attribute logic also generates an enable signal for the signal received from the external display controller circuit, both of these signals being processed in the combination logic; using this additional enable signal, the controller unit can switch on/off the externally received signal.
[0030] The present invention therefore provides a display controller circuit which can combine various video objects/pages to a complete video signal in a way that ensures a high refresh rate and that offers the use of an ordinary video controller to combine video objects.
[0031] In the accompanying drawings, a preferred embodiment of the present invention is shown. Additional features and advantages of the invention arises from the following description in which these drawings are explained.
[0032] In the drawings,
Fig. 1 shows a video controller according to the state of the art which is able to combine various video objects to a complete video view,
Fig. 2 is a schematical representation of a circuit according to the present invention,
Fig. 3 shows details of the combination logic,
Fig. 4 is a detailed diagram of a complete display controller circuit,
Figs. 5a-5c show examples of display controller cascading and
Figs. 6a-6d show an example of the operation of the display controller.
[0033] Fig. 1 shows a display controller circuit according to the state of the art. A microprocessor 1 controls a video controller 2 which is of a type like the 82716/VSDD Matra Harris controller. This video controller is - for the purpose of combining the various video objects to a complete video view - a special controller chip. Box 3 indicates a memory block, in this case a set of RAM (ramdom access memory) chips. This memory block is logically - and possibly even physically - divided in some object areas 01 to 03 each of these areas containing a specific object to be shown on the screen. These objects could, for example, be graphic objects like the house in object 01 or the tree in object 02, but also alphanumerics like the word "COUNTRYSIDE" in object 03 or the like. Besides these object areas, memory block 3 contains a set of pointers called object description table 4. This object description table contains all information related to the various objects, for example, information about their position in the RAM memory or information about their final position on the screen. When generating the video signal, video controller 2 has permanently to look up objecct description table 4 to place the various objects at their correction position on the screen. This look-up method must be performed on a line basis, e.g., for any line on the video screen the video controller has to chek the object description table for objects which affected that line.
[0034] The complete video signal is transmitted on line 5 to display 6 which shows the various objects.
[0035] It is obvious that such a video controller is rather complicated in its hardware structure (and, of course, rather expensive). Besides that, the number of objects which can be combined is limted. The video controller needs a lot of the total available time for access to the RAM, either to the object description table or the object locations themselves. In known systems, this access needs more than 90 % of the time totally available. Therefore, the microprocessor itself has nearly no time for access to the RAMs. This is the reason why, according to the circuit of Fig. 1, the processor has no direct access to the RAMs but only via the video controller. This is also a reason for the limited possible refresh rate of the whole system.
[0036] Fig. 2 shows an overall block diagram of a display controller circuit according to the present invention. Memory block 7 contains video information of various video objects in specific locations 7a, 7b and 7c. Each of these video objects represents a complete pixel map (i.e., a bit map) of the whole raster display screen called "page" hereinafter. In practical applications, a resolution of 1.024 × 512 pixels is adequate for alphanumerics, whereas for waves or geometric bodies a higher reolution would be necessary. Therefore, each of memory locations 7a to 7c could be used to generate a video signal for the complete screen. Of course, this is not necessary; each of memory locations 7a to 7c could also be related only to a specific, eventually predefined area on the screen.
[0037] Memory 7 is under control of a controller unit 8 which might, for example, be a central processing unit (CPU), a video controller (VC) or a combination of both of these. This controller unit has access to memory 7 to store new display information and to control operation of this memory. Controller unit 8 also controls a block 9 generally depicted as attribute logic. This attribute logic generates enable signals which are transmitted on line 10 to a combination logic 11. The latter does not only receive the enable signals but also the video information read-outs (preferably serialized)on lines 12a to 12c. On each of these lines, a serial signal representing the assigned video object/page is present, and read-outs on lines 12a to 12c occur in parallel. Therefore, combination logic 11 receives simultaneously signals from each video object/page and the associated enable signals. The enable signals provide the combination logic with the necessary information to select a specific (or even more than one) page. The combination logic generates the video signal ("Video Out") on line 13.
[0038] It is understood that the number of memory blocks in memory 7 can vary; these blocks could even be defined dynamically.
[0039] Fig. 3 shows a very simple possible realization of the combination logic. Controller unit 8 is the same as outline in Fig. 2. Reference numerals 15a to 15c represent the video RAM pages. The serial outputs (video information read-outs) of video RAM pages 15a to 15c are each passed to one of AND gates 18a to 18c on lines 19a to 19c. Attribute logic 9 generates an enable signal for each of these video read-outs; these enable signals are transmitted on lines 20a to 20c to AND gates 18a to 18c.
[0040] By the enable signals transmitted on lines 2 0a to 20c, the appropriate video information read-out can be switched on/off under control of controller unit 8. An additional AND gate 21 is used to switch an external signal ("EXT IN") on line 22 on or off. For this purpose, attribute logic 9 generates an additional enable signal on line 23. By using an external signal, cascading of display controllers becomes possible (as will be explained later).
[0041] The outputs of AND gates 18a to 18c and 21 are passed to an OR gate 24 generating the video signal "Video Out" on line 13.
[0042] Fig. 4 shows a detailed diagram of the whole system. Operation is performed under control of a microprocessor 25 which communicates with other hardware via interface 26. This microprocessor is equipped with typical microprocessor components such as ROM 27, RAM 28 and the like.
[0043] Microprocessor 25 communicates with a video controller 29 via a bus connection 32. This video controller generates video control signals like horizontal or vertical synchronizatiuon signals as generally indicated by lines 30. These video controller signals are not subject of the present invention, and their definition and generation is well known in the art; so they will not be described in detail here.
[0044] Microprocessor 25 as well as video controller 29 have access to three video RAM pages 31a to 31c each of these video RAM pages containing a pixel map of a whole screen; each of them could therefore be used to generate a complete video signal. In the shown example, for the purposes of a medical monitor video RAM page 31a contains wave information (such as ECG or respiration) with a resolution of 2.048 × 512 pixels, whereas video RAM pages 31b and 31c contain alphanumerics and graphics information with a resolution of 1024 × 512 pixels. Video controller 29 controls read-out of the video RAM pages and enables microprocessor 25 to access these RAM pages on lines 32.
[0045] Video RAM pages 31a to 31c can be read out on lines 33a to 33c each of these lines representing a parallel output. Therefore, lines 33a to 33c each represent a plurality of lines. Shift registers 34a to 34c convert the parallel output of the video RAM pages into serial form. Instead of using RAMs and shift registers it is also possible to use RAMs with integrated shift registers.
[0046] The video information read-out of shift registers 34a to 34c is transmitted via lines 35a to 35c to NAND gates 36a to 36c. On each of lines 35a to 35c, a complete video signal is transmitted, line 35a -in this case - representing a wave signal whereas lines 35b and 35c represent alphanumeric and/or graphic information.
[0047] NAND gates 36a to 36c also receive enable signals: The "enable wave" signal on line 37a, the "enable alpha/graphics 1" signal on line 37b and the "enable alpha/graphics 2" signal on line 37c. These enable signals are generated under control of microprocessor 25. The processor has access to an attribute RAM 38 to store appropriate enable signals (and also other attribute signals) in advance. Address generation for attribute RAM 38 is performed by the video controller in address generation section 39 and transmitted to RAM 38 on line 40. Address generation section 39 of video controller 29 also generates appropriate addresses for video RAM pages 31a to 31c (bus 41). Therefore, synchronization between video RAM page address generation and attribute RAM address generation is ensured; consequently, video information read-outs and enable signals are also synchronized.
[0048] In the present example, the attribute signals do not have a resolution of 1 pixel; the concept uses so-called "character cells", i.e. only specific blocks of the diplay called "character cells" can be influenced as a whole. Character cells of a specific video information read-out can be switched on or off or can be assigned other attributes such as half intensity, blink inverse or the like, but no higher resolution van be obtained. This concept is memory- and time saving and can ne vertheless be accepted as in practice, the attributes must only influence a character as a whole, whereas waves or other graphic representations do not need high attribute resolution.
[0049] The output of RAM 38 is transmitted via line 42 (which represents a multiplicity of lines) to buffer 43.
[0050] NAND gates 36a to 36c combine the video information read-outs and the approprite enable signals performing an AND functon with an inversion at the output. For example, if the "enable wave "signal on line 37a is "0", then output 44a of gate 36a is held constant at "1", whereas, if the "enable wave" signal is "1", the signal present on line 44a is the inverted "wave" signal of line 35a. The enable signal can be regarded as an "on/off" indication. It is therefore very easy to assign a video information read-out to a specific area on the screen; for example, if the "wave" signal shall appear in the upper left corner of the screen, the enable signal is only "1" if the beam passes this region.
[0051] NAND gates 36b and 36c also receive other attributes, in this case a blink signal. These signals can be used to switch a character cell on and off intermittently thus realizing a blink function. For this purpose, attribute RAM 38 generates two blink enable signals on lines 45a and 45b which are labeled as "Blink 1" and "Blink 2" in Fig. 4. These blink enable signals are ORed in OR gates 46a and 46b with a "blink clock" signal received on line 47 and generated by a hardware oscillator or by software. The "Blink 1" and "Blink 2" signals have inverted logic. Therefore, if, for example, the "Blink 1" signal is held at positive potential (logical "1"), the output of OR gate 46a is permanently "1" and therefore does not influence the signal passing NAND gate 36b. On the other hand, if the "Blink 1" signal is "0", the output of gate 46a alternates following the "blink clock" signal and therefore switches the output of NAND gate 36b intermittently on and off. The same is true for the second signal path from line 45b to gate 36c.
[0052] Outputs 44a-44c of NAND gates 36a to 36c are connected with the inputs of an additional NAND gate 75. Because the signals received by this gate have inverted logic, gate 75 implements an OR function. The output of gate 75 is a signal which combines the video information read-outs to a complete video signal; the video information read-outs are only transmitted in the areas defined by the enable signals. The output of gate 75 labeled as "EXT Video OUT" (line 48) is used as an external input for other display controller circuits. The meaning of the external video out signal will be outlined below.
[0053] For the purpose of cascading, an additional NAND gate 49 receives an "external in" (EXT IN) signal on line 50. This is a video signal generated by an external display controller. At the other input, NAND gate 49 receives an "Enable External" signal generated by attribute RAM 38 on line 51. Gate 49 therefore implements an "AND" function with an inversion at the output. If the "Enable External" attribute signal has positive potential, gate 49 transmits the "external in" signal with inverted logic.
[0054] The output of gate 49 is transmitted on line 52 to the input of a NAND gate 53. This gate also receives the inverted "EXT Video OUT" signal of line 48. Inversion is performed by inverter 54. In consideration of the inverted logic of the signal received on line 52 and of the output of inverter 54 received on line 55, NAND gate 53 implements an OR function with respect to the original signals. Therefore, the "VIDEO OUT" signal - the generated video signal - on line 56 is a combination of the video signals generated internally and of the externally received signal (if the external signal is enabled).
[0055] Figs. 5a to 5c show various examples of cascading of display controller circuits according to the invention using the EXT IN inputs and the EXT Video OUT and VIDEO OUT outputs.
[0056] According to Fig. 5a, a first display controller circuit is generally outlined by numeral 65. The EXT Video OUT output of this circuit is connected (as indicated by 67) with the EXT IN input of a second display controller circuit 66. In such a combination, the video signals generated by thge first and second display controller circuits can be obtained in the form of an "overlay" at output VIDEO OUT of the second display controller circuit 66 (at output EXT Video OUT of circuit 66 only the signals generated internally by this circuit are present).
[0057] Another example for the cascading of display controllers is shown in Fig. 5b. Output EXT Video OUT of a first display controller 68 is connected with the EXT IN input of a second display controller 69. VIDEO OUT output of controller 69 therefore transmits the display information (i.e., the pages) of both the controllers 68 and 69. VIDEO OUT output of controller 69 is connected with the EXT IN input of a third display controller 70. Output VIDEO OUT of this third controller therefore provides all of the information generated by the first, the second and the third display controller (EXT Video OUT outputs of controllers 69 and 70 are not used in this case as these outputs transmit only information generated by the related display controllers themselves and not the signals received at their inputs).
[0058] Fig. 5c is an example for driving multiple CRTs with display controller circuits according to the invention. EXT Video OUT output of a first display controller 71 is connected with the EXT IN input of a second display controller 72 the VIDEO OUT output of which is used as video signal for a CRT 73. As VIDEO OUT of controller 72 provides the signals generated by both display controllers, CRT 73 shows an "overlay" of the view generated by these controllers.
[0059] In similar manner, EXT Video OUT output of controller 72 is connected with the EXT IN input of controller 71 whose VIDEO OUT output drives a second CRT 74 also showing all of the information generated by both display controllers.
[0060] Figs. 6a to 6d show various displays in order to further explain display controller operation. The shown displays relate to a medical monitor which measures and displays the electrocardiogram (ECG) and the respiration (RESP) of a patient.
[0061] Fig. 6a shows a screen 57 wherein two waves, the ECG 58 and respiration 59 are displayed. A representation of these waves could, for example, be stored in wave video RAM page 31a (cf. Fig. 4). The display of Fig. 6a exists only as a representation in the associated wave RAM page; in the shown example, it is not displayed in this form (but, of course, it could be displayed if appropiate enable signals were generated).
[0062] Figs. 6b and 6c show corresponding alphanumerics displays stored in alpha graphics video RAM pages 31b and 31c. With reference to Fig. 6b, there is shown the label "ECG" (reference no. 60) and the current pulse rate (reference no. 61). Referring to Fig. 6c, there is shown the label "RESP" (reference no. 62) and the current respiration rate (reference no. 63). These alphanumerics displays are also not shown to the user but have their representation in the alphanumeric/graphic RAM page.
[0063] Fig. 6d shows operation of the display controller according to the present invention. This display is a combination of the displays of Figs. 6a to 6c. This combination is performed by the combination logic under control of the attribute logic. The output of alphanumeric/graphic RAM pages 31b and 31c is enabled over the whole screen area (the signals on enable lines 37 and 37c, cf. Fig. 4, are permanently "1"), whereas the output of wave RAM page 31a is only enabled via enable line 37a when the beam passes screen area 64. Therefore, the right part of the wave representation is cut off which can be seen in comparison with Fig. 6a.
1. Display controller circuit for the generation of a video signal, said video signal
containing the video information of a video display being composed of at least two
video objects, characterized in that said display controller circuit comprises:
(a) a video informatiuon storage medium (7;15a,15b,15c;31a,31b, 31c) of a type that allows to read out the information related to the different video objects in parallel thus forming various video information read-outs (12a,12b,12c;19a,19b,19c;35a,35b,35c), each of these read-out (12a,12b,12c;35a,35b,35c) representing a video object,
(b) an attribute logic (9;38,43) generating at least one enable signal (20a,20b,20c;37a,37b,37c),
(c) at least one controller unit (8;25,29), preferably a CPU and/or a video controller, said controller unit (8;25,29) controlling said video information storage medium (7;15a,15b,15c;31a,31b,31c) and said attribute logic (9;38,43),
(d) a combination logic (11) combining said video information read-outs (12a,12b,12c;19a,19b,19c;35a,35,35c) to a video signal (13;56) in dependence on the enable signal (20a,20b,20c;37a,37b,37c) generated by said attribute logic (9;38,43)
2. Display controller circuit according to claim 1, characterized in that each of
said video information read-outs (12a,12b,12c;19a,19b,19c;35a,35b, 35c) represents
a whole video display.
3. Display controller circuit according to claim 1 or 2, characterized in that the
attribute logic (9;38,43) generates and the combination logic (11) processes a specific
enable signal (20a;20b,20c;37a,37b,37c) for every video information read-out (12a,12b,12c;19a,19b,19c;35a,35b,35c)
related to a certain video object.
4. Display controller circuit according to at least one of the preceding claims, characterized
in that the combination logic (11) combines the video information read-outs (12a,12b,12c;19a,19b,19c;35a,35b,35c)
with the associated enable signals (20a,20b,20c;37a,37b,37c) in a circuit of substantially
AND-like function, preferably AND-like gates (18a,18b,18c;36a,36b,36c).
5. Display controller circuit according to claim 4, characterized in that the combination
logic (11) combines at least two of the outputs of said AND-like function circuits
in an OR-like function circuit, preferably an OR-like gate (24;75).
6. Display controller circuit according to at least one of the preceding claims, characterized
in that the attribute logic (9;38, 43) generates and the combination logic (11) processes
additional attribute signals, in particular blink signals and/or "half/full intensity"
signals.
7. Display controller circuit according to at least one of the preceding claims, characterized
in that the attribute logic (9;38, 43) consists of a random access memory (38) being
under control of said controller unit (8;25,29), the output of said random access
memory (38) preferably being buffered.
8. Display controller circuit according to at least one of the preceding claims, characterized
in that said combination logic (11) also receives a signal (EXT IN) of an external
display controller circuit for the purpose of cascading.
9. Display controller circuit according to claim 8, characterized in that said attribute
logic (9;38,43) also generates an enable signal (51) for the signal received from
the external display controller circuit (EXT IN) both of these signals being processed
in the combination logic (11).