[0001] The present invention relates to a display controller for data processing apparatus,
of the type set forth in the preamble of claim 1.
[0002] Normally display controllers the above-mentioned type comprise a display refresh
memory which can be recorded with the codes for alpha-numeric characters or in accordance
with a map of pixels or graphic dots. In a series of computers for personal use, which
are capable of being controlled by programs which are standard in the industry, the
refresh memory has a capacity for map recording dots equal to the dots which can be
displayed on the display, but it is not possible for it simultaneously to record alpha-numeric
codes and graphic pixels. In such displays, if different portions of images are to
be displayed on the video unit and in particular if an alpha-numeric window together
with a graphic image is to be displayed, the characters in such window must first
be recorded as a map of dots in the refresh memory.
[0003] An alpha-numeric display controller has been proposed, which is capable of dividing
the refresh memory into different windows which can be controlled independently to
provide for horizontal and vertical movement or scroll of the texts. For that purpose
an auxiliary memory carries the list of rows of characters to be displayed. Therefore
on the one hand the windows divide the screen only vertically while on the other hand
the memory is recorded in accordance with a single alpha-numeric mode in a manner
corresponding to all the windows.
[0004] A display controller is also known, which comprises a refresh memory formed by a
plurality of pages which are read in parallel relationship for displaying colour images.
That controller makes it possible to record a first page by means of alpha-numeric
codes while the other pages are recorded with a dot map. In the display operation,
it is possible to select complementary zones of the first page and the other pages
in such a way as to substitute an alpha-numeric text for a graphic portion. However
that control does not make it possible simultaneously to display characters and graphics
of different definitions, so that it is not very flexible.
[0005] The object of the present invention is to provide a display control in which the
refresh memory can be recorded and displayed simultaneously with character codes and
dot map.
[0006] The object is met by the display controller of the invention as defined in the characterising
portion of claim 1.
[0007] That arrangement finds practical application for example in work stations of banking
type, in which the operation, by a single display operation, can check both the state
of the account of the customer, which is recorded by means of codes, and the customer
signature which is recorded in graphic form.
[0008] The following description sets forth a preferred embodiment of the invention which
is given by way of non-limiting example, with reference to the accompanying drawings
in which:
Figure 1 is a general diagram of a computer for personal use which incorporates the
display control according to the invention,
Figure 2 is a block diagram of the display controller of the invention,
Figure 3 is a diagrammatic view of the input and output registers of the controller
in figure 2,
Figure 4 is a diagram of the refresh memory for graphic data in standard mode,
Figure 5 is a diagram of the refresh memory for graphic data in window mode,
Figure 6 is a diagram illustrating an example of a display operation and the associated
memory of the window descriptors.
[0009] Referring to Figure 1, reference numeral 10 generally indicates a central unit (CPU)
of a computer, for example a personal computer, which is connected by means of a data
and address channel or bus 11 to a working read-write memory (RAM) 12 and a read only
memory (ROM) 13. Also connected to the bus 11 is a series of input/output units such
as a keyboard 14, a printer 15, a floppy disc unit 16 and a display controller 17
which controls the display of data and images on a display unit 18, for example of
cathode ray tube (CRT) type.
[0010] The display controller 17 (see Figure 2) comprises a tube control unit (CRTC) 19
which is programmable to generate the vertical and horizontal timing signals and the
raster address signals for control of the display. It comprises a logic means for
controlling the cursor, the movement of the image and the other functions required
of the display. By way of example, the unit 19 may be formed by the integrated component
HD6345 produced by Hitachi and permits sub-division into four segments in the vertical
direction of the image on the screen, with independent scroll in the individual segments
and control of two independent cursors. For that purpose the unit 19 comprises a series
of registers for controlling the various functions, including two horizontal and vertical
synchronisation registers, for indicating the position or cell of the character to
be displayed, as a multiple of the period of a character on the line, or line of characters,
as will be described in greater detail hereinafter.
[0011] The display controller 17 can control both the display of characters in accordance
with a pixel or dot matrix having a given number of columns and rows, and the display
of graphics, the pixels of which are recorded in a memory in accordance with a memory
bit map.
[0012] The following display modes are provided for a standard video display unit 18 with
640 × 400 pixels:
1) Alpha-numeric mode of 80 × 25 characters in accordance with a matrix of 8 × 16
pixels;
2) Alpha-numeric mode of 40 × 25 characters in accordance with a matrix of 16 × 16
pixels;
3) High-definition monochrome graphic mode of 640 × 400 pixels;
4) Normal-definition monochrome graphic mode with 640 × 200 pixels;
5) High-definition colour graphic mode with 320 × 400 pixels;
6) Normal-definition colour graphic mode with 320 × 200 pixels.
[0013] It will be clear therefore that, in the alpha-numeric modes, the display is effected
with the same definition as the graphic mode with 640 × 400 pixels. The dot matrix
of 8 columns × 16 rows defines a cell on the screen whereby the screen can contain
a total of 2000 cells.
[0014] The logic means of the unit 19 is controlled by a group 21 of input/output registers
(I/O) connected thereto by a data bus 20 which in turn is connected to the bus 11
by way of a data interface 22. The registers 21 serve to define the operating conditions
or modes of the control and the modes in which the images are to be displayed.
[0015] The controller 17 further comprises a display refresh memory 23 which is connected
to the unit 19 by means of a latch 25 and a multiplexer 26. An address interface 24
is connected to the multiplexer 26 and to a unit 44 for selection between the memory
and the registers 21.
[0016] Finally the logic means of the unit 19 can send an interrupt requires to the CPU
10 to permit the latter to recognise undesired accesses to the memory 23 or to the
registers 21. The interrupt request is transmitted on the bus 11 by way of an interrupt
interface 30.
[0017] In accordance with the invention the controller 17 can control the video display
unit 18 selectively in accordance with a standard condition or mode in which the display
is effected uniformly in one of the above-listed modes, and in accordance with a condition
or mode which will be referred to hereinafter as the window mode and in which the
screen can be sub-divided into two or more windows which can be displayed in different
ways.
[0018] The refresh memory 23 has a capacity of 32 Kbytes and is capable of being written
selectively under the control of the CPU 10 and an arbiter unit formed by another
multiplexer 45, with the character codes, or in accordance with a map of the pixels
of the graphics to be displayed. For recording character codes, the memory 23 is subdivided
in accordance with words of 2 bytes, the first of which represents the alpha-numeric
code of the character while the second byte represents the attributes of the character,
that is to say characteristic particulars in accordance with which the character is
to be displayed such as underlining, reverse, colour of background and character,
light strength, etc. Since a page of 40 × 25 characters requires a memory of 2 Kbytes
while a page of 80 × 25 characters requires a memory of 4 Kbytes, the refresh memory
23 can contain up to a maximum of 16 pages of text in the former case and 8 pages
in the latter case.
[0019] The output of the memory 23 is held at a latch 46. For displaying a character, the
alpha-numeric code of the latch 46 is used to address a ROM 27 acting as a character
generator while the bytes of the attributes are used for addressing an attribute decoder
28. The outputs of the generator 27 and the decoder 28 therefore define the pixels
to be displayed on the video display, for each scanning line. It should be noted that
the characters in the alpha-numeric mode 40 × 25 are produced in known manner by the
same character generator 27, repeating each output bit during horizontal scanning
under the control of the unit 19.
[0020] For recording graphic pixels, the memory 23 records a map of a bit for each pixel
in the monochrome display mode and two bits for each pixel in the case of colour display.
In that case the two bits can define four different colours for the pixel, In the
case of high-definition display, the entire memory 23 can thus refresh a single graphic
page while in the normal-definition display mode, 16 Kbytes of memory 23 are sufficient
to refresh a graphic page, whereby half of the memory 23 can be disregarded or can
be used to record another graphic page. The unit 19 then controls reading of the map
of the memory 23 in accordance with the line raster sequence provided for control
of the display 18.
[0021] In particular the memory 23 (see Figure 4) is allocated between the addresses B8000
and BFFFF. In the normal-definition graphic mode of 200 lines the memory 23 is divided
into two 16 Kbyte halves which are connected together by means of a transceiver 47
(Figure 2) and connected to the bus 20 by means of another transceiver 48. Each half
of the memory 23 contains a display page; in the first half odd lines 1,3,5 etc of
the image are recorded at the addresses between B8000 and B9FFF (see Figure 4) while
the even lines 2, 4, 6 etc of the image are recorded at the addresses between BA000
and BBFFF. A similar situation obtains in the second half of the memory 23 from the
address BC000 when it is selected by a signal PAGE = 1. For the colour graphic mode
with 320 × 200 the lines are recorded as above, but the bits of each byte are coupled
in pairs for selecting the colour, whereby each byte controls the display of four
dots.
[0022] In the high-definition graphic mode the entire memory 23 provides for a single memory
map in which recording takes place in accordance with following table I (see also
Figure 4):
TABLE I
[0023] Lines 1, 5, 9, 13, 17, 21, 25, 29, etc address B8000-B9FFF
Lines 2, 6, 10, 14, 18, 22, 26, 30 etc address BA000-BBFFF
Lines 3, 7, 11, 15, 19, 23, 27, 31 etc address BC000-BDFFF
Lines 4, 8, 12, 16, 20, 24, 28, 32, etc address BE000-BFFFF
[0024] For colour display, an ROM 29 (see Figure 2) forming the colour table is addressed
by a background mixer unit 49, by a serialiser 31 for the output signals from another
mixer unit 50 for the signals to be displayed, and the output signals of the attribute
decoder 28, to determine the colours of the pixels to be displayed. The mixer units
49 and 50 also receive the signals from the registers 21 by way of a multiplexer 51
and a latch 52 and the signals from the memory 23 by way of a further latch 53. In
particular the ROM 29 comprises two separate colour tables or palettes which can be
selected, as will be described hereinafter. The palette 1 comprises the colours black,
green, red and yellow, while the palette 2 comprises the colours grey, cyan, magenta
and white. The signals from the colour table 29 are passed to an interface 32 of the
video display unit 18, which thus provides for control of the display of the content
of the memory 23.
[0025] The display 18 may be formed by a video display for displaying monochrome images
in the positive mode, that is to say, for displaying characters in black on a white
background. Such a display has a standard capacity of 640 × 640, whereby that number
of pixels can be displayed in the graphic mode. In the alpha-numeric mode, by virtue
of the optical effect of expansion of the black pixels, the characters are traced
out differently with respect to those of the negative display, so that the result
is different from that obtained by the negative character with the attribute 'reverse'.
[0026] In addition, in the alpha-numeric mode it can be conditioned by means of a known
circuit to display 640 × 480 pixels. In that case the matrix of the character was
selected as 8 × 15 whereby the format of the display is provided by 80 × 32 characters.
The positive characters in standard mode and in 8 × 15 mode are generated by a second
character generating ROM 34, as will be described hereinafter. When the positive display
is present, the refresh RAM 23 will have a capacity of 36 Kbytes. The output signals
from the character generator 34 are passed by way of the table 29 to the serialiser
31 from which they issue in series to provide pilot control for the display 18 in
a similar manner to that described above for the negative monochrome display. An
OR circuit permits alternative connection as between the two character generators
27 and 34 and the mixer unit 50.
[0027] In the window mode the control unit 19 conditions means included in the unit 44 to
address the individual cells at the refresh memory 23, both for display in accordance
with an alpha-numeric mode and for display in accordance with a graphic mode. It is
thus possible to define any graphic window which has an integral number of cells and
thus a number of columns and rows which is a multiple of those of the character matrix.
In that case the multiplexer 45 applies to the addresses of the memory 23 an offset
such that it appears to the CPU 10 to be allocated to the addresses A 8000-AFFF (see
Figure 5). In the normal-definition graphic mode, the memory 23 is now divided into
eight zones which constitute the eight scanning lines of the cells. The first zone
between the addresses A8000 and A87FF is addressed directly by the unit 19, while
the other portions are addressed successively by way of a constant offset of 800 hexadecimal.
Therefore the scanning lines of the screen are recorded in the memory 23 in the sequence
indicated in following table II (see also Figure 5). That sequence comprises only
the first 16 Kbytes of memory 23 and is repeated in a similar manner for the second
16 Kbytes of memory 23.
TABLE II
[0028] Lines 1, 9, 17, 25, 33 etc address A8000-A87FF
Lines 2, 10, 18, 26, 34 etc address A8800-A8FFF
Lines 3, 11, 19, 27, 35, etc address A9000-A97FF
Lines 4, 12, 20, 28, 36 etc address A9800-A9FFF
Lines 5, 13, 21, 29, 37 etc address AA000-AA7FF
Lines 6, 14, 22, 30, 38, etc address AA800-AAFFF
Lines 7, 15, 23, 31, 39 etc address AB000-AB7FF
Lines 8, 16, 24, 32, 40 etc address AB800-ABFFF
[0029] Similarly in the high-definition graphic mode, the entire memory 23 is divided into
16 zones which constitute the 16 scanning lines of the cells. The sequences of recording
in the memory 23 are set out in following table III:
TABLE III
[0030] Lines 1, 17, 33, 49, 65 etc address A8000-A87FF
Lines 2, 18, 34, 50, 66 etc address A8800-A8FFF
Lines 3, 19, 35, 51, 67 etc address A9000-A97FF
Lines 4, 20, 36, 52, 68 etc address A9800-A9FFF
Lines 5, 21, 37, 53, 69 etc address AA000-AA7FF
Lines 6, 22, 38, 54, 70 etc address AA800-AAFFF
Lines 7, 23, 39, 55, 71 etc address AB000-AB7FF
Lines 8, 24, 40, 56, 7 etc address AB800-ABFFF
Lines 9, 25, 41, 57, 73 etc address AC000-AC7FF
Lines 10, 26, 42, 58, 74 etc address AC800-ACFFF
Lines 11, 27, 43, 59, 75 etc address AD000-AD7FF
Lines 12, 28, 44, 60, 76 etc address AD800-ADFFF
Lines 13, 29, 45, 61, 77 etc address AE000-AE7FF
LInes 14, 30, 46, 62, 78 etc address AE800-AEFFF
Lines 15, 31, 47, 63, 79 etc address AF000-AF7FF
Lines 16, 32, 48, 64, 80 etc address AF800-AFFFF
[0031] The controller 17 (see Figure 1) further comprises an auxiliary read-write memory
(RAM) 33 (see Figure 2) which is addressed by way of the interface 24 and the arbiter
multiplexer 45. The memory 33 is connected by way of a latch 54 to the multiplexer
26 and by way of a transceiver 55 to the bus 20. The control unit 19 is capable of
associating with each alpha-numeric code in the memory 23 and with each graphic recording
cell in the same memory, a byte of the auxiliary memory 33 in which there is recorded
a window descriptor code which defines the mode in which the corresponding cell is
to be displayed.
[0032] The memory 33 has a capacity of 4 Kbytes and is allocated to the addresses A0000-A7FFF
(see Figure 6) and can therefore contain two separate pages of the screen. The auxiliary
memory 39 is suitably compiled in each byte with the window descriptors coherent with
the data recorded in the refresh memory 23. The two memories 23 and 33 are accessible
to the CPU 10 at any time without waiting for the retrace period, either in sequence
or individually. In the former case the descriptors are recorded on each occasion
at the time of recording of the cell while in the second case it is possible to modify
the content of a cell or the descriptor thereof, one independently of each other,
while obviously respecting coherence in respect of the alpha-numeric or graphic modes.
[0033] In particular the display mode is defined by the three lowest-value bits 0, 1 and
2 which are referred to as D0, D1 and D2. Table IV below sets out decoding of those
three bits of the window descriptor byte.

[0034] The other bits D3-D7 of the byte are used for the definition of colours in the graphic
modes and for the definition of some attributes in the alpha-numeric modes, as will
become apparent hereinafter.
[0035] The graphic signals emitted by the memory 23 (Figure 2) and those emitted by the
character generator 27 or 34 and the attribute decoder 28 are now passed to the two
mixer units 49 and 50 which load the serialiser 31 to address the colour table 29,
thus providing control for the video 18.
[0036] The various units of the controller 17 are controlled by the group 21 of I/O registers,
which comprises six registers 36-42 (see Figure 3), the bits of which give the signals
indicative of the various parameters required by the display. In particular the register
36 operates as a read only unit and forms the status 1 register whose bit 0 supplies
a signal DISPN = 1 when there is a horizontal or vertical retrace period. The bit
3 provides a signal VSYN = 0 substantially during vertical retracing. The bit 4 provides
a signal MONO = 0 in the presence of a colour CRT and a signal MONO = 1 in the presence
of a monochrome CRT.
[0037] The register 37, operating each time also as a read only unit, constitutes the status
2 register whose bit 0 provides a signal INTI = 1 to permit access to the other I/O
registers of the group 21 and a signal INTI = 0 to permit reading of the register
37 by the CPU 10. The bit 1 provides a signal INTM = 1 to permit access to the refresh
memory 23. The bit 2 is capable of providing a signal WIND for selecting the condition
or mode of the display. In particular WIND = 0 is provided for operating in the standard
mode while WIND = 1 is provided for operating in the window mode. The bit 3 provides
a signal MONI = 0 when a positive display is present and a signal MONI = 1 when a
normal display of 640 × 400 pixels is present. The signal MONI therefore serves to
select the two character generators 27 and 34.
[0038] The register 38 constitutes the colour setting register whose bits 0, 1 and 2 provide
the signals BALT, GLAT and RALT which define the three primary colours while the bit
5 provides the signal CO = 0 to select the colour palette 1 and a signal CO = 1 to
select the colour palette 2. The bit 3 provides the signal ILAT which determines the
intensity of all the colours while the bit 4 provides the signal ALTB which provides
the intensity of the colours of the data to be displayed in the colour graphic modes.
[0039] The registers 39, 41 and 42 constitute three mode registers. The bit 0 of the mode
1 register 39 provides a signal HRES = 1 for defining the alpha-numeric mode 80 ×
25 and a signal HRES = 0 to define the alpha-numeric mode 40 × 25. The bit 1 provides
a signal GRAP = 1 in the graphic modes and GRAP = 0 in the alpha-numeric modes. The
bit 3 provides the signal VIDE = 1 to enable the display and the signal VIDE = 0 during
reprogramming of the I/O registers and the unit 19. The bit 4 provides a signal BWO
= 1 in the monochrome graphic modes and a signal BWO = 0 in the colour graphic modes.
The bit 5 provides the signal BLIB only in the alpha-numeric modes and if BLIB = 1
enables blinking of the characters which have the attribute of the intensity of the
background = 1.
[0040] The bit 0 of the mode 2 register 41 provides a signal OLIM = 1 in the high-definition
graphic modes 640 × 400 and 320 × 400. In the alpha-numeric modes it permits the unit
19 to address any part of the memory 23. The bit 3 provides a signal PAGE = 0 to select
one half of the memory 23 in the normal-definition graphic modes and a signal PAGE
= 1 to select the other memory half 23. The bit 6 provides a signal UNDE = 1 which
enables decoding of the underlining attribute in such a way that all the characters
defined in colour blue by the attribute byte are displayed in white and underlined.
The bit 7 provides a signal ABWF = 1 to enable the status 2 register 37.
[0041] Finally the register 42 constitutes the mode 3 register whose bit 0 provides a signal
POSO which can be used only with a positive video display. Then if POSO = 1, negative
display is enabled, with the character generator 27 being activated. The bit 5 provides
a signal MODO = 0 to indicate a display of format 640 × 400 and a signal MODO = 1
to indicate a display of format 640 × 480.
[0042] In the window mode, the signals of the status 1 and status 2 registers 36 and 37
and the mode 3 register 42 as well as the signal VIDE of mode 1 register 39 and the
signal ABWF of mode 2 register 41 maintain their functions without alteration. On
the other hand the other functions are controlled by the bits D3-D7 of the window
descriptors. In particular, in the alpha-numeric modes the bits D3 and D4 of the window
descriptors have the same function respectively as the signal BLIB of the mode 1 register
39 and the signal UNDE of the mode 2 register 41. In the graphic modes the bits D3-D7
respectively perform the same functions as the signals BLAT, GLAT, RALT, ILAT and
ALTB of the colour register 38.
[0043] The mode of operation of the display controller 17 as described above is as follows:
[0044] Assuming that the display is of negative monochrome type, the registers 36-42 are
recorded with the corresponding signals. If the system operates in the standard mode,
the bit 2 of the register 37 is set in such a way as to provide the signal WIND =
0. That signal conditions the unit 19 (see Figure 2) to operate on the refresh memory
23 in dependence on the other parameters provided by the registers 36-42 in the above-described
manner. To operate in the window mode, the bit 2 of the register 37 on the other hand
is set in such a way as to provide the signal WIND = 1. That signal conditions the
unit 19 to operate on the refresh memory 23 and on the auxiliary memory 33, deactivating
the register 38 and the outputs 0-6 of the register 41.
[0045] It will be assumed now that a page is to be recorded, which appears on the monochrome
display as formed by a strip 60 (see Figure 6) formed by three lines of alpha-numeric
characters in the mode 80 × 25, a window 61 formed by 30 × 15 cells for a graphic
image in accordance with the graphic mode of 640 × 400, a window 62 of 10 × 15 characters
in the mode 40 × 25, a window 63 formed by 30 × 15 cells for another graphic image
in accordance with the graphic mode of 640 × 200, and a strip 64 formed by seven rows
of characters in the mode 80 × 25.
[0046] 240 words are recorded in the zone A800-A87FF in the refresh memory 23 (see Figure
5). Each word is formed by a byte of alpha-numeric code and a byte of the associated
attribute. Correspondingly, recorded in the auxiliary memory 33 are 240 bytes which
indicate the 80 × 25 alpha-numeric recording mode. Those bytes will therefore have
the bits D0 = 1, D1 = 0 and D2 = 0.
[0047] For the fourth row of cells, recorded in the memory 23 are 30 × 16 words in a memory
map in accordance with the layout in Figure 5. In particular the unit 19 defines the
address of only the first line in each cell in the zone A8000 - A8700 while the subsequent
lines in the same cell are automatically addressed by adding the hexadecimal constant
800 to the above-indicated address.
[0048] The first line of words of graphic cells is associated with 30 bytes of descriptors
in the auxiliary memory 33 which comprise the bits D0 = 0, D1 = 0 and D2 = 0. They
are followed by ten words recorded for a row of characters in the mode 40 × 25, each
of which occupies two adjoining cells of the screen. In a corresponding manner, recorded
in the auxiliary memory 33 are 20 bytes, with the associated descriptors, which comprise
the bits D0 = 1, D1 = 0 and D2 = 1, whereby it will be clear that each character of
the format 16 × 16 requires two descriptors. Finally, for the fourth row of cells,
30 × 8 words are recorded in the refresh memory 23 in a memory map in the mode 600
× 200, in accordance with the layout in Figure 5.
[0049] In this case also the unit 19 defines the address of just the first line of each
cell in the zone A8000 - A8700 while the subsequent lines of the same cells are automatically
addressed by adding the hexadecimal constant 800 to the address. In this case also
associated with the first line of words of graphic cells are 30 bytes of window descriptors
in the auxiliary memory 33. The fourth row of cells therefore also requires 80 descriptors.
[0050] Recording is effected in a similar manner in respect of the 14 other rows of cells
in which the three windows 61, 62 and 63 appear. Finally, recorded in the zone A8000
- A87FF of the memory 23 are 560 words for the last seven rows of characters in accordance
with the mode 80 × 25 while the associated 560 bytes of window descriptors are recorded
in the auxiliary memory 33. The page being considered therefore requires 2000 descriptors.
[0051] It will be clear therefore that the auxiliary memory 33 records a constant number
of window descriptors, independently of the modes in which the individual windows
are recorded.
[0052] For display purposes, the unit 19 sequentially addresses the words of the first memory
zone 23. For each word associated with window descriptors which identify one of the
alpha-numeric modes, the first byte is emitted as the address of the character generator
27 and the second byte is passed to the attribute decoder 28 during the operation
of scanning all the elementary lines of the row of cells.
[0053] For each word in the first memory zone 23 associated with window descriptors which
identify one of the graphic modes during the scanning of the successive elementary
lines of the cell, the unit 19 addresses the word which is read in the sequence of
memory zones 23 provided by the respective graphic mode. The output of the character
generator 27 or 34 and the attribute decoder 28 in the alpha-numeric modes and the
output of the memory 23 in the graphic modes is passed to the mixer unit 50 which
thus provides for mixing of the graphic and alpha-numeric signals. The output from
the unit 50, by way of the serializer 31, arrives at the colour table 29 whose output
provides control for the video 18 by way of the display interface 32.
[0054] It will be appreciated that the controller described may be the subject of various
modifications and improvements without departing from the scope of the invention.
For example the refresh memory 23 may be formed by a group of memory levels in order
to produce images with a better selection of colours, defining each pixel by means
of a group of corresponding bits in the various memory levels. The controller 17
may also be provided for controlling different video display units, for example a
negative display unit and a positive display unit. Finally the latter may be provided
only to operate in a standard mode, in which case the character generator 34 will
not be connected to the refresh memory 23.
1. A display controller for data processing apparatuses comprising a display refresh
memory (23) for storing the codes of the characters to be displayed or the map of
the dots of the graphics to be displayed, a character generator (27, 34) for providing
for each character code the dots of the associated character in accordance with a
predetermined matrix of rows and columns, and a control unit (17) for sequential control
of the display in accordance with the dot map characterised in that the control unit
(17) includes logic means (47-50) which are active in a window mode to divide the
memory (23) in such a way as to display a series of independent windows and selectively
to record the character codes or the dot map in each window, means (33) being provided
to condition the control unit (17) in such a way as to control the display in accordance
with the recording mode in each window.
2. A controller according to claim 1, characterised by a second refresh memory (23)
for recording the character codes or the dot map in a standard mode, means (37) being
provided to select the window mode and standard mode.
3. A controller according to claim 1 or 2, characterised in that each window recorded
in accordance with the dot map comprises a number of rows and columns which is a multiple
of that of the matrix, whereby each window comprises a whole number of graphic cells
of dimensions which are the same as the matrix.
4. A controller according to claim 3, characterised in that the conditioning means
comprise an auxiliary memory (33) for recording a window descriptor code (D0-D7) for
each character cell and for each graphic cell.
5. A controller according to claim 4, characterised in that the descriptor code (D0-D7)
is capable of selecting the definition of the character and the definition of the
graphic images respectively among a group of definitions provided by the control unit.
6. A controller according to claim 4 or 5, characterised in that the logic means (47-50)
are conditioned by a window descriptor in graphic mode to address the successive lines
of dots of a cell automatically on predetermined refresh memory portions.
7. A controller according to claim 6, characterised in that the memory portions are
determined automatically by adding a constant to the address of the first line of
the cell.
8. A controller according to any of claims 4 to 7, characterised by a series of registers
(21) for setting up the display parameters, one of the registers (37) being capable
of controlling the said selection means.
9. A controller according to claim 8, comprising a character generator (27, 34) addressable
by the character codes recorded in the memory (23) in a series of line scanning operations
of the display, characterised in that in the window mode, the memory portions are
addressed automatically from the address of the first line of the cells.
10. A controller according to any of the preceding claims, comprising means (37) for
controlling display of characters in a positive mode, characterised in that the character
generator (27, 34) comprises a zone (34) for generating of the characters in positive
mode, means (42) being provided to disable this zone of the character generator when
the window mode is selected.