An output amplifier for a charge transfer device

Abstract

 A capacitive level shift circuit is used to shift the level of the output of a charge transfer device from a high level down to a low level typically used in processing circuits to which the charge transfer device output is provided.

Description

Background of the Invention

[0001] This invention relates to an output amplifier for a charge transfer device, and particularly to an output amplifier suitable for a charge transfer device actuated with a high voltage power source.

[0002] Fig. 1 shows an output amplifier of a conventional bombarding channel type charge coupled device (BCCD). Reference numeral 1 represents a transfer portion of the BCCD for transferring signal charges according to transfer clock signals φ₁ and φ₂. An output gate transistor having its gate coupled to an output gate (OG) signal is provided at an end of the transfer portion 1, and a capacitor 2 is connected through the output gate transistor to the end of the transfer portion 1. A floating diffusion P, i.e., a connection between one end of the output gate transistor and the capacitor 2, is connected both to a first voltage source V_RD through a MOSFET transistor 3 for reset and to a gate of a MOSFET 4 constituting an impedance converting circuit.

[0003] The MOSFET 4 has a drain connected to a second voltage source V_DD and a source connected through a constant current source 5 to ground. The source voltage of the MOSFET 4 is provided to the output terminal 8.

[0004] One example of the construction of an ordinary BCCD is as follows. A thin n-type layer is formed on the surface of a p-type silicon substrate, and a transfer electrode is formed on the thin n-type layer. A relatively high reverse bias voltage is applied to the thin n-type layer to expel free electrons (majority carriers) from dopants in the n-type layer and generate a depletion layer consisting of dopant ions, so that a transfer channel is formed in the bulk of the n-type layer away from the Si-SiO₂ interface. Accordingly, when proper clock pulses φ₁ and φ₂ are applied to the transfer electrode, the signal charge is transferred in the transfer channel. As a result, transfer efficiency and transfer speed can be improved.

[0005] Next, the operation of an output amplifier having the above construction will be described hereinafter with reference to Figs. 1 and 2. Signal charge transferred from the transfer portion 1 of the BCCD is transferred through the output gate transistor to the floating diffusion P. Immediately before the transfer of the signal charge to the floating diffusion P, a reset signal φ_RS is set to a high (H) level to render the transistor 3 conductive. Accordingly, the potential of the floating diffusion P is positively reset to a voltage of the voltage source V_RD before the signal charge is read out. After the above step, the signal charge from the transfer portion 1 is provided through the output gate transistor and a potential drop corresponding to the amount of the signal charge occurs in the floating diffusion P, so that the signal charge is subjected to impedance conversion and is then outputted as a detecting signal S₀ to the output terminal 8.

[0006] However, in the output amplifier of the charge transfer device actuated with a high voltage source as described above, the transfer channel of the BCCD is kept in a high potential state and therefore signal charge cannot be effectively detected unless the potential of the floating diffusion P is reset to a higher potential than the potential of the transfer channel. Accordingly, the voltage of the voltage source V_DD must be maintained extremely high, e.g., at least 10 V, and similarly the voltage of the other voltage source V_DD must be kept high, so that it is difficult to combine the BCCD or the like with circuits actuated with a low voltage source.

[0007] Furthermore, for ordinary use, detecting signal S₀ is applied to and operated on by a logical circuit actuated with a relatively lower voltage, and therefore a large gap occurs between the level of the voltage V_CC to be applied to the logic circuit and the level of the voltages V_RD and V_DD to be applied to the output amplifier of the BCCD, so that compatibility becomes a problem.

[0008] Accordingly, it is an object of this invention to provide an output amplifier for a charge transfer device operable with a low voltage source.

Summary of the Invention

[0009] To attain the above and other objects, the output amplifier according to the present invention for detecting signal charge transferred from a transfer channel in a charge transfer device is characterized in that a level shift circuit with capacitive elements is provided at an end of the output of the charge transfer device.

Brief Description of the Drawings

[0010] The invention will be more clearly understood from the following description in conjunction with the accompanying drawings, in which:

Fig. 1 shows a conventional output amplifier of a charge transfer device;

Fig. 2 shows a timing chart for explaining the operation of the circuit shown in Fig. 3;

Fig. 3 shows an embodiment of an output amplifier of a charge transfer device according to this invention; and

Fig. 4 shows a timing chart for explaining the operation of the circuit shown in Fig. 1.

Detailed Description of the Invention

[0011] An embodiment of a charge transfer device output amplifier according to this invention will be described hereinafter with reference to Fig. 3.

[0012] In Fig. 3, reference numeral 9 represents a BCCD of the type shown in Fig. 1. An output gate transistor having its gate controlled by the output gate signal OG connects a floating diffusion P₁ to the BCCD. The floating diffusion P₁ is also connected through a first capacitive element 10 to ground, and is connected through a reset MOSFET 11 to a first power source line V_RD. Finally, the diffusion P₁ is connected to one end of a second capacitive element 12. The connection point P₂ at the output side of the capacitive element 12 is connected through a third capacitive element 13 to ground, connected through an analog switch 14 to a second power source line V_CC, and is further connected to the gate of the MOSFET 15 with source follower configuration. The source of the MOSFET 15 is connected through an analog switch 16 to the gate of the MOSFET 17 with source follower configuration, and the source of the MOSFET 17 is connected to an output terminal 18.

[0013] MOSFETs 19 and 20 are connected in series with each other between the power source V_CC and ground to form a current source circuit for generating a desired current. The MOSFET 20 and a pair of MOSFETs 21 and 22 comprise a current mirror circuit for supplying the MOSFETs 15 and 17 with a desired current.

[0014] The analog switch 16 is supplied with a sample-and-hold signal φ_SH, and the combination of the analog switch 16 and the MOSFETs 17 and 22 carries out a sample-and-hold operation. A reset signal φ_RS is applied simultaneously to the MOSFET 11 and to the analog switch 14, to reset the floating diffusion P₁ and the connection point P₂ to the voltages of the first and second power source lines V_DD and V_CC, respectively.

[0015] Reference numeral 23 represents a voltage increasing circuit for increasing the voltage of the second power source line V_CC by means of a charge pumping circuit or the like, and for generating the voltage of the first power source line V_RD. In this embodiment, the second power source line V_CC is set to a voltage approximately in the range of 3 to 5 volts, which is required for operating an ordinary logic circuit, and the first power source line V_RD is set to about 10 volts.

[0016] The operation of the output amplifier as described above will now be described with reference to a timing chart shown in Fig. 4. Before a signal charge is transferred from the transfer portion of the BCCD 9, a reset signal φ_RS is shifted to a high level, e.g., at a time t₁, to make the MOSFET 11 and the analog switch 14 conductive, so that the potential M_P1 of the floating diffusion P₁ is reset to the voltage V_RD and the potential V_P2 of the connection point P₂ is reset to the voltage V_CC.

[0017] After completion of the above resetting operation, the signal charge is transferred from the transfer portion of the BCCD 9 through the output gate OG thereby to generate a drop-out voltage ΔV (at a time t₂) corresponding to the signal charge at both of the floating diffusion P₁ and the connection point P₂. That is, since the floating diffusion P₁ and the connection point P₂ are connected through the capacitive element C₂ to each other, the connection point P₂ suffers the same drop-out voltage ΔV as suffered by the floating diffusion P₁.

[0018] The output terminal 18 has the same voltage as is maintained at the connection point P₂ at the time (t₃) when a sample-and-hold signal φ_SH is shifted to a high level, and outputs therefrom a signal S₀ of a voltage corresponding to the signal charge.

[0019] As described above, a signal of high voltage level V_RD is shifted to a signal of low voltage level V_CC by the configuration of the capacitive elements 10, 12 and 13 in this invention, so that a high voltage source is not demanded for an output amplifier, unlike a conventional output amplifier. As a result, the output amplifier can use the same low voltage source as employed in a signal processing circuit to be connected to the output terminal 18. This simplifies compatability problems between the BCCD and signal processing circuit to improve the flexibility in design, and the BCCD can be easily and effectively used in a circuit operated with a low voltage source.

[0020] According to this invention as described above, the capacitive configuration is used to shift the signal generated at the output terminal of the charge transfer device to an actuating voltage level for a circuit which is operated with a low voltage source, so that a charge transfer device operated with a high voltage source and a circuit operated with a low voltage source can be easily matched and combined.

Claims

1. An output amplifier for detecting signal charge transferred from a transfer channel of a charge transfer device, said output amplifier comprising:
a first capacitor having first and second terminals;
first means for setting said first terminal to a first predetermined voltage level prior to a first time;
second means for setting said second terminal to a second predetermined voltage level different from said first predetermined level prior to said first time;
connecting means for connecting said signal charge to a first terminal at said first time to cause a change in the voltage level at said first terminal and a change in the voltage level at said second terminal which corresponds to said change at said first terminal; and
output means for providing an output in accordance with the voltage level at said second terminal.

2. An output amplifier as claimed in Claim 1, wherein said first predetermined level is higher than said second predetermined level.

3. An output amplifier as claimed in Claim 1, wherein said first means comprises a switching transistor coupled between said first terminal and a source of voltage of said first predetermined level and said second means comprises an analog switch coupled between said second terminal and a source of voltage of said second predetermined level.

4. An output amplifier as claimed in Claim 3, wherein switching transistor and switch are actuated by a common signal.

5. An output amplifier as claimed in Claim 3, wherein said source of voltage of said first predetermined level comprises a voltage increasing circuit having an input coupled to said source of voltage of said second predetermined level for increasing the voltage at its input to obtain a voltage of said first predetermined level.

6. An output amplifier as claimed in Claim 1, wherein said output means comprises first and second transistors each having a conduction path between first and second transistor terminals and a control terminal with the conduction of each said conduction path varying in accordance with the voltage level at the respective control terminal, the control terminal of said first transistor being coupled to said first terminal of said capacitor, the first terminals of each of said first and second transistors being coupled to a source of voltage of said second predetermined level, current supply means coupled to the second terminal of each of said first and second transistors for supplying each of said first and second transistors with a desired current, and further switch means for connecting said second terminal of said first transistor to the control terminal of said second transistor after said first time.

Drawing