(19)
(11) EP 0 282 969 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
15.03.1989 Bulletin 1989/11

(43) Date of publication A2:
21.09.1988 Bulletin 1988/38

(21) Application number: 88104084.4

(22) Date of filing: 15.03.1988
(51) International Patent Classification (IPC)4: G06F 7/00, G06F 13/38
(84) Designated Contracting States:
DE FR GB

(30) Priority: 18.03.1987 JP 61011/87

(71) Applicant: HITACHI, LTD.
Chiyoda-ku, Tokyo 100 (JP)

(72) Inventors:
  • Matsumura, Hisashi
    Hadano-shi (JP)
  • Wada, Hiroyuki
    Hadano-shi (JP)
  • Ugajin, Atsushi
    Hadano-shi (JP)
  • Niwa, Tokuhiro
    Hadano-shi (JP)
  • Nakamura, Masayuki
    Showa-ku Nagoya (JP)
  • Nakai, Kouichi
    Owariasahi-shi (JP)
  • Inagawa, Takashi
    Midoricho Owariasahi-shi (JP)

(74) Representative: Beetz & Partner Patentanwälte 
Steinsdorfstrasse 10
80538 München
80538 München (DE)


(56) References cited: : 
   
       


    (54) Computer system having byte sequence conversion mechanism


    (57) In a computer system with a configuration in which a plurality of processors (1, 2) respectively having different word access methods access a common memory (19), there is disposed between the common memory and the processors a conversion circuit (29-32, 40-47) to reverse the sequence of the bytes constituting each word. Furthermore, there are disposed between input/­output controllers (121, 122) and the processor (101) a conversion circuit (115-118) to reverse the sequence of the bytes constituting each word.







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