Scaled voltage level translator circuit

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EP 0 288 697 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	07.02.1990 Bulletin 1990/06

(43)	Date of publication A2:
	02.11.1988 Bulletin 1988/44

(21)	Application number: 88103608.1

(22)	Date of filing: 08.03.1988

(51)	International Patent Classification (IPC)⁴: H03F 3/343

(84)	Designated Contracting States:
	DE FR GB IT

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Priority:

01.05.1987 US 45348

(71)	Applicant: International Business Machines Corporation
	Armonk, N.Y. 10504 (US)

(72)	Inventors:
	Lobb, Kenneth George Rochester Minnesota 55901 (US) Schuelke, Brian Andrew Rochester Minnesota 55901 (US) Schmerbeck, Timothy Joseph Kasson Minnesota 55944 (US) Sutton, Manning Olsen San Francisco California 94117 (US)

(74)	Representative: Vekemans, André (BE)
	Compagnie IBM France Départ. Propriété Intellectuelle B.P. 13 F-06610 La Gaude F-06610 La Gaude (FR)

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References cited: :

(54)	Scaled voltage level translator circuit

(57) A circuit (100) translates an input signal (EIN) about an input reference voltage (E1) to an output signal (EOUT) referenced to a different voltage (2). The input signal may be scaled, and multiple inputs may be scaled independently and summed. Shift networks transfer the input signal across a resistor (R1) on the input of a current mirror; the the output signal appears across a resistor (R3) in an output of the mirror.

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