The present invention relates to a display device, more particularly to a display device having such an incomplete memory characteristic as that of ferroelectric liquid crystal and which takes a specified time to rewrite the picture elements, and to a driving system of the display device.

Ferroelectric liquid crystal is a well-known element with incomplete memory characteristic. When a picture is to be displayed on a matrix type display panel that uses ferroelectric liquid crystal, video signals are sent from, say a personal computer to the display panel. Since the video signals from the personal computer are non-interlace signals, however, it is not possible to use all frames of the signals in displaying the picture on the panel because of the time restriction for rewriting by the ferroelectric liquid crystal. Conventionally, therefore, a picture is displayed by using, for instance, every other frame of video signals.

Assuming that the number of scanning lines M of a video signal sent from a personal computer is 200 and that the time required by the liquid crystal for rewriting the picture elements in one horizontal scanning period is 200 »s, the frame frequency fF on the screen is calculated as:$$\text{fF =}\frac{\text{1}}{\text{f × M}}\text{=}\frac{\text{1}}{\text{200 × 10⁻⁶ × 200}}\text{= 25 Hz}$$

If the memory characteristic of the liquid crystal is incomplete, when a figure "1" is kept written, the luminance of the image changes little by little after the figure is rewritten, as shown in Figs. 7(1), 7(2), 7(3) and 7(4). For instance, the luminance of the picture elements on the lines L₁, L₂, L₃ and L₄ changes as shown in Figs. 7(1), 7(2), 7(3) and 7(4), respectively. The combined luminance of the 4 (vertical) × 4 (horizontal) picture elements changes at 25 Hz as shown in Fig. 7(5). Since human eyes can sense the luminance variation at a frequency not higher than 60 Hz, the above luminance change is sensed as a flicker so that the picture quality is deteriorated.

An object of the present invention is to solve the above problem by providing a display device and its driving system which improves the display picture quality by controlling the operation of rewriting the picture elements.

The invention is defined by the claims.

To achieve the above object, according to an embodiment of the present invention, a display device, which provides an incomplete memory characteristic and takes "r" seconds to rewrite the picture elements in one horizontal scanning period, comprises "M" scanning lines divided into a plurality of groups each containing "K" scanning lines (K>1, M>1, K, M = positive integers), and means for sending scanning signals to the "M" scanning lines so as to rewrite a picture. The scanning signal sending means sends scanning signals to the first scanning line in each scanning line group in the first frame, to the second scanning line in each scanning line group in the second frame, and to the "K"th scanning line in each scanning line group in the "K"th frame so that the picture elements on the "M" scanning lines are rewritten by "K" times of scanning.

The present invention is effective for the condition of$$\text{60 >}\frac{\text{1}}{\text{r x M}}$$ in which "r" is the time required for rewriting the picture elements in one horizontal scanning period.

The action of the present invention is described in the following, assuming K = 2, M = 200 and r = 200 »s for simplification.

In the first frame, the scanning lines of odd number 1, 3, 5, ..., 199 are scanned, and in the second frame the scanning lines of even number 2, 4, 6, ..., 200 are scanned, thus completing an entire picture in two frames. Specifically, picture signals input to the display device contain 200 effective scanning lines in one frame. However, all of these 200 effective lines are not used for each frame. For the first frame, the signals for scanning lines of odd number alone are used while those for scanning lines of even number are discarded. For the second frame, the signals for scanning lines of even number alone are used while those for scanning lines of odd number are discarded. As a result, picture elements are written at 50 Hz on the display panel, compared with 25 Hz by the conventional device. This results in less conspicuous flicker of a picture.

The present invention will become more fully understood from the detailed description of preferred embodiments given hereinbelow and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present invention, and wherein:

• Fig. 1 is a circuit diagram showing the construction of the display device of a first embodiment of the present invention;
• Fig. 2 is a chart of signal waveform in each part thereof;
• Fig. 3 is a circuit diagram showing the construction of the display device of a second embodiment of the invention;
• Fig. 4 and 5 are charts of signal waveform in each part thereof;
• Fig. 6 is a chart for explaining the effect of the present invention; and
• Fig. 7 is a chart for explaining the conventional device.

According to an embodiment of the present invention, a display device such as an X-Y matrix type liquid crystal display panel contains a pair of insulating substrates with a liquid crystal layer sandwiched therebetween. "M" pcs. of scanning electrodes are provided on the inner side of one of the substrates, and "N" pcs. of signal electrodes on the inner side of the other substrate, the scanning electrodes crossing the signal electrodes at a right angle. The display device of the present invention provides an incomplete memory characteristic and takes "r" seconds to rewrite the picture elements in one horizontal scanning period. An example of a substrate with an incomplete memory characteristic is ferroelectric liquid crystal. The insulating substrate of the display device may include a conductive member with an insulating film formed thereon or a conductive member alone. The insulating substrates having scanning electrodes and signal electrodes respectively are covered with insulating films, respectively. An effective display region is realized by the "M" scanning electrodes and the "N" signal electrodes.

The present invention is characterised in the following features.

The "M" scanning electrodes are divided into "P" groups each containing "K" scanning electrodes (K > 1, P > 1, K, P = integers). By the first frame, all the first scanning electrodes in all groups are scanned sequentially. Then by the second frame, all the second scanning electrodes in all groups are scanned sequentially. This process is repeated until all the "K"th scanning electrodes in all groups have been scanned by the "K"th frame. Namely, "P" scanning electrodes are scanned sequentially by each frame, and this scanning process is repeated "K" times to scan "M" scanning electrodes, thus rewriting the picture elements for one picture.

If "M" cannot be divided by "K", at least one of the "P" groups may contain fewer than "K" electrodes. But preferably every group should contain the same number of electrodes.

With K = 2, for instance, every other scanning line is rewritten by each frame. With K = 3, every third scanning line is rewritten by each frame.

The present invention is effective particularly for the condition of$$\text{60 >}\frac{\text{1}}{\text{r × M}}$$ .

In the following description, the display device is assumed to be an X-Y matrix type liquid crystal display panel in which the number of scanning electrodes "M" = 200, and the number of signal electrodes "N" = 640. It is not intended that the present invention is limited to the above; the number of electrodes "M" and "N" may be changed as desired.

In the X-Y matrix liquid crystal display panel 1 of the present embodiment, signal electrodes Y₁, Y₂, ... Y_N=640 are provided on the first insulating substrate, and scanning electrodes L₁, L₂, ... L_M=200 on the second insulating substrate. The signal electrodes and the scanning electrodes are covered with insulating films for insulation between the electrodes. A ferroelectric liquid crystal layer (such as CS-1014 by Chisso Corporation) is placed between the first and second insulating substrates.

Image data to be supplied to the signal electrodes Y₁, Y₂, ... Y₆₄₀ is sent in form of input signals Ei through a terminal 3 to a shift register 6 which comprises D flip flops R₁, R₂, ... R₆₄₀ corresponding to the signal electrodes respectively. The input signals Ei are applied to the data terminals of the D flip flops R₁, R₂, ... R₆₄₀. A basic clock pulse signal C is supplied from a converter circuit 2 to the clock terminals of the D flip flops R₁, R₂, ... R₆₄₀ so that data signals are output sequentially from the D flip flops R₁, R₂, ... R₆₄₀ in this order. The data signals thus output pass through D flip flops r₁, r₂, ... r₆₄₀ and drivers d₁, d₂, ... d₆₄₀ and are input to the signal electrodes Y₁, Y₂, ... Y₆₄₀. Horizontal clock pulse signals cℓ are supplied as clock signals to the D flip flops r₁ , r₂ , ... r₆₄₀.

Here, the image data or video signals contains "M" pcs. of scanning electrodes or scanning lines in one frame. When a picture is to be rewritten by "K" frames, the same image signals are supplied "K" times.

Using horizontal synchronizing pulse HP and vertical synchronizing pulse VP that are input through terminals 4 and 5, a converter circuit 2 generates basic clock pulse signal C and horizontal clock cℓ. The converter circuit 2 also generates selection signals U₁, U₂, ... U_K for selecting one of the 1st to the "K"th electrodes of each group. One of the selection signals U₁, U₂, ... U_K becomes high in each frame, the selection signal of high level changes in the order of U₁, U₂, ... U_K as a frame changes. Specifically, the selection signal U₁ becomes high in the first frame, and the selection signal U₂ becomes high in the second frame as shown in Fig. 2. And eventually, the selection signal U_K becomes high in the Kth frame (not shown).

Receiving the selection signal U₁ and the horizontal clock pulse signal cℓ, D flip flops b₁, b_K+1, ... supply rewrite signals through drivers a₁, a_K+1, ... to the scanning electrodes L₁, L_K+1, .... Similarly, receiving the selection signal U₂ and the horizontal clock pulse signal cℓ, D flip flops b₂, b_K+2, ... supply rewrite signals through drivers a₂, a_K+2, ... to the scanning electrodes L₂, L_K+2, .... With the selection signal U_K as well, rewrite signals are supplied to the specified scanning electrodes. Namely, on receiving the selection signal UK and the horizontal clock pulse signal cℓ, D flip flops b_K, b_2K, ... b_M supply rewrite signals through drivers a_K, a_2K, ... a_M to the scanning electrodes L_K, L_2K, ... L_M.

On receiving a selection signal and a horizontal clock pulse signal cℓ, the D flip flop b₁ supplies an output equivalent to the selection signal to the following D flip flop b_K+1 simultaneously as it supplies rewrite signal to the scanning electrode L₁. The D flip flop b_K+1, on receiving the signal output from the D flip flop b₁ and a horizontal clock pulse signal cℓ, outputs rewrite signal to the scanning electrode L_K+1 and simultaneously supplies an output equivalent to the selection signal to the following D flip flop. Through the repetition of this operation, the scanning electrodes of the same order in all groups are rewritten sequentially in the same frame period.

As a result, the lines L₁, L_K+1, ... are rewritten in the first frame, the lines L₂, L_K+2, ... are rewritten in the second frame, and the lines L_K, L_2K, ... are rewritten in the Kth frame so that all the effective scanning lines are rewritten in K frames, as indicated partly by the signal driver output D in Fig. 2. With K = 2, all the effective scanning lines are rewritten in two frames, the scanning lines of odd number being rewritten in the first frame and the scanning lines of even number being rewritten in the second frame.

Fig. 3 shows an example in which the present invention is applied to a split X-Y matrix type liquid crystal display panel 1. In this second embodiment, the display panel is divided into a first block 1A and a second block 1B. The first and second display block 1A and 1B are driven under the same condition as described later. The number of scanning electrodes in the effective display region is M, with M′ pcs. in the first display block 1A and M′ pcs. in the second display block 1B. The M′ scanning electrodes in each of the first and second display blocks 1A and 1B are divided into P′ groups each containing K′ electrodes.

In the display device of this construction, the first scanning electrodes of the groups are scanned first, and the second scanning electrodes of the groups are scanned next. This process is repeated until the K′th electrode of the groups are scanned. In other words, 2P′ scanning electrodes are scanned in each time, and the scanning operation is conducted K′ times to rewrite the picture on an entire display panel divided into the first and the second display blocks.

The action of the display device of the second embodiment shown in Fig. 3 is described assuming the number of scanning electrodes M = 200, the number of scanning electrodes in each of the first and second display blocks M′ = 100, and the number of signal electrodes N = 640. In each of the first and second display blocks, the scanning electrodes are divided into groups each containing K′ electrodes. In this example, K′ = 2. Therefore, the scanning lines of even number and the scanning lines of odd number are scanned separately.

A hundred scanning electrodes L₁, L₂, ... L₁₀₀ are arranged in the first display block 1A, and a hundred scanning electrodes L₁₀₁, L₁₀₂ ... L₂₀₀ are arranged in the second display block 1B. Both the first and the second display blocks 1A and 1B have 640 signal electrodes Y₁, Y₂, ... Y₆₄₀. Ferroelectric liquid crystal is used as a liquid crystal layer for each of the display blocks 1A and 1B.

Signal electrode drivers d₁, d₂, ... d₆₄₀ and D flip flops r₁, r₂, ... r₆₄₀ and R₁, R₂, ... R₆₄₀ for registers are basically the same as those for the first embodiment shown in Fig. 1. These elements are provided for the first and the second display blocks 1A and 1B independently. Image input signals Ei, horizontal synchronizing pulses HP and vertical synchronizing pulses VP as shown in Fig. 4 are input from a personal computer to terminals 3, 4 and 5, respectively. On the basis of these signal inputs, a first converter circuit 2 outputs image data signals Ei₁ and Ei₂, horizontal synchronizing pulses HP and basic selection pulses U shown in Fig. 5. The image data signals Ei₁ are supplied to the D flip flop R₁ for the first display block 1A, and the image data signals Ei₂ are supplied to the D flip flop R₁ for the second display block 1B.

On the basis of the horizontal synchronizing pulses HP and the basic selection pulses U, a second converter circuit 2′ generates basic clock pulse signals c, horizontal clock pulse signals cℓ and selection signals U₁ and U₂. In the present embodiment, the first and second converter circuit 2 and 2′ are provided separately. They may be combined in one circuit. Outputs from the first and second converter circuits 2 and 2′ are shown in Fig. 5.

Referring to Fig. 3, the selection signals U₁ are supplied to D flip flops b₁ and b₁₀₁, and the selection signals U₂ to D flip flops b₂ and b₁₀₂. The output from the D flip flop b₁ is given to the first scanning electrode L₁ via a scanning electrode driver a₁. The output from the D flip flop b₁₀₁ is given to the scanning electrode L₁₀₁ in the second display block 1B via a scanning electrode driver a₁₀₁. D flip flops b₃, b₅, ... b₉₉ are connected in series after the D flip flop b₁, but they are not shown in Fig. 3. The outputs from the D flip flops b₃, b₅, ... b₉₉ are connected via scanning electrode drivers a₃, a₅, ... a₉₉ to the scanning electrodes L₃, L₅, ... L₉₉ in the first display block 1A. Similarly, D flip flops b₁₀₃, b₁₀₅, ... b₁₉₉ are connected in series after the D flip flop b₁₀₁, although they are not shown. The outputs from the D flip flops b₁₀₃, b₁₀₅, ... b₁₉₉ are connected via scanning electrode drivers a₁₀₃, a₁₀₅, ... a₁₉₉ to the scanning electrodes L₁₀₃, L₁₀₅, ... L₁₉₉ in the second display block 1B.

The second selection signals U₂ are provided to D flip flops b₂ and b₁₀₂. Similarly, D flip flops b₄, b₆, ... b₁₀₀ are connected in series after the D flip flop b₂, and D flip flops b₁₀₄, b₁₀₆, ... b₂₀₀ after the D flip flop b₁₀₂. The D flip flops b₂, b₁₀₀, b₁₀₂ and b₂₀₀ drive the scanning electrodes L₂, L₁₀₀, L₁₀₂ and L₂₀₀ through the scanning electrode drivers a₂, a₁₀₀, a₁₀₂ and a₂₀₀, respectively, as shown in Fig. 3. The D flip flops b₄, b₆, ... b₉₈ and b₁₀₄, b₁₀₆, ... b₁₉₈ drive the corresponding scanning electrodes in the same manner as the above but the description thereof is omitted here. The clock pulse signal inputs to the scanning electrodes from the D flip flops b₁, ... b₂₀₀ are horizontal clock pulse signals cℓ generated by the second converter circuit 2′, and the clock pulse signal inputs to the signal electrodes from the D flip flops r₁, r₂, ... r₆₄₀ are also the horizontal clock pulse signals cℓ.

In the first frame, selection signals U₁ are supplied to the data terminals of the D flip flops b₁ and b₁₀₁. On the basis of the selection signals and the horizontal clock pulse signals cℓ supplied as clock pulse signal inputs, the D flip flops b₁ and b₁₀₁ supply the scanning electrodes L₁ and L₁₀₁ with the output P1 shown in Fig. 5. The outputs P₁ are also input to the data terminals of the following D flip flops b₃ and b₁₀₃ (not shown). On the basis of the signal input P₁ and the horizontal clock pulse signals cℓ supplied as clock pulse signal inputs, the D flip flops b₃ and b₁₀₃ output signals P₃ of Fig. 5 to the scanning electrodes L₃ and L₁₀₃. The similar pulses are output from the subsequent D flip flops to the corresponding scanning electrodes, and in the end of the first frame, the outputs from the D flip flops b₉₇ and b₁₉₇ are input to the data terminals and horizontal clock pulse signals to the clock terminals of the D flip flops b₉₉ and b₁₉₉, which then supply the scanning electrodes L₉₉ and L₁₉₉ with signals P₉₉ shown in Fig. 5. Thus, the first scanning electrodes of all groups are rewritten. In other words, rewrite signals are output sequentially to all the scanning electrodes of odd number in the first frame.

In the second frame, similar pulses are output from the D flip flops related to the second scanning electrodes of the groups, namely to the scanning electrodes of even number. The duration of the pulses P₁, P₃, ... P₉₉ is set at "r" sec. (about 200 »s in this embodiment) which is needed by liquid crystal to rewrite picture elements. "r/2" shown for the image data signal Ei in Fig. 5 is 100 »s in this embodiment.

Referring to Fig. 5, in the duration of the pulse P₁, for example, the D flip flops r₁, r₂, ... r₆₄₀ for the signal electrodes output signals to the first scanning line in the first display block 1A and to the 101st scanning line in the second display block 1B. Therefore, the scanning lines L₁ and L₁₀₁ are rewritten in the duration of the pulse P₁. Similarly, the scanning lines L₃ and L₁₀₃ are rewritten in the duration of the pulse P₃. Thus, the scanning lines of odd number L₁, L₃, ... L₉₉, and L₁₀₁, L₁₀₃, ... L₁₉₉ are rewritten in the first frame, and the scanning lines of even number L₂, L₄, ... L₁₀₀, and L₁₀₂, L₁₀₄, ... L₂₀₀ are rewritten in the second frame. In the third frame, the same scanning electrodes as in the first frame are rewritten.

In the second embodiment shown in Fig. 3, the number of scanning electrodes in each group K′ is assumed to be 2 so that a picture is completed in two frames. It should be understood that the second embodiment shown in Fig. 3 can be modified easily to set K′ to any desired value other than 2.

The effect of the present invention with K (or K′) = 2 as shown in Figs. 1 and 3 is explained with reference to Fig. 6. When a figure "1" is kept written on the display screen, the luminance of the figure on the scanning electrodes L₁, L₂, L₃ and L₄ is shown in Figs. 6(1), 6(2), 6(3) and 6(4). The combined luminance of the 4 (vertical) × 4 (horizontal) picture elements is shown in Fig. 6(5). It means that the apparent frequency for rewriting the entire image is 50 Hz although each scanning line is rewritten at 25 Hz. According to the present invention, therefore, flicker decreases and the picture quality improves compared with the picture by the conventional device in which an entire picture is rewritten at 25 Hz. With K = 2, every other scanning line is rewritten in each frame. With K = 3, every third line is rewritten in each frame.

According to the present invention, as mentioned above, the display device which provides an incomplete memory characteristic and takes a specified time to rewrite the picture elements in one horizontal scanning period decreases flicker by increasing the apparent speed of rewriting the picture elements. This results in improved picture quality.

In the above embodiments of the present invention, it is assumed that the number of effective scanning lines in the effective display region is M. The total number of scanning lines in the display device may be greater than M. For M = 200, for instance, the total number of scanning line may be, say, 262.

While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the present invention as claimed.