(19)
(11) EP 0 307 831 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
27.12.1990 Bulletin 1990/52

(43) Date of publication A2:
22.03.1989 Bulletin 1989/12

(21) Application number: 88114838.1

(22) Date of filing: 10.09.1988
(51) International Patent Classification (IPC)4: G06F 7/50
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 14.09.1987 US 95969

(71) Applicant: Hughes Aircraft Company
Los Angeles, California 90045-0066 (US)

(72) Inventors:
  • Shahriary, Iradj
    Santa Monica, CA 90403 (US)
  • des Brisay, George S., Jr.
    Hemet, CA 92344 (US)
  • Avery Susan K.
    Altadena, CA 91001 (US)

(74) Representative: Witte, Alexander, Dr.-Ing. 
Witte, Weller, Gahlert, Otten & Steil, Patentanwälte, Rotebühlstrasse 121
70178 Stuttgart
70178 Stuttgart (DE)


(56) References cited: : 
   
       


    (54) High speed adder


    (57) An improved cascadable adder (11) is disclosed which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be implemented in gallium arsenide technology and includes a first circuit (13) for exclusive ORing first bits (A₁, B₁) of first and second digital words (A₁, B₁) respectively; and a second circuit (37) operatively connected to the first circuit (13) for generating, with only two gate delays, a carry (C₁) associated with the summing of the first bits.







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