(19)
(11) EP 0 310 111 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
19.09.1990 Bulletin 1990/38

(43) Date of publication A2:
05.04.1989 Bulletin 1989/14

(21) Application number: 88116182.2

(22) Date of filing: 30.09.1988
(51) International Patent Classification (IPC)4: G11C 29/00
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 02.10.1987 JP 249162/87

(71) Applicant: HITACHI, LTD.
Chiyoda-ku, Tokyo 101 (JP)

(72) Inventors:
  • Hatayama, Kazumi
    Hitachi-shi (JP)
  • Hayashi, Terumine
    Hitachi-shi (JP)

(74) Representative: Beetz & Partner Patentanwälte 
Steinsdorfstrasse 10
80538 München
80538 München (DE)


(56) References cited: : 
   
       


    (54) Memory incorporating logic LSI and method for testing the same LSI


    (57) This invention relates to a memory incorporating logic LSI and a method for testing the same LSI. Signal path switching circuit portions (50, 51) are disposed in the course of a memory portion (30) and a logic circuit portion (20) so that a test signal input and an output signal can be observed at the input and output terminal portion (40) so as to be able to effect a dynamic function test of the memory portion (30). Further there is disposed a logic circuit testing signal memory circuit portion (80), which switches over the signal path switch­ing circuit portions (50, 51) to the logic circuit portion (20) so as to be able to effect a test of the logic circuit portion (20), independently of the state of the memory portion (30)







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